WO2005060586A2 - Structures de contact d'un dispositif electronique - Google Patents

Structures de contact d'un dispositif electronique Download PDF

Info

Publication number
WO2005060586A2
WO2005060586A2 PCT/US2004/040900 US2004040900W WO2005060586A2 WO 2005060586 A2 WO2005060586 A2 WO 2005060586A2 US 2004040900 W US2004040900 W US 2004040900W WO 2005060586 A2 WO2005060586 A2 WO 2005060586A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
led
light
conductive
patterned
Prior art date
Application number
PCT/US2004/040900
Other languages
English (en)
Other versions
WO2005060586A3 (fr
Inventor
Alexei A. Erchak
Eleftrios Lidorikis
John W. Graff
Original Assignee
Luminus Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/735,498 external-priority patent/US7166871B2/en
Priority claimed from US10/794,244 external-priority patent/US20040259279A1/en
Priority claimed from US10/794,452 external-priority patent/US7074631B2/en
Priority claimed from US10/871,877 external-priority patent/US7105861B2/en
Application filed by Luminus Devices, Inc. filed Critical Luminus Devices, Inc.
Publication of WO2005060586A2 publication Critical patent/WO2005060586A2/fr
Publication of WO2005060586A3 publication Critical patent/WO2005060586A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0083—Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • a light emitting diode often can provide light in a more efficient manner than an incandescent light source and/or a fluorescent light source.
  • the relatively high power efficiency associated with LEDs has created an interest in using LEDs to displace conventional light sources in a variety of lighting applications. For example, in some instances LEDs are being used as traffic lights and to illuminate cell phone keypads and displays.
  • an LED is formed of multiple layers, with at least some of the layers being formed of different materials. In general, the materials and thicknesses selected for the layers determine the wavelength(s) of light emitted by the LED.
  • the chemical composition of the layers can be selected to try to isolate injected electrical charge carriers into regions (commonly refened to as quantum wells) for relatively efficient conversion to optical power.
  • the layers on one side of the junction where a quantum well is grown are doped with donor atoms that result in high electron concentration (such layers are commonly refened to as n- type layers), and the layers on the opposite side are doped with acceptor atoms that result in a relatively high hole concentration (such layers are commonly refened to as p-type layers).
  • a common approach to preparing an LED is as follows. The layers of material are prepared in the form of a wafer.
  • the layers are formed using an epitaxial deposition technique, such as metal-organic chemical vapor deposition (MOCVD), with the initially deposited layer being formed on a growth substrate.
  • MOCVD metal-organic chemical vapor deposition
  • the layers are then exposed to various etching and metallization techniques to form contacts for electrical cunent injection, and the wafer is subsequently sectioned into individual LED chips.
  • the LED chips are packaged.
  • electrical energy is usually injected into an LED and then converted into electromagnetic radiation (light), some of which is extracted from the LED.
  • the invention features an optical display system that includes a microdisplay having a surface and a light emitting device.
  • the light emitting device includes a multi-layer stack of materials including a light generating region, and a first layer supported by the light generating region.
  • a surface of the first layer is configured so that the light generated by the light generating region can emerge from the light emitting device via the surface of the first layer.
  • the ratio of the aspect ratio of the surface of the microdisplay and the aspect ratio of the surface of the first layer is at most about two.
  • the invention features an optical display system that includes a microdisplay, a light emitting device, and at least one optical component disposed along an optical path from the microdisplay to the light emitting device.
  • the microdisplay, the light emitting device and the optical component are positioned so that, during use, an image plane of the system does not coincide with a surface of the microdisplay illuminated by light emitted by the light emitting device.
  • the invention features a method of illuminating a microdisplay using a plurality of light emitting devices. The method includes activating the plurality of light emitting devices so that at least one of the plurality of light emitting devices has an activation time that is different from an activation time of at least one of the other light emitting devices in the plurality of light emitting devices.
  • the invention features an optical display system that includes a LED and a cooling system that is configured so that, during use, the cooling system regulates a temperature of the light emitting diode.
  • the invention features a light emitting device that includes a multi-layer stack of materials.
  • the multi-layer stack of materials includes a light generating region, and a first layer supported by the light generating region.
  • the surface of the first layer is configured so that the light generated by the light generating region can emerge from the light emitting device via the surface of the first layer.
  • the surface of the first layer has a contact region configured so that, during use, at most about 20% an area of a microdisplay illuminated by the light emitting diode comprises dark spots formed due to the contact region.
  • the invention features an optical display system that includes a plurality of light emitting diodes, a microdisplay, at least one optical component disposed along an optical path from the microdisplay to the light emitting diode, and a beam aggregation device configured to combine light generated by the plurality of light emitting diodes.
  • the invention features a system that includes a light emitting device.
  • the light emitting device includes a rectangular multi-layer stack of materials including a light generating region, and a first layer supported by the light generating region.
  • the surface of the first layer is configured so that light generated by the light generating region can emerge from the light emitting device via the surface of the first layer
  • the light emitting device also includes at least one electrical contact pad disposed along an edge of the surface of the first layer, and a package.
  • the package includes a plurality of plated regions for providing electrical contact to the light emitting device, a plurality of castellations to provide electrical contact from one surface of the package to the opposite surface of the package, and a plurality of wire bonds connected between the plated regions and the at least one electrical contact pad.
  • the invention features a device that includes a material body designed for use in an electronic device, and a contact stracture supported by the surface of the material body.
  • the contact structure includes a patterned conductive layer and a patterned insulating layer.
  • the patterned insulating layer is disposed between the interior portion of the patterned conductive layer and the surface of the material body.
  • the insulating layer is patterned such that the conductive layer extends past all edges of the insulating layer to form an electrical contact to the material body.
  • the invention features a device that includes a semiconductor die.
  • the device also includes a conductive pad disposed along one side of a surface layer of the semiconductor die and another conductive pad disposed along the opposite side of the surface layer of the semiconductor die.
  • the device further includes a plurality of conductive contacts in electrical contact with at least one of the conductive pads and extending from at least one of the conductive pads toward a central area of the semiconductor die.
  • the device also includes an insulating layer disposed between an interior portion of at least some of the plurality of conductive contacts and the top layer of the semiconductor die.
  • the invention features a device that includes a rectangular light emitting diode (LED).
  • the device also includes a conductive pad disposed along one side of a surface layer of the rectangular LED and another conductive pad disposed along the opposite side of the surface layer of the rectangular LED.
  • the device further includes a plurality of conductive contacts in electrical contact with at least one of the conductive pads and extending from at least one of the conductive pads toward a central area of the rectangular LED.
  • the invention features a device that includes a stack of materials and a contact structure disposed on the surface of the stack of materials.
  • the contact stracture includes a patterned conductive layer and a patterned insulating layer disposed between the patterned conductive layer and the surface of the stack of materials.
  • the pattemed conductive layer and the patterned insulating layer are configured such that during use a voltage drop across the patterned conductive layer is about the same at a plurality of segments disposed along the length of the patterned conductive layer.
  • the invention features a device that includes a stack of materials and a contact stracture disposed on the surface of the stack of materials.
  • the contact stmcture includes a patterned conductive layer configured such that during use a heat generation across the patterned conductive layer is about the same at a plurality of segments disposed across the patterned conductive layer.
  • a light-emitting system can include an LED and/or a relatively large LED chip that can exhibit relatively high light extraction.
  • a light-emitting system can include an LED and/or a relatively large LED chip that can exhibit relatively high surface brightness, relatively high average surface brightness, relatively low need for heat dissipation or relatively high rate of heat dissipation, relatively low etendue and or relatively high power efficiency.
  • a light-emitting system can include an LED and/or a relatively large LED chip that can be designed so that relatively little light emitted by the LED/LED chip is absorbed by packaging.
  • a light-emitting system can include a packaged LED (e.g., a relatively large packaged LED) that can be prepared without using an encapsulant material. This can result in a packaged LED that avoids certain problems associated with the use of certain encapsulant materials, such as reduced performance and/or inconsistent performance as a function of time, thereby providing a packaged LED that can exhibit relatively good and/or reliable performance over a relatively long period of time.
  • a light-emitting system can include an LED (e.g., a packaged LED, which can be a relatively large packaged LED) that can have a relatively uniform coating of a phosphor material.
  • a light-emitting system can include an LED (e.g., a packaged LED, which can be a relatively large packaged LED) that can be designed to provide a desired light output within a particular angular range (e.g., within a particular angular range relative to the LED surface normal).
  • a light-emitting system can include an LED and/or a relatively large LED chip that can be prepared by a process that is relatively inexpensive.
  • a light-emitting system can include an LED and/or a relatively large LED chip that can be prepared by a process that can be conducted on a commercial scale without incurring costs that render the process economically unfeasible.
  • using a rectangular shape for an LED can provide certain advantages.
  • the advantages can include one or more of the following.
  • the rectangular LED can allow a greater number of wire bonds per unit area increasing the power that can be input into the LED.
  • the rectangular shape can be chosen to match a particular aspect ratio of a pixel or microdisplay, thus, eliminating the need for complex beam shaping optics.
  • the rectangular shape can also improve heat dissipation from the LED and reduce the likelihood of failure due to the device overheating. Also, because the cross section of an individual LEDs cut from a wafer is only slightly larger than the light-emitting surface area of the LED, many individual, and separately addressable LEDs can be packed closely together in an anay. If one LED does not function (e.g., due to a large defect), then it does not significant diminish the performance of the anay because the individual devices are closely packed.
  • FIG. 1 is a schematic representation of a light emitting system.
  • FIG. 2A-2D are schematic representations of optical display systems.
  • FIG. 3 is a schematic representation of an optical display system.
  • FIG. 4A is a schematic representation of a top view of an LED.
  • FIG. 4B is a schematic representation of an optical display system.
  • FIG. 5 is a schematic representation of an optical display system.
  • FIG. 6 is a schematic representation of an optical display system.
  • FIG. 7 is a schematic representation of an optical display system.
  • FIGS. 8A and 8B are schematic representations of an optical display system.
  • FIG. 9 is a schematic representation of an optical display system.
  • FIG. 10 is a schematic representation of an optical display system.
  • FIG. 11 is a schematic representation of an optical display system.
  • FIG. 12 is a cross-sectional view of an LED with a patterned surface.
  • FIG. 13 is a top view the patterned surface of the LED of FIG 2.
  • FIG. 14 is a graph of an extraction efficiency of an LED with a patterned surface as function of a detuning parameter.
  • FIG. 15 is a schematic representation of the Fourier transformation of a patterned surface of an LED.
  • FIG. 16 is a graph of an extraction efficiency of an LED with a patterned surface as function of nearest neighbor distance.
  • FIG. 17 is a graph of an extraction efficiency of an LED with a patterned surface as function of a filling factor.
  • FIG. 18 is a top view a patterned surface of an LED.
  • FIG. 19 is a graph of an extraction efficiency of LEDs with different surface patterns.
  • FIG. 20 is a graph of an extraction efficiency of LEDs with different surface patterns.
  • FIG. 21 is a graph of an extraction efficiency of LEDs with different surface patterns.
  • FIG. 22 is a graph of an extraction efficiency of LEDs with different surface patterns.
  • FIG. 23 is a schematic representation of the Fourier transformation two LEDs having different patterned surfaces compared with the radiation emission spectmm of the LEDs.
  • FIG. 24 is a graph of an extraction efficiency of LEDs having different surface patterns as a function of angle.
  • FIG 25 is a side view of an LED with a patterned surface and a phosphor layer on the patterned surface.
  • FIG. 26 is a cross-sectional view of a multi-layer stack.
  • FIG. 27 is a cross-sectional view of a multi-layer stack.
  • FIG 28 is a cross-sectional view of a multi-layer stack.
  • FIG 29 is a cross-sectional view of a multi-layer stack.
  • FIG. 30 depicts a side view of a substrate removal process.
  • FIG. 31 is a partia cross-sectional view of a multi-layer stack
  • FIG. 32 is a partia cross-sectional view of a multi-layer stack
  • FIG 33 is a partia cross-sectional view of a multi-layer stack
  • FIG. 34 is a partia cross-sectional view of a multi-layer stack
  • FIG. 35 is a partia cross-sectional view of a multi-layer stack
  • FIG. 36 is a partia cross-sectional view of a multi-layer stack
  • FIG. 31 is a partia cross-sectional view of a multi-layer stack
  • FIG. 32 is a partia cross-sectional view of a multi-layer stack
  • FIG 33 is a partia cross-sectional view of a multi-layer stack
  • FIG. 37 is a partia cross-sectional view of a multi-layer stack
  • FIG. 38 is a partia cross-sectional view of a multi-layer stack
  • FIG. 39 is a partia cross-sectional view of a multi-layer stack
  • FIG. 40 is a partia cross-sectional view of a multi-layer stack
  • FIG. 41 is a partia cross-sectional view of a multi-layer stack
  • FIG. 42 is a partia cross-sectional view of a multi-layer stack.
  • FIG. 43 is a partial cross-sectional view of a multi-layer stack.
  • FIG. 44 is a partial cross-sectional view of a multi-layer stack.
  • FIG. 45 A is a perspective view of an LED.
  • FIG. 45B is a top view of an LED.
  • FIG. 46 A is a top view of an LED.
  • FIG. 46B is a partial cross-sectional view of an LED.
  • FIG. 46C is an equivalent circuit diagram.
  • FIG. 47A is a top view of an LED.
  • FIG. 47B is an equivalent circuit diagram.
  • FIG. 48 A is a top view of an LED.
  • FIG 48B is an equivalent circuit diagram.
  • FIG 49A is a top view of an LED.
  • FIG. 49B is a partial cross-sectional view of an LED.
  • FIG. 49C is a partial cross-sectional view of an LED.
  • FIG. 50 is a graph of junction cunent density.
  • FIG. 51 A is a top view of a multi-layer stack.
  • FIG. 5 IB is a partial cross-sectional view of an LED.
  • FIG. 52 is a view of a contact.
  • FIG. 53 is a diagram of a packaged LED.
  • FIG. 54 is a diagram of a packaged LED and a heat sink.
  • FIG. 1 is a schematic representation of a light-emitting system 50 that has an anay 60 of LEDs 100 inco ⁇ orated therein. Anay 60 is configured so that, during use, light that emerges from LEDs 100 (see discussion below) emerges from system 50 via surface 55.
  • light-emitting systems include projectors (e.g., rear projection projectors, front projection projectors), portable electronic devices (e.g., cell phones, personal digital assistants, laptop computers), computer monitors, large area signage (e.g., highway signage), vehicle interior lighting (e.g., dashboard lighting), vehicle exterior lighting (e.g., vehicle headlights, including color changeable headlights), general lighting (e.g., office overhead lighting), high brightness lighting (e.g., streetlights), camera flashes, medical devices (e.g., endoscopes), telecommunications (e.g. plastic fibers for short range data transfer), security sensing (e.g.
  • projectors e.g., rear projection projectors, front projection projectors
  • portable electronic devices e.g., cell phones, personal digital assistants, laptop computers
  • computer monitors large area signage (e.g., highway signage), vehicle interior lighting (e.g., dashboard lighting), vehicle exterior lighting (e.g., vehicle headlights, including
  • biometrics biometrics
  • integrated optoelectronics e.g., intrachip and interchip optical interconnects and optical clocking
  • military field communications e.g., point to point communications
  • biosensing e.g. photo-detection of organic or inorganic substances
  • photodynamic therapy e.g. skin treatment
  • night-vision goggles solar powered transit lighting, emergency lighting, ai ⁇ ort runway lighting, airline lighting, surgical goggles, wearable light sources (e.g. life-vests).
  • An example of a rear projection projector is a rear projector television.
  • An example of a front projection projector is a projector for displaying on a surface, such as a screen or a wall.
  • a laptop computer can include a front projection projector.
  • surface 55 is formed of a material that transmits at least about 20% (e.g., at least about 30%, at least about 40%, at least about 50%, at least about 60%, at least about 70%, at least about 80%, at least about 90%, at least about 95%) of the light that emerges from LEDs 100 and impinges on surface 55.
  • materials from which surface 55 can be formed include glass, silica, quartz, plastic, and polymers.
  • An example is time- sequencing of substantially monochromatic sources (e.g. LEDs) in display applications (e.g., to achieve vibrant full-color displays).
  • Another example is in telecommunications where it can be advantageous for an optical system to have a particular wavelength of light travel from the source to the light guide, and from the light guide to the detector.
  • a further example is vehicle lighting where color indicates signaling.
  • An additional example is in medical applications (e.g., photosensitive drag activation or biosensing applications, where wavelength or color response can be advantageous).
  • the light that emerges e.g., total light intensity, light intensity as a function of wavelength, and/or peak emission wavelength
  • the light that emerges e.g., total light intensity, light intensity as a function of wavelength, and/or peak emission wavelength
  • An example is in general lighting (e.g., where multiple wavelengths can improve the color rendering index (CRI)).
  • CRI is a measurement of the amount of color shift that objects undergo when lighted by the light-emitting system as compared with the color of those same objects when seen under a reference lighting system (e.g., daylight) of comparable conelated temperature.
  • LEDs 100 can be configured differently. As an example, in some embodiments, system 50 includes a single LED 100.
  • the anay is curved to help angularly direct the light from various sources onto the same point (e.g., an optic such as a lens).
  • the anay of devices is hexagonally distributed to allow for close-packing and high effective surface brightness.
  • the devices are distributed around a minor (e.g., a dichroic minor) that combines or reflects light from the LEDs in the anay.
  • a minor e.g., a dichroic minor
  • the light that emerges from LEDs 100 is shown as traveling directly from LEDs 100 to surface 55. However, in some embodiments, the light that emerges from LEDs 100 can travel an indirect path from LEDs 100 to surface 55.
  • system 50 includes a single LED 100.
  • light from LEDs 100 is focused onto a microdisplay (e.g., onto a light valve such as a digital light processor (DLP) or a liquid crystal display (LCD)).
  • a microdisplay e.g., onto a light valve such as a digital light processor (DLP) or a liquid crystal display (LCD)
  • DLP digital light processor
  • LCD liquid crystal display
  • light is directed through ⁇ various optics, minors or polarizers (e.g., for an LCD).
  • light is projected through primary or secondary optics, such as, for example, a lens or a set of lenses.
  • FIG. 2 A shows an optical display system 1100 (see discussion above) including a non-Lambertian LED 1110 (see discussion below), a lens 1120 and a microdisplay 1130.
  • LED 1110 is spaced a distance LI from lens 1120
  • microdisplay 1130 is spaced a distance L2 from lens 1120.
  • Distances LI and L2 are selected so that, for light emitted by LED 1110 that impinges on lens 1120, the image plane of lens 1120 coincides with the surface of microdisplay 1130 on which the light emitted by LED 1110 impinges.
  • system 1100 can use the light emitted by LED 1110 to relatively efficiently illuminate the surface of microdisplay 1130 with the shape of the surface of LED 1110 that emits light being about the same as the shape of the surface of 1130 that is illuminated by the light emitted by LED 1110.
  • the ratio the aspect ratio of LED 1110 to the aspect ratio of microdisplay 1130 can be from about 0.5 to about 2 (e.g., from about 9/16 to about 16/9, from about 3/4 to about 4/3, about 1).
  • the aspect ratio of microdisplay 1130 can be, for example, 1920x1080, 640x480, 800x600, 1024x700, 1024x768, 1024x720, 1280x720, 1280x768, 1280x960, or 1280x1064.
  • the surface of microdisplay 1130 and/or the surface of LED 1110 can have any desired shape. Examples of such shapes include square, circular, rectangular, triangular, trapezoidal, and hexagonal.
  • an optical display system can relatively efficiently illuminate the surface of microdisplay 1130 without a lens between LED 1110 and microdisplay 1130 while still having the shape of the surface of LED 1110 that emits light being about the same as the shape of the surface of 1130 that is illuminated by the light emitted by LED 1110.
  • FIG. 2B shows a system 1102 in which a square LED 1110 is imaged onto a square microdisplay 1130 without having a lens between LED 1110 and microdisplay 1130.
  • FIG. 2C shows an optical display system 1104 in which a rectangular LED 1110 can be imaged onto a rectangular microdisplay 1130 (with a similarly proportioned aspect ratio) without having a lens between LED 1110 and microdisplay 1130.
  • an anamo ⁇ hic lens can be disposed between LED 1110 and microdisplay 1130. This can be desirable, for example, when the aspect ratio of LED 1110 is substantially different from the aspect ratio of microdisplay 1130.
  • FIG 2D shows a system 1106 that includes LED 1110 having a substantially square shaped surface, microdisplay 1130 having a substantially rectangular shaped surface (e.g., an aspect ratio of about 16:9 or about 4:3), and an anamo ⁇ hic lens 1120 disposed between LED 1110 and microdisplay 1130.
  • anamo ⁇ hic lens 1120 can be used to convert the shape of the light emitted by LED 1110 to substantially match the shape of the surface of microdisplay 1130. This can enhance the efficiency of the system by increasing the amount of light emitted by the surface of LED 1110 that impinges upon the surface of microdisplay 1130.
  • FIG. 3 shows an optical display system 1200 including LED 1110, lens 1120, and microdisplay 1130.
  • the light emitting surface of LED 1110 has contact regions to which electrical leads 1115 are attached (see discussion below).
  • LED 1110 is spaced a distance L3 from lens 1 120
  • microdisplay 1130 is spaced a distance L4 from lens 1120.
  • Leads 1115 block light from being emitted from the contact regions of LED 1110. If the plane of the surface of microdisplay 1130 on which the light emitted by LED 1110 impinges coincides with the image plane of lens 1120, a set of dark spots 1202 conesponding to the contact region of the light emitting surface of LED 1110 can appear on this surface of microdisplay 1130.
  • distances L3 and L4 are selected so that, for light emitted by LED 1110 that impinges on lens 1120, the image plane of lens 1120 does not coincide with the plane of the surface of microdisplay 1130 on which the light emitted by LED 1110 impinges (i.e., there exists a distance, ⁇ L, between the image plane of lens 1 120 and the plane of the surface of microdisplay 1130 on which the light emitted by LED 1110 impinges).
  • the light from LED 1 1 10 is defocused in the plane of the surface of microdisplay 1130 on which the light emitted by LED 1110 impinges, and the resulting intensity of light is more uniform on this surface of microdisplay 1130 than in the image plane of lens 1 120.
  • the total distance between the LED and the microdisplay 1 130 can be represented as the distance between the LED 1110 and the image plane 1 120 (L5) plus the distance, ⁇ L.
  • ⁇ L is increased by increasing the distance between the LED 11 10 and the microdisplay 1130, the intensity of dark spots decreases but the intensity of light emitted by LED 1110 that impinges on the surface of microdisplay 1 130 decreases.
  • the intensity is greater than the intensity at the image plane, but the microdisplay may be only partially illuminated.
  • the absolute value of ⁇ L/L5 is from about 0.00001 to about 1 (e.g., from about 0.00001 to about 0.1, from about 0.00001 to about 0.01, from about 0.00001 to about 0.001), or from about .00001 to about .0001)
  • multiple LEDs may be used to illuminate a single microdisplay (e.g., a 3x3 matrix of LEDs).
  • Such a system can be desirable because, when multiple LEDs are ananged to illuminate a single microdisplay, if one LEDs fails, the system would still be useable (however a dark spot may occur due to the absence of light from the particular LED).
  • the optical system can be configures so that dark spots do not appear on the surface of the microdisplay.
  • the microdisplay can be translated outside of the image plane such that the area between the LEDs does not result in a dark spot.
  • the intensity of dark spots on the surface of microdisplay 1130 can be reduced by appropriately configuring the contact region of the surface of LED 1110.
  • FIG 4A shows a top view of an LED 1110 with a contact region disposed around the perimeter of LED 1110.
  • the optical display system can be configured (e.g., by properly sizing the area of the surface of microdisplay 1130) so that the intensity of the dark spots created by the contact region of the surface of LED 1110 on surface 1130 is relatively small.
  • This approach may be used with systems that include multiple LEDs (e.g., a 3x3 matrix of LEDs).
  • FIG. 4B shows an optical display system 300 that includes LED 1110 and microdisplay 1130.
  • LED 11 10 includes a contact region formed by leads 1115 that is selected so that dark spots 1202 appear at a region not imaged on the surface of microdisplay 1130.
  • the surface of microdisplay 1130 can be located at the image plane of lens 1120 because the dark spots fall outside of the area imaged on the microdisplay at the image plane of lens 1120.
  • leads 1115 can be disposed, for example, on the surface of LED 1110 around its perimeter.
  • the area inside the contact region of surface 1110 matches (e.g., the aspect ratio is similar) to the surface of microdisplay 1130.
  • FIG 5 shows an optical display system 1700 that includes LED 1110 and microdisplay 1130.
  • LED 1110 also includes a contact region formed by leads 1115 and a homogenizer 1702 (also refened to as a light tunnel or light pipe) that guides light emitted from LED 1110 to a lens 1120.
  • a homogenizer 1702 also refened to as a light tunnel or light pipe
  • Total internal reflection of the light emitted by LED 1110 off the inside surfaces of homogenizer 1702 can generate a substantially uniform output distribution of light and can reduce the appearance of dark spots caused by leads 1115 so that microdisplay 1130 is substantially uniformly illuminated by LED 1110 (e.g., an image generated in an image plane 1131 is substantially uniform).
  • system 1700 can include one or more additional optical components.
  • optical display system 1700 can also include a lens disposed in the path prior to the homogenizer to focus light into the homogenizer.
  • the aspect ratio of the aperture of homogenizer 1702 matches that of LED 1110 such that when LED 1110 is mounted in close proximity to homogenizer 1702, additional lenses may not be necessary or such that more efficient coupling of light into homogenizer 1702 is possible with a lens prior to homogenizer 1702.
  • FIG. 6 shows an optical display system 1710 that includes LED 1110 and microdisplay 1130.
  • LED 1110 also includes a contact region formed by leads 1115 and a set of multiple lenses 1712 that are disposed between LED 1110 and lens 1120.
  • Lenses 1712 can vary in size, shape, and number. For example, the number and size of lenses 1712 can be proportional to the cross- sectional area of LED 1110. In some embodiments, lenses 1712 include a set of between about 1 and about 100 lenses with sizes varying of, for example, from about 1 mm to about 10 cm. The light emitted by LED 1110, enters lenses 1712 and is refracted. Since the surfaces of lenses 1712 are curved, the light refracts at different angles causing the beams emerging from lenses 1712 to overlap. The overlapping of the beams reduces the appearance of dark spots caused by leads 1115 so that microdisplay 1130 is substantially uniformly illuminated by LED 1110 (e.g., an image generated in an image plane 1131 is substantially uniform).
  • optical display systems have been described as including a single lens, in some embodiments, multiple lenses can be used. Further, in certain embodiments, one or more optical components other than lens(es) can be used. Examples of such optical components include minors, reflectors, collimators, beam splitters, beam combiners, dichroic minors, filters, polarizers, polarizing beam splitters, prisms, total internal reflection prisms, optical fibers, light guides and beam homogenizers. The selection of appropriate optical components, as well as the conesponding anangement of the components in the system, is known to those skilled in the art.
  • FIG. 7 shows a system 1500 that includes a blue LED 1410 (an LED with a dominant output wavelength from about 450 to about 480 nm), a green LED 1420 (an LED with a dominant output wavelength from about 500 to about 550 nm), and a red LED 1430 (an LED with a dominant output wavelength from about 610 to about 650 nm) which are in optical communication with the surface of microdisplay 1130.
  • LEDS 1410, 1420, and 1430 can be ananged to be activated simultaneously, in sequence or both.
  • LEDs 1410, 1420, and 1430 are activated in sequence.
  • a viewer's eye generally retains and combines the images produced by the multiple colors of LEDs. For example, if a particular pixel (or set of pixels) or microdisplay (or portion of a microdisplay) of a frame is intended to be pu ⁇ le in color, the surface of the microdisplay can be illuminated with red LED 1430 and blue LED 1410 during the appropriate portions of a refresh cycle. The eye of a viewer combines the red and the blue and "sees" a pu ⁇ le microdisplay.
  • a refresh cycle having an appropriate frequency can be used.
  • LEDs 1410, 1420 and 1430 may have varying intensities and brightness.
  • green LED 1420 may have a lower efficiency than red LED 1430 or blue LED 1410. Due to a particular LED (e.g., green LED 1420) having a lower efficiency, it can be difficult to illuminate the surface of the microdisplay with a sufficiently high brightness of the color of light (e.g., green) emitted by the relatively low efficiency LED (e.g., LED 1420).
  • the activation cycles for the multiple LEDs can be adjusted.
  • the least efficient LED may be allocated a longer activation time (i.e., on for a longer period of time) than the more efficient LEDs.
  • the cycle may be in the ratio of 1/6:2/3:1/6 (red:green:blue).
  • the cycle may be in the ratio of 0.25:0.45:0.30 (red: green :blue).
  • the duty cycle dedicated to the activation of the green LED may be further increased.
  • the duty cycle dedicated to imaging the green LED 1420 can be greater than about 40% (e.g., greater than about 45%, greater than about 50%, greater than about 60%, greater than about 70%, greater than about 80%, greater than about 90%).
  • the duty cycle for each LED is different.
  • the duty cycle for red LED 1430 can be greater than the duty cycle for blue LED 1410. While systems have been described in which the activation cycle is selected based on the intensity and/or brightness of an LED, in some systems the activation time of an LED may be selected based on one or more other parameters.
  • the activation time of the least efficient light emitting device is at least about 1.25 times (e.g., at least about 1.5 times, at least about 2 times, at least about 3 times) the activation time of another light emitting device.
  • FIG. 8A shows an embodiment of a liquid crystal display (LCD) based optical display system 1720 including blue LED 1410, green LED 1420, and red LED 1430 (e.g., as described above) which are in optical communication with the surface of associated LCD panels 1728, 1730, and 1732.
  • Optical display system 1720 also includes lenses 1722, 1724, and 1726 in a conesponding optical path between LEDs 1410, 1420, and 1430 and associated LCD panels 1728, 1730, and 1732.
  • Lenses 1722, 1724, and 1726 focus the light onto associated LCD panels 1728, 1730, and 1732.
  • Optical display system 1720 further includes a device 1734 (e.g., an x-cube) that combines multiple beams of light from LCD panels 1728, 1730, and 1732 into a single beam 1736 (indicated by anows) that can be directed to a projection lens 1735 or other display
  • a device 1734 e.g., an x-cube
  • optical display system 1720 can include a polarizer that transmits a desired polarization (e.g. the 'p' polarization) while reflecting another polarization (e.g. the V polarization).
  • the polarizer can be disposed in the path between LEDs 1410, 1420, and 1430 and associated lenses 1722, 1724, and 1726, between lenses 1722, 1724, and 1726 and the associated LCD panels 1728, 1730, and 1732, or in other locations along the optical path.
  • the aspect ratio of an LED e.g., LED 1430
  • the microdisplay e.g., microdisplay 1732
  • DLP digital light processor
  • a digital light processor (DLP) based optical display system 1750 including blue LED 1410, green LED 1420, and red LED 1430 (as described above) which are each in optical communication with associated lenses 1722, 1724, and 1726 (as described above).
  • Light emitted from LEDs 1410, 1420, and 1430 passes through the associated lenses 1722, 1724, and 1726 and is collected by a device 1734 (e.g., an x-cube) that combines multiple beams of light emitted by LEDs 1410, 1420, and 1430 into a single beam that can be directed to a total internal reflection (TIR) prism 1752.
  • TIR total internal reflection
  • the light emerging from x-cube 1734 can be directed to TIR prism 1752 by a minor 1754 or other device such as a light guide.
  • TIR prism 1752 reflects light and directs the light to a DLP panel 1756.
  • DLP panel 1756 includes a plurality of minors that can be actuated to generate a particular image.
  • a particular minor can either reflect light 1760 (indicated by anows) such that the light is directed to a projection 1755 or can cause the light to be reflected away from projection lens 1755.
  • the combination of the LEDs 1410, 1420, and 1430 and DLP panel 1756 allow greater control of the signal.
  • the amount of data sent to DLP panel 1756 can be reduced (allowing greater switching frequency) by switching on and off LEDs 1410, 1420, and 1430 in addition to the minors in DLP panel 1756.
  • red LED 1430 can be switched off eliminating the need to send a signal to DLP 1752 to switch the associated minor.
  • the ability to modulate the LEDs can improve for example color quality, image quality, or contrast.
  • FIG. 10 shows a particular embodiment of a liquid crystal on silicon (LCOS) based optical display system 1770 including blue LED 1410, green LED 1420, and red LED 1430 (as described above) which are each in optical communication with an associated polarizing beam splitter 1774, 1778, and 1782.
  • LCOS liquid crystal on silicon
  • Light emitted from LEDs 1410, 1420, and 1430 passes through the associated polarizing beam splitters 1774, 1778, and 1782 and is projected onto an associated LCOS panel 1772, 1776, or 1780. Since LCOS panels 1772, 1776, and 1780 are not sensitive to all polarizations of light, the polarizing beam splitters 1774, 1778, and 1782 polarize the light to a particular polarization (e.g., by transmitting a desired polarization (e.g., the 'p' polarization) while reflecting another polarization (e.g., the 's' polarization) the polarization of some light and pass other polarizations) based on the sensitivity of LCOS panels 1772, 1776, and 1780.
  • a desired polarization e.g., the 'p' polarization
  • another polarization e.g., the 's' polarization
  • the light reflected from LCOS panels 1772, 1776, and 1780 is collected by a device 1734 (e.g., an x-cube) that combines the beams of light from the multiple LCOS panels 1772, 1776, and 1780 to generate a beam 1790 (indicated by arrows) that is directed to a projection lens 1795.
  • a device 1734 e.g., an x-cube
  • the optical display system includes red, green, and blue light emitting devices, other colors and combinations are possible.
  • the system need not have only three colors. Additional colors such as yellow may be included and allocated a portion of the duty cycle. Alternately, multiple LEDs having different dominant wavelengths may be optically combined to produce a resulting color.
  • a blue-green LED e.g., an LED with a dominant wavelength between the wavelength of blue and green
  • a yellow LED to produce 'green' light.
  • the number of LEDs and the color of each LED can be selected as desired. Additional microdisplays can also be included.
  • the duty cycle for the lesser efficient LED e.g. green
  • sending only the difference in image information from the previous image rather than the total information required to reconstruct each image allows an increase in the data rate. Using this method, less data needs to be sent allowing for higher data rates and reduced duty cycles for complementary colors for a given refresh cycle.
  • optical componentry may or may not be present along the light path between one or more of the LEDs and the microdisplay.
  • an x-cube or a set of dichroic minors may be used to combine light from the multiple LEDs onto a single microdisplay.
  • different optical componentry can be used for each LED (e.g. if the surface of the LEDs are of different size or shape), or the same optical componentry can be used for more than one LED.
  • differing brightness for a particular color based on the desired chromaticity of an image may be obtained by illuminating the display for a portion of the activation time allocated to the particular LED. For example, to obtain an intense blue, the blue LED can be activated for the entire activation time and for a less intense blue, the blue LED is activated for only a portion of the total allocated activation time.
  • the portion of the activation time used to illuminate the display can be modulated, for example, by a set of minors that can be positioned to either pass light to the microdisplay or reflect the light away from the microdisplay.
  • an anay of moveable microdisplays e.g., a moveable minor
  • each microminor can represent a pixel and the intensity of the pixel can be determined by the positioning of the microdisplay.
  • the microminor can be in an on or an off state and the proportion of the time spent in the on state during the activation time of a particular color of LED determines the intensity of the image.
  • one or more of the LEDs e.g., each LED
  • FIG. 1 1 shows an optical display system 1600 that includes LED 11 10, microdisplay 1 130, a cooling system 1510, and a sensor 1520 that is in thermal communication with LED 1110 and electrical communication with cooling system 1510 so that, during use of system 1600, sensor 1520 and cooling system 1510 can be used to regulate the temperature of LED 1110.
  • This can be desirable, for example, when LED 1110 is a relatively large are LED (see discussion below) because such an LED can generate a significant amount of heat.
  • the amount of power input to LED 1110 can be increased with (primarily, increased operational efficiency at higher drive cunents) reduced risk of damaging LED 1110 via the use of sensor 1520 and cooling system 1510 to cool LED 11 10.
  • cooling systems include thermal electric coolers, fans, heat pipes, and liquid cooling systems.
  • Sensor 1520 can be, for example, manually controlled or computer controlled. In some embodiments, the system may not include a sensor (e.g., cooling system 1510 can be permanently on, or can be manually controlled).
  • the use of a cooling system can provide multiple advantages such as reducing the likelihood of damage to the LED resulting from an excess temperature and increasing the efficiency of the LED at higher drive cunents.
  • the cooling system may also reduce the shift in wavelength induced by temperature.
  • using a non-lambertian LED results in non-uniform angular distribution of light. In such embodiments, the microdisplay can be translated away from the image plane to reduce the appearance of the angular non-uniformity.
  • FIG. 12 shows a side view of an LED 100 in the form of a packaged die.
  • LED 100 includes a multi-layer stack 122 disposed on a submount 120.
  • Multi-layer stack 122 includes a 320 nm thick silicon doped (n-doped) GaN layer 134 having a pattern of openings 150 in its upper surface 110.
  • Multi-layer stack 122 also includes a bonding layer 124, a 100 nm thick silver layer 126, a 40 nm thick magnesium doped (p-doped) GaN layer 128, a 120 nm thick light-generating region 130 formed of multiple InGaN/GaN quantum wells, and a AlGaN layer 132.
  • An n-side contact pad 136 is disposed on layer 134, and a p-side contact pad 138 is disposed on layer 126.
  • An encapsulant material (epoxy having an index of refraction of 1.5) 144 is present between layer 134 and a cover slip 140 and supports 142. Layer 144 does not extend into openings 150.
  • Light is generated by LED 100 as follows.
  • P-side contact pad 138 is held at a positive potential relative to n-side contact pad 136, which causes electrical cunent to be injected into LED 100.
  • electrical cunent passes through light-generating region 130, electrons from n-doped layer 134 combine in region 130 with holes from p-doped layer 128, which causes region 130 to generate light.
  • Light-generating region 130 contains a multitude of point dipole radiation sources that emit light (e.g., isotropically) within the region 130 with a spectrum of wavelengths characteristic of the material from which light-generating region 130 is formed.
  • the spectrum of wavelengths of light generated by region 130 can have a peak wavelength of about 445 nanometers (nm) and a full width at half maximum (FWHM) of about 30 nm.
  • the charge earners in p-doped layer 126 have relatively low mobility compared to the charge caniers in the n-doped semiconductor layer 134.
  • placing silver layer 126 (which is conductive) along the surface of p- doped layer 128 can enhance the uniformity of charge injection from contact pad 138 into p-doped layer 128 and light-generating region 130. This can also reduce the electrical resistance of device 100 and/or increase the injection efficiency of device 100.
  • silver layer 126 has relatively high thermal conductivity, allowing layer 126 to act as a heat sink for LED 100 (to transfer heat vertically from the multi-layer stack 122 to submount 120). At least some of the light that is generated by region 130 is directed toward silver layer 126.
  • This light can be reflected by layer 126 and emerge from LED 100 via surface 110, or can be reflected by layer 126 and then absorbed within the semiconductor material in LED 100 to produce an electron-hole pair that can combine in region 130, causing region 130 to generate light.
  • at least some of the light that is generated by region 130 is directed toward pad 136.
  • the underside of pad 136 is formed of a material (e.g., a Ti/Al Ni/Au alloy) that can reflect at least some of the light generated by light-generating region 130.
  • the light that is directed to pad 136 can be reflected by pad 136 and subsequently emerge from LED 100 via surface 110 (e.g., by being reflected from silver layer 126), or the light that is directed to pad 136 can be reflected by pad 136 and then absorbed within the semiconductor material in LED 100 to produce an electron-hole pair that can combine in region 130, causing region 130 to generate light (e.g., with or without being reflected by silver layer 126).
  • surface 110 of LED 100 is not flat but consists of a modified triangular pattern of openings 150. In general, various values can be selected for the depth of openings 150, the diameter of openings 150 and the spacing between nearest neighbors in openings 150 can vary.
  • openings 150 have a depth 146 equal to about 280 nm, a non-zero diameter of about 160 nm, a spacing between nearest neighbors or about 220 nm, and an index of refraction equal to 1.0.
  • the triangular pattern is detuned so that the nearest neighbors in pattern 150 have a center-to-center distance with a value between (a - ⁇ a) and (a + ⁇ a), where "a" is the lattice constant for an ideal triangular pattern and " ⁇ a" is a detuning parameter with dimensions of length and where the detuning can occur in random directions.
  • detuning parameter, ⁇ a is generally at least about one percent (e.g., at least about two percent, at least about three percent, at least about four percent, at least about five percent) of ideal lattice constant, a, and/or at most about 25% (e.g., at most about 20%, at most about 15%, at most about 10%) of ideal lattice constant, a.
  • the nearest neighbor spacings vary substantially randomly between (a - ⁇ a) and (a + ⁇ a), such that pattern 150 is substantially randomly detuned.
  • a non-zero detuning parameter enhances the extraction efficiency of an LED 100.
  • P P ⁇ + P ⁇ + ... + P m captures the frequency-dependent response of the quantum well light-generating region 130, the p-contact layer 126 and other layers within LED 100.
  • the individual P m terms are empirically derived values of different contributions to the overall polarizability of a material (e.g., the polarization response for bound electron oscillations, the polarization response for free electron oscillations).
  • each of the additional metal layers will have a conesponding frequency dependent dielectric constant.
  • silver layer 126 (and any other metal layer in LED 100) has a frequency dependent term for both bound electrons and free electrons, whereas light-generating region 130 has a frequency dependent term for bound electrons but does not have a frequency dependent term for free electrons.
  • other terms can be included when modeling the frequency dependence of the dielectric constant. Such terms may include, for example, electron-phonon interactions, atomic polarizations, ionic polarizations and/or molecular polarizations.
  • the emission of light from the quantum well region of light-generating region 130 is modeled by inco ⁇ orating a number of randomly-placed, constant-cunent dipole sources within the light-generating region 130, each emitting short Gaussian pulses of spectral width equal to that of the actual quantum well, each with random initial phase and start-time.
  • a large supercell in the lateral direction is used, along with periodic boundary conditions. This can assist in simulating relatively large (e.g., greater than 0.01 mm on edge) device sizes.
  • the full evolution equations are solved in time, long after all dipole sources have emitted their energy, until no energy remains in the system.
  • the total energy emitted, the energy flux extracted through top surface 110, and the energy absorbed by the quantum wells and the n-doped layer is monitored. Through Fourier transforms both in time and space, frequency and angle resolved data of the extracted flux are obtained, and therefore an angle- and frequency-resolved extraction efficiency can be calculated.
  • an angle- and frequency-resolved extraction efficiency can be calculated.
  • the detuned pattern 150 can enhance the efficiency with which light generated in region 130 emerges from LED 100 via surface 110 because openings 150 create a dielectric function that varies spatially in layer 134 according to pattern 150. It is believed that this alters the density of radiation modes (i.e., light modes that emerge from surface 110) and guided modes (i.e., light modes that are confined within multi-layer stack 122) within LED 100, and that this alteration to the density of radiation modes and guided modes within LED 100 results in some light that would otherwise be emitted into guided modes in the absence of pattern 150 being scattered (e.g.., Bragg scattered) into modes that can leak into radiation modes.
  • scattered e.g., Bragg scattered
  • pattern 150 can eliminate all of the guided modes within LED 100. It is believed that the effect of detuning of the lattice can be understood by considering Bragg scattering off of a crystal having point scattering sites. For a perfect lattice ananged in lattice planes separated by a distance d, monochromatic light of wavelength ⁇ is scattered through an angle ⁇ according to the Bragg condition, n ⁇ - 2dsin#, where n is an integer that gives the order of the scattering.
  • the Bragg condition can be relaxed by detuning the spacing of between lattice sites by a detuning parameter ⁇ a. It is believed that detuning the lattice increases the scattering effectiveness and angular acceptance of the pattern over the spectral bandwidth and spatial emission profile of the source. While a modified triangular pattern 150 having a non-zero detuning parameter ⁇ a has been described that can enhance light extraction from LED 100, other patterns can also be used to enhance light extraction from LED 100.
  • FIG. 15 depicts the Fourier transform for an ideal triangular lattice. Extraction of light into a particular direction with in-plane wavevector k is related to the source emission Shinto all those modes with in-plane wavevector k! (i.e.
  • the maximum G to be considered is fixed by the frequency ( ⁇ ) emitted by the light-generating region and the dielectric constant of the light-generating region. As shown in FIG. 15, this defines a ring in reciprocal space which is often called the light line.
  • the light line will be an annulus due to the finite bandwidth of the light-generating region but for sake of clarity we illustrate the light line of a monochromatic source.
  • light propagating within the encapsulant is bounded by a light line (the inner circle in FIG. 15).
  • FIG. 16 shows the effect of increasing lattice constant for an ideal triangular pattern. The data shown in FIG. 16 are calculated using the parameters given for LED 100 shown in FIG.
  • the emitted light has a peak wavelength of 450 nm
  • the depth of the holes, the diameter of the holes, and the thickness of the n-doped layer 134 scale with the nearest neighbor distance, a, as 1.27a, 0.72a, and 1.27a + 40 nm, respectively.
  • Increasing the lattice constant increases the density of G points within the light-line of the encapsulant.
  • a clear trend in extraction efficiency with NND is observed. It is believed that the maximum extraction efficiency occurs for NND approximately equal to the wavelength of light in vacuum. The reason a maximum is achieved, is that as the NND becomes much larger than the wavelength of light, the scattering effect is reduced because the material becomes more uniform.
  • the filling factor for a triangular pattern is given by (2 ⁇ /V3)*(r/a) 2 , where r is the radius of a hole.
  • the data shown in FIG. 17 are calculated using the parameters given for the LED 100 shown in FIG. 12, except that the diameter of the openings is changed according the filling factor value given on the x-axis of the graph.
  • the extraction efficiency increases with filling factor as the scattering strengths ( ⁇ j) increase. A maximum is observed for this particular system at a filling factor of -48%.
  • LED 100 has a filling factor of at least about 10% (e.g., at least about 15%, at least about 20%) and/or at most about 90% (e.g., at most about 80%, at most about 70%, at most about 60%).
  • a modified triangular pattern has been described in which a detuning parameter relates to positioning of openings in the pattern from the positions in an ideal triangular lattice
  • a modified (detuned) triangular pattern may also be achieved by modifying the holes in an ideal triangular pattern while keeping the centers at the positions for an ideal triangular pattern.
  • FIG. 18 shows an embodiment of such a pattern.
  • a modified (detuned) pattern can have openings that are displaced from the ideal locations and openings at the ideal locations but with varying diameters.
  • enhanced light extraction from a light-emitting device can be achieved by using different types of patterns, including, for example, complex periodic patterns and nonperiodic patterns.
  • a complex periodic pattern is a pattern that has more than one feature in each unit cell that repeats in a periodic fashion.
  • a complex periodic pattern examples include honeycomb patterns, honeycomb base patterns, (2x2) base patterns, ring patterns, and Archimidean patterns.
  • a complex periodic pattern can have certain openings with one diameter and other openings with a smaller diameter.
  • a nonperiodic pattern is a pattern that has no translational symmetry over a unit cell that has a length that is at least 50 times the peak wavelength of light generated by region 130. Examples of nonperiodic patterns include aperiodic patterns, quasicrystalline patterns, Robinson patterns, and Amman patterns.
  • FIG. 19 shows numerical calculations for LED 100 for two different complex periodic patterns in which certain openings in the patterns have a particular diameter, and other openings in the patterns have smaller diameters.
  • the numerical calculations represented in FIG 19 show the behavior of the extraction efficiency (larger holes with a diameter of 80 nm) as the diameter of the smaller holes (dR) is varied from zero nm to 95 nm.
  • the data shown in FIG. 17 are calculated using the parameters given for the LED 100 shown in FIG. 12 except that the diameter of the openings is changed according the filling factor value given on the x-axis of the graph.
  • multiple hole sizes allow scattering from multiple periodicities within the pattern, therefore increasing the angular acceptance and spectral effectiveness of the pattern.
  • FIG. 20 shows numerical calculations for LED 100 having different ring patterns (complex periodic patterns). The number of holes in the first ring sunounding the central hole is different (six, eight or 10) for the different ring patterns.
  • the data shown in FIG. 20 are calculated using the parameters given for the LED 100 shown in FIG. 12, except that the emitted light has a peak wavelength of 450 nm.
  • the numerical calculations represented in FIG. 20 show the extraction efficiency of LED 100 as the number of ring patterns per unit cell that is repeated across a unit cell is varied from two to four.
  • FIG. 21 shows numerical calculations for LED 100 having an Archimidean pattern.
  • the Archimidean tiling A19 consists of 19 equally- spaced holes with a NND of a.
  • the holes are ananged in the form of an inner hexagon of seven holes, and outer hexagon of 12 holes, and a central hole within the inner hexagon.
  • the enhancement in light extraction, the methodology for conducting the conesponding numerical calculation, and the physical explanation of the enhanced light extraction for a light-emitting device having the pattern shown in FIG. 21 is generally the same as described above. As shown in FIG. 21 the extraction efficiency for A7 and A19 is about 77%.
  • the data shown in FIG. 21 the extraction efficiency for A7 and A19 is about 77%.
  • FIG. 21 shows numerical calculation data for LED 100 having a quasicrystalline pattern. Quasicrystalline patterns are described, for example, in M. Senechal, Quasicrystals and Geometry (Cambridge University Press, Cambridge, England 1996), which is hereby inco ⁇ orated by reference. The numerical calculations show the behavior of the extraction efficiency as the class of 8-fold based quasi-periodic stracture is varied. It is believed that quasicrystalline patterns exhibit high extraction efficiency due to high degree of in-plane rotational symmetries allowed by such structures.
  • the enhancement in light extraction, the methodology for conducting the conesponding numerical calculation, and the physical explanation of the enhanced light extraction for a light-emitting device having the pattern shown in FIG. 22 is generally the same as described above.
  • Results from FDTD calculations shown in FIG. 22 indicate that the extraction efficiency of quasicrystalline structures reaches about 82%.
  • the data shown in FIG. 22 are calculated using the parameters given for the LED 100 shown in FIG. 12, except that the emitted light has a peak wavelength of 450 and except that the NND is defined as the distance between openings within an individual cell. While certain examples of patterns have been described herein, it is believed that other patterns can also enhance the light extraction from LED 100 if the patterns satisfy the basic principles discussed above.
  • adding detuning to quasicrystalline or complex periodic structures can increase extraction efficiency.
  • at least about 45% e.g., at least about 50%, at least about 55%, at least about 60%, at least about 70%, at least about 80%, at least about 90%, at least about 95%) of the total amount of light generated by light-generating region 130 that emerges from LED 100 emerges via surface 110.
  • the cross-sectional area of LED 100 can be relatively large, while still exhibiting efficient light extraction from LED 100.
  • one or more edges of LED 100 can be at least about one millimeter (e.g., at least about 1.5 millimeters, at least about two millimeters, at least about 2.5 millimeters, at least about three millimeters), and at least about 45% (e.g., at least about 50%, at least about 55%, at least about 60%, at least about 70%, at least about 80%, at least about 90%, at least about 95%) of the total amount of light generated by light-generating region 130 that emerges from LED 100 emerges via surface 110.
  • This can allow for an LED to have a relatively large cross-section (e.g., at least about one millimeter by at least about one millimeter) while exhibiting good power conversion efficiency.
  • the extraction efficiency of an LED having the design of LED 100 is substantially independent of the length of the edge of the LED.
  • the difference between the extraction efficiency of an LED having the design of LED 100 and one or more edges having a length of about 0.25 millimeter and the extraction efficiency of LED having the design of LED 100 and one or more edges having a length of one millimeter can vary by less than about 10% (e.g., less than about 8%, less than about 5%, less than about 3%).
  • the extraction efficiency of an LED is the ratio of the light emitted by the LED to the amount of light generated by the device (which can be measured in terms of energy or photons).
  • the quantum efficiency of an LED having the design of LED 100 is substantially independent of the length of the edge of the LED.
  • the difference between the quantum efficiency of an LED having the design of LED 100 and one or more edges having a length of about 0.25 millimeter and the quantum efficiency of LED having the design of LED 100 and one or more edges having a length of one millimeter can vary by less than about 10% (e.g., less than about 8%, less than about 5%, less than about 3%).
  • the quantum efficiency of an LED is the ratio of the number of photons generated by the LED to the number of electron-hole recombinations that occur in the LED. This can allow for an LED to have a relatively large cross-section (e.g., at least about one millimeter by at least about one millimeter) while exhibiting good performance.
  • the wall plug efficiency of an LED having the design of LED 100 is substantially independent of the length of the edge of the LED.
  • the difference between the wall plug efficiency of an LED having the design of LED 100 and one or more edges having a length of about 0.25 millimeter and the wall plug efficiency of LED having the design of LED 100 and one or more edges having a length of one millimeter can vary by less than about 10% (e.g., less than about 8%, less than about 5%, less than about 3%).
  • the wall plug efficiency of an LED is the product of the injection efficiency of the LED (the ratio of the numbers of carriers injected into the device to the number of carriers that recombine in the light-generating region of the device), the radiative efficiency of the LED (the ratio of electron-hole recombinations that result in a radiative event to the total number of electron-hole recombinations), and the extraction efficiency of the LED (the ratio of photons that are extracted from the LED to the total number of photons created).
  • This can allow for an LED to have a relatively large cross-section (e.g., at least about one millimeter by at least about one millimeter) while exhibiting good performance.
  • FIG. 23 shows the Fourier transform construction for two ideal triangular lattices of different lattice constant.
  • FIG. 24 which shows extraction efficiency into a solid angle (given by the collection half-angle in the diagram).
  • the data shown in FIG. 24 are calculated using the parameters given for the LED 100 shown in FIG. 12, except that the emitted light has a peak wavelength of 530 nm and a bandwidth of 34 nm, the index of refraction of the encapsulant was 1.0, the thickness of the p-doped layer was 160 nm, the light generating layer was 30 nm thick, the NND (a) for the three curves is shown on FIG 24, and the depth, hole diameter, and n-doped layer thickness scaled with a, as 1.27a, 0.72a, and 1.27a + 40 nm, respectively.
  • the approach is especially applicable for reducing the source etendue which is believed to often be proportional to n 2 , where n is the index of refraction of the sunounding material (e.g., the encapsulant). It is therefore believed that reducing the index of refraction of the encapsulating layer for LED 100 can lead to more collimated emission, a lower source etendue, and therefore to a higher surface brightness (here defined as the total lumens extracted into the etendue of the source).
  • using an encapsulant of air will reduce the source etendue while increasing extraction efficiency into a given collection angle centered around the normal direction.
  • the distribution of light is more collimated than a lambertian distribution.
  • at least about 40% e.g., at least about 50%, at least about 70%, at least about 90%
  • the light emerging via the surface of the dielectric layer emerges within at most about 30° (e.g., at most about 25°, at most about 20°, at most about 15°) of an angle normal to surface 110.
  • a wafer has at least about five LEDs (e.g., at least about 25 LEDs, at least about 50 LEDs) per square centimeter.
  • an LED 300 having a layer containing a phosphor material 180 can be disposed on surface 110.
  • the phosphor material can interact with light at the wavelength(s) generated by region 130 to provide light at desired wavelength(s). In some embodiments, it may be desirable for the light that emerges from packaged LED 100 to be substantially white light.
  • the phosphor material in layer 180 can be formed of, for example, a (Y,Gd)(Al,Ga)G:Ce or "YAG" (yttrium, aluminum, garnet) phosphor. When pumped by blue light emitted from the light-generating region 130, the phosphor material in layer 180 can be activated and emit light (e.g., isotropically) with a broad spectram centered around yellow wavelengths.
  • layer 180 can be substantially uniformly disposed on surface 110.
  • the distance between the top 151 of pattern 150 and the top 181 of layer 180 can vary by less than about 20% (e.g., less than about 10%, less than about 5%, less than about 2%) across surface 1 10.
  • the thickness of layer 180 is small compared to the cross-sectional dimensions of surface 130 of LED 100, which are typically about one millimeter (mm) by one mm.
  • the phosphor material in layer 180 can be substantially uniformly pumped by light emerging via surface 110.
  • the phosphor layer 180 is relatively thin compared to the dimensions of the surface 110 of the LED 100, such that light emitted by the light- generating region 130 is converted into lower wavelength light within the phosphor layer 180 approximately uniformly over the entire surface 110 of LED 100.
  • the relatively thin, uniform phosphor layer 180 produces a uniform spectram of white light emitted from the LED 100 as a function of position on surface 110.
  • LED 100 can be fabricated as desired. Typically, fabrication of LED 100 involves various deposition, laser processing, lithography, and etching steps. For example, FIG.
  • FIG. 26 shows a LED wafer 500 containing an LED layer stack of material deposited on a substrate (e.g., sapphire, compound semiconductor, zinc oxide, silicon carbide, silicon) 502.
  • a substrate e.g., sapphire, compound semiconductor, zinc oxide, silicon carbide, silicon
  • Such wafers are commercially available. Exemplary commercial suppliers include Epistar Co ⁇ oration, Arima Optoelectronics Co ⁇ oration and South Epitaxy Co ⁇ oration.
  • a buffer layer 504 e.g., a nitride-containing layer, such as a GaN layer, an A1N layer, an AlGaN layer
  • an n-doped semiconductor layer e.g., an n-doped Si:GaN
  • a cunent spreading layer 508 e.g., an AlGaN/GaN heterojunction or superlattice
  • a light-emitting region 510 e.g., an InGaN/GaN multi-quantum well region
  • a semiconductor layer 512 e.g., a p-doped Mg:GaN layer
  • Wafer 500 generally has a diameter of at least about two inches (e.g., from about two inches to about 12 inches, from about two inches to about six inches, from about two inches to about four inches, from about two inches to about three inches).
  • FIG. 27 shows a multi-layer stack 550 including layers 502, 504, 506, 508, 510 and 512, as well as layers 520, 522, 524 and 526, which are generally formed of materials capable of being pressure and/or heat bonded as described below.
  • layer 520 can be a nickel layer (e.g., electron-beam evaporated)
  • layer 522 can be a silver layer (e.g., electron-beam evaporated)
  • layer 524 can be a nickel layer (e.g., electron-beam evaporated)
  • layer 526 can be a gold layer (e.g., electron- beam evaporated).
  • layer 520 can be a relatively thin layer
  • layer 524 can be a relatively thick layer.
  • Layer 524 can act, for example, as diffusion banier to reduce the diffusion of contaminants (e.g., gold) into layers 520, 522 and/or 524 itself.
  • multi-layer stack 550 can be treated to achieve an ohmic contact.
  • stack 550 can be annealed (e.g., at a temperature of from about 400°C to about 600°C) for a period of time (e.g., from about 30 seconds to about 300 seconds) in an appropriate gas environment (e.g., nitrogen, oxygen, air, forming gas).
  • FIG. 28 shows a multi-layer stack 600 that includes a submount (e.g., germanium (such as polycrystalline germanium), silicon (such as polycrystalline silicon), silicon-carbide, copper, copper-tungsten, diamond, nickel-cobalt) 602 having layers 604, 606, 608 and 610 deposited thereon.
  • a submount e.g., germanium (such as polycrystalline germanium), silicon (such as polycrystalline silicon), silicon-carbide, copper, copper-tungsten, diamond, nickel-cobalt
  • Submount 602 can be formed, for example, by sputtering or electroforming.
  • Layer 604 is a contact layer and can be formed, for example, from aluminum (e.g., electron evaporated).
  • Layer 606 is a diffusion barrier and can be formed, for example, from Ni (e.g. electron evaporated).
  • Layer 608 can be a gold layer (e.g., electron-beam evaporated), and layer 610 can be a AuSn bonding layer (e.g., thermal evaporated, sputtered) onto layer 608.
  • multi-layer stack 600 can be treated to achieve an ohmic contact.
  • stack 600 can be annealed (e.g., at a temperature of from about 350°C to about 500°C) for a period of time (e.g., from about 30 seconds to about 300 seconds) in an appropriate gas environment (e.g., nitrogen, oxygen, air, forming gas).
  • FIG. 29 shows a multi-layer stack 650 formed by bonding together layers 526 and 610 (e.g., using a solder bond, using a eutectic bond, using a peritectic bond). Layers 526 and 610 can be bonded, for example, using thermal-mechanical pressing.
  • multi-layer stack 650 can be put in a press and pressurized (e.g., using a pressure of up to about 5 MPa, up to about 2 MPa) heated (e.g., to a temperature of from about 200°C to about 400°C).
  • Stack 650 can then be cooled (e.g., to room temperature) and removed from the press.
  • Substrate 502 and buffer layer 504 are then at least partially removed from stack 650. In general, this can be achieved using any desired methods. For example, as shown in FIG.
  • substrate 502 is removed by exposing stack 650 (e.g., through surface 501 of substrate 502) to electromagnetic radiation at an appropriate wavelength to partially decompose layer 504. It is believed that this results in local heating of layer 504, resulting in the partial decomposition of the material of layer 504 adjacent the interface of layer 504 and substrate 502, thereby allowing for the removal of substrate 502 from stack 650 (see discussion below). For example, in embodiments in which layer 504 is formed of gallium nitride, it is believed that constituents including gallium and gaseous nitrogen are formed.
  • stack 650 can be heated during exposure of surface 501 to the electromagnetic radiation (e.g., to reduce strain within stack 650).
  • Stack 650 can be heated, for example, by placing stack 650 on a hot plate and/or by exposing stack 650 to an additional laser source (e.g. a CO 2 laser). Heating stack 650 during exposure of surface 501 to electromagnetic radiation can, for example, reduce (e.g., prevent) liquid gallium from re-solidifying. This can reduce the build up of strain within stack 650 which can occur upon the re-solidification of the gallium. In certain embodiments, after exposure to the electromagnetic radiation, residual gallium is present and keeps substrate 502 bonded in stack 650. In such embodiments, stack 650 can be heated to above the melting temperature of gallium to allow substrate 502 to be removed from the stack.
  • an additional laser source e.g. a CO 2 laser
  • stack 650 may be exposed to an etchant (e.g., a chemical etchant, such as HCI) to etch the residual gallium and remove substrate 502.
  • an etchant e.g., a chemical etchant, such as HCI
  • Other methods of removing the residual gallium e.g., physical methods
  • surface 501 is exposed to laser radiation including the abso ⁇ tion wavelength of layer 504 (e.g., about 248 nanometers, about 355 nanometers).
  • Laser radiation processes are disclosed, for example, in U.S. Patent Nos. 6,420,242 and 6,071,795, which are hereby inco ⁇ orated by reference.
  • the multi-layer stack is then heated to above the melting point of gallium, at which point substrate 502 and buffer layer 504 are removed from the stack by applying a lateral force to substrate 502 (e.g., using a cotton swab).
  • a lateral force to substrate 502 (e.g., using a cotton swab).
  • multiple portions of surface 501 are simultaneously exposed to the electromagnetic radiation.
  • multiple portions of surface 501 are sequentially exposed to electromagnetic radiation. Combinations of simultaneous and sequential exposure can be used.
  • the electromagnetic radiation can be exposed on surface 501 in the form of a pattern (e.g., a se ⁇ entine pattern, a circular pattern, a spiral pattern, a grid, a grating, a triangular pattern, an elementary pattern, a random pattern, a complex pattern, a periodic pattern, a nonperiodic pattern).
  • the electromagnetic radiation can be rastered across one or more portions of surface 501.
  • surface 501 is exposed to overlapping fields of electromagnetic radiation.
  • the electromagnetic radiation passes through a mask before reaching surface 501.
  • the electromagnetic radiation can pass through an optical system that includes a mask (e.g., a high thermal conductivity mask, such as a molybdenum mask, a copper-beryllium mask) before reaching surface 501.
  • a mask e.g., a high thermal conductivity mask, such as a molybdenum mask, a copper-beryllium mask
  • the mask is an aperture (e.g., for truncating or shaping the beam).
  • the optical system can include, for example, at least two lenses having the mask disposed therebetween.
  • the mask can be formed as a pattern of material on surface 501, with the mask leaving certain portions of surface 501 exposed and some portions of surface 501 unexposed. Such a mask can be formed, for example, via a lithography process.
  • the electromagnetic radiation can be rastered across one or more portions of the mask.
  • reducing at least one dimension of the region on surface 501 exposed to electromagnetic radiation within a given area of surface 501 can limit undesired crack propagation, such as crack propagation into layer 504, layer 506 or other layers of stack 650 during removal of substrate 502, while still allowing for crack propagation at the interface between substrate 502 and buffer layer 504. It is believed that, if the size of the feature of the electromagnetic radiation on surface 501 is too large, then a gaseous bubble (e.g., a nitrogen bubble) may form that can create a localized pressure that can cause undesired cracking.
  • a gaseous bubble e.g., a nitrogen bubble
  • At least one dimension of the spot or line can be a maximum of at most about one millimeter (e.g., at most about 500 microns, at most about 100 microns, at most about 25 microns, at most about 10 microns).
  • the spot size is from about five microns to about one millimeter (e.g., from about five microns to about 100 microns, from about five microns to about 25 microns, from about five microns to about 10 microns).
  • stack 650 is vibrated while surface 501 is exposed to the electromagnetic radiation.
  • vibrating stack 650 while exposing stack 650 to the electromagnetic radiation can enhance crack propagation along the interface between layer 504 and substrate 502.
  • the conditions are selected to limit the propagation of cracks into layer 504 (e.g., so that substantially no cracks propagate into layer 504, 506, and the rest of stack 650).
  • a portion of buffer layer 504 typically remains on at least a portion of the surface of layer 506.
  • a residue of material from substrate 502 e.g., containing aluminum and/or oxygen
  • buffer layer 504 It is generally desirable to remove the remaining portions of buffer layer 504 and any residue from substrate 502, to expose the surface of layer 506, and to clean the exposed surface of layer 506 because layer 506 (which is typically formed of an n-doped semiconductor material) can exhibit good electrical properties (e.g., desirable contact resistance) for subsequent formation of an electrical contact.
  • One or more process steps are usually used to remove any residue and/or remaining portion of buffer layer 504 present, and to clean the surface of layer 506 (e.g., to remove impurities, such as organics and/or particles).
  • the process(es) can be performed using a variety of techniques and/or combinations of techniques.
  • buffer layer 504 is not completely removed. Instead, in such embodiments, these processes can be used to remove only on portions of buffer layer 504 that conespond to locations where electrical leads will subsequently be disposed (e.g., by using a self- aligned process).
  • the amount of strain in stack 650 (e.g., due to the lattice mismatch and/or thermal mismatch between the layers in stack 650) can change. For example, if the amount of strain in stack 650 is decreased, the peak output wavelength of region 510 can change (e.g., increase). As another example, if the amount of strain in stack 650 is increased, the peak output wavelength of region 510 can change (e.g., decrease).
  • substrate 502 and submount 602 are selected so that the coefficient of thermal expansion of submount 602 differs from a coefficient of thermal expansion of substrate 502 by less than about 15% (e.g., less than about 10%, less than about 5%).
  • substrate 502 and submount 602 are selected so that the thickness of submount 602 is substantially greater than the thickness of substrate 502.
  • semiconductor layers 504, 506, 508, 510, 512 and submount 602 are selected so that the coefficient of thermal expansion of submount 602 differs from a coefficient of thermal expansion of one or more of layers 504, 506, 608, 510, and 512 by less than about 15% (e.g., less than about 10%, less than about 5%>).
  • substrate 502 and submount 602 can have any desired thickness.
  • substrate 502 is at most about five millimeters (e.g., at most about three millimeters, at most about one millimeter, about 0.5 millimeter) thick.
  • submount 602 is at most about 10 millimeters (e.g., at most about five millimeters, at most about one millimeter, about 0.5 millimeter) thick. In some embodiments, submount 602 is thicker than substrate 502, and, in certain embodiments, substrate 502 is thicker than submount 602. After removal of buffer layer 504 and exposing/cleaning the surface of layer 506, the thickness of layer 506 can be reduced to a desired final thickness for use in the light-emitting device. This can be achieved, for example, using a mechanical etching process, alone or in combination with an etching process.
  • the surface of layer 506 has a relatively high degree of flatness (e.g., a relatively high degree of flatness on the scale of the lithography reticle to be used).
  • the surface of layer 506 has a flatness of at most about 10 microns per 6.25 square centimeters (e.g., at most about five microns per 6.25 square centimeters, at most about one micron per 6.25 square centimeters).
  • the surface of layer 506 has a flatness of at most about 10 microns per square centimeter (e.g., at most about five microns per square centimeter, at most about one microns per square centimeter). In certain embodiments, after etching/cleaning the exposed surface of layer 506, the surface of layer 506 has an RMS roughness of at most about 50 nanometers (e.g., at most about 25 nanometers, at most about 10 nanometers, at most about five nanometers, at most about one nanometer).
  • the exposed surface of layer 506 may be too rough and/or insufficiently flat to use nanolithography to form the pattern with sufficient accuracy and/or reproducibility.
  • the nanolithography process may include depositing a planarization layer on the surface of layer 506 and a lithography layer on the surface of the planarization layer. For example, FIG.
  • planarization layer 702 is disposed on the surface of layer 506, and a lithography layer 704 is disposed on the surface of layer 702, an exposed surface 505 of layer 506 may be relatively rough (e.g., RMS roughness of about 10 nanometers or more) after cleaning/etching layer 506.
  • planarization layer 702 is formed of multiple layers (e.g., of the same material) that are sequentially deposited.
  • planarization layer 702 examples include polymers (e.g., DUV-30J from Brewer Sciences, anti-reflection coatings, high viscosity formable polymers), and examples of materials from which lithography layer 704 can be selected include UV-curable polymers (e.g., low viscosity MonoMatTM available from Molecular Imprints, Inc.).
  • Layers 702 and 704 can be formed using any desired technique, such as, for example, spin coating, vapor deposition, and the like.
  • Layer 702 can be, for example, at least about 100 nanometers thick (e.g., at least about 500 nanometers thick) and/or at most about five microns thick (e.g., at most about one micron thick).
  • Layer 704 can be, for example, at least about one nanometer thick (e.g., at least about 10 nanometers thick) and/or at most about one micron thick (e.g., at most about 0.5 micron thick).
  • a mold that defines a portion of the desired pattern is then pressed into lithography layer and (typically with heating or UV-curing of the mold and/or layer 704), and stepped across the surface of layer 704 in a portion-by-portion manner to form indentions in layer 704 (FIG. 32) that conespond to the desired pattern in the surface of layer 506.
  • a single step covers the entire wafer (e.g., full wafer nanolithography techniques).
  • Layer 704 is then etched (e.g., using reactive ion etching, wet etching) to expose portions of the surface of layer 702 conesponding to what were the indented portions of layer 704 (FIG. 33).
  • imprint/etch processes are disclosed, for example, in U.S. Patent No. 5,722,905, and Zhang et al., Applied Physics Letters, Vol. 83, No. 8, pp. 1632-34, both of which are hereby inco ⁇ orated by reference.
  • the pattern in layer 704 also leaves regions for depositing n-contacts later on in the process flow.
  • patterned layer 704 is used as a mask to transfer the pattern into the planarization layer 702 (e.g., dry etching, wet etching).
  • An example of a dry etching method is reactive ion etching.
  • layers 702 and 704 are subsequently used as a mask to transfer the pattern into the surface of layer 506 (e.g., using dry etching, wet etching).
  • the process can include, disposing a material 708 (e.g., a metal, such as aluminum, nickel, titanium, tungsten) in the etched portions of layers 702 and 704 (e.g., by evaporation) and on the surface of layer 704.
  • a material 708 e.g., a metal, such as aluminum, nickel, titanium, tungsten
  • layers 702 and 704 are then etched (e.g., using reactive ion etching, wet etching), leaving behind etch-resistant material 708 on the surface of layer 506, which can serve as a mask for etching the pattern into the surface of layer 506 (FIG. 39).
  • etch resistant material 708 can then be removed (e.g., using dry etching, wet etching).
  • the process can include, after forming the indents in layer 704, disposing (e.g., spin coating) an etch resistant material (e.g., a Si-doped polymer) 710 on the surface of layer 704 and in the indents in layer 704, and material 710 is then etched back (e.g., using dry etching) so that to expose the surface of layer 704 while maintaining the etch- resistant material in the indents in layer 704 (FIG. 41). As shown in FIG.
  • an etch resistant material e.g., a Si-doped polymer
  • portions of layers 702 and 704 are then etched (e.g., using reactive ion etching, dry etching, wet etching), leaving behind etch-resistant material 708 and the portions of layers 702 and 704 under material 708, which serve as a mask for etching the pattern into the surface of layer 506 (FIG. 43).
  • etch-resistant material 708 can then be removed (e.g., using reactive ion etching, dry etching, wet etching).
  • removing layer 708 can involve the use of a plasma process (e.g., a fluorine plasma process).
  • a layer of phosphor material can optionally be disposed (e.g., spin-coated) onto the patterned surface of n-doped layer 506.
  • the phosphor can conformally coat the patterned surface (coat with substantially no voids present along the bottoms and sidewalls of the openings in the patterned surface).
  • a layer of encapsulant material can be disposed on the surface of patterned n-doped layer 506 (e.g. by CVD, sputtering, suspension by liquid binder that is subsequently evaporated).
  • the encapsulant can contain one or more phosphor materials.
  • the phosphor can be compressed to achieve thickness uniformity less than about 20%, less than about 15%, less than about 10%, less than about 5%, or less than about 2% of the average thickness of the phosphor.
  • the phosphor-containing encapsulant can conformally coat the patterned surface. After the dielectric function pattern has been created in the n-doped layer 506, individual LED dice can be cut from the wafer. Once wafer processing and wafer testing is complete, individual LED dice are separated and prepared for packaging and testing. A sidewall passivation step and/or a pre-separation deep mesa etching step may be used to reduce potential damage to the electrical and/or optical properties of the patterned LED incuned during wafer cutting.
  • the individual LEDs can be any size up to the size of the wafer itself, but individual LEDs are typically square or rectangular, with sides having a length between about 0.5 mm to 5 mm.
  • standard photolithography is used to define the location of contact pads on the wafer for energizing the device, and ohmic contacts are evaporated (e.g. using electron beam evaporation) onto the desired locations.
  • a contact layout for an LED 1802 includes two conductive pads 1804a and 1804b and conductive bars (or fingers) 1806 extending from conductive pads 1804a and 1804b toward a central area of LED 1802.
  • Wire bonds (not shown) connected to conductive pads 1804a and 1804b provide cunent and voltage to LED 1802.
  • Conductive bars 1806 spread the cunent from the conductive pads 1804a and 1804b to a top surface 1808 of LED 1802. Bars 1806 allow the cunent to be spread sufficiently across top surface 1808 while limiting the amount of surface 1808 covered by the contacts.
  • FIG. 45B shows a top view of LED 1802 including conductive pads 1804a and 1804b and conductive bars 1806.
  • the width of conductive pads 1804a and 1804b can be larger than the width of conductive bars 1806.
  • the larger width of pads 1804a and 1804b can allow pads 1804a and 1804b to function as power busses and spread a relatively large amount of power down the bus to bars 1806.
  • the width of pads 1804a and 1804b and bars 1806 can be relative to the size of LED 1802 and/or can be based on other factors such as lithography and processing parameters. For example, an LED may range in size from about 0.5mm to about 1cm on a side. As described above, the aspect ratio of LED 1802 can also vary.
  • the width of conductive pads 1804a and 1804b can be, for example, about 50um to about 500um and the width of bars 1806 can be, for example, about lum to about 50um.
  • conductive pads 1804a and 1804b and bars 1806 can vary based on, for example, cunent and power to be supplied to the LED or based on deposition and processing parameters.
  • conductive pads 1804a and 1804b and bars 1806 can be about O.lum to about lOum in height.
  • bars 1806 can vary as desired in both length and shape.
  • bars 1806 can be rectangular and extend from conductive pads 1804a and 1804b toward a central region of LED 1802.
  • bars 1806 could have a different shape such as square, triangular, or trapezoidal.
  • FIGS. 46A to 46C show another example of a contact structure.
  • multiple bars 1812 extend across the entire length of LED 1810, connecting conductive pad 1804a to conductive pad 1804b.
  • Contact bars 1812 have an associated resistivity r m , thickness t b , and a length 1.
  • Cunent distribution properties for LED 1810 based on conductive pads 1804a and 1804b and contact bars 1812 can be estimated by simplifying the structure into an equivalent circuit model as shown in FIG. 46C. The aspect ratio of LED 1810 can influence the cunent dissipation of the system.
  • the contact resistance is divided by the surface coverage ratio/, as shown in the following equation
  • J J 0 (e' v - , KT - l)
  • J 0 the junction saturation cunent and the absolute temperature.
  • the above estimates neglect the contribution of the n-type material in lateral cunent spreading.
  • the cunent spreading is predominantly occurring in the metal contact because the conductivity of the contact is much greater than the conductivity of the n-type material.
  • the ratio of the contact conductivity to the n-type material conductivity can be in the range of from about 100 to about 500.
  • p m 2.2-10 "6 ⁇ cm (gold)
  • p p . c 1.0-10 "3 ⁇ cm 2
  • p p 5.0 ⁇ cm
  • p n-c 1.0-10 ⁇ 4 ⁇ cm 2
  • p n 5.0-10 "3 ⁇ cm
  • n-contact surface coverage 10% and thicknesses for p-, n-, and metal 0.3 ⁇ m, 3.0 ⁇ m and 2 ⁇ m (at a 10% coverage).
  • L s equals 1.4mm.
  • U 0.325
  • the contact resistivity can alternatively or additionally be altered to enhance the cunent spreading by including an insulating layer 1820 (e.g., an oxide layer, FIG. 47A) underneath a portion of the contact. As shown in FIGS. 47A and 47B, insulating layer 1820 (indicated by dashed lines) is included under a portion of bar 1812.
  • Insulating layer 1820 has a greater width at the top of the bar (e.g., close to pads 1804) and gets thinner towards the central area of the die.
  • An equivalent circuit diagram is shown in FIG. 47B.
  • Contact resistivity is generally proportional to the contact area. For example, the contact resistivity increases as the contact area decreases as shown in the following equation e ff where W ⁇ s the repetition rate of the bars (e.g., the number of bars per unit area). Due to underlying insulating layer 1820, the area of the contact is smaller at the edge of the contact closest to pads 1804a and 1804b and increases as the distance from pads 1804a and 1804b increases.
  • the cunent uniformity factor for the structure shown in FIG. 47B can be estimated according to the following equation
  • oxide layer 1820 can force cunent towards the ends of the contacts (e.g., toward the central area of the die) increasing the cunent spreading. Oxide layer 1820 can also reduce the light generation underneath the light absorbing contacts allowing greater percentage of the generated light to emerge from the surface of the LED.
  • FIGS. 48A and 48B show a further configuration of pads 1804a and 1804b, contact 1830, and oxide layer 1820 (indicated by dashed lines and disposed under a portion of contact 1830).
  • contacts 1830 are also tapered. While shown in FIG. 48A as being linearly tapered, other tapering could be used. The linear tapering maintains a similar total contact area to the contact area of contact 1812 shown in FIG.
  • the oxide can be tapered at higher angle so that the contact resistance is maximum at the pad and minimum at the die center. The contact resistance decreases towards the die center, and the bar resistance decreases closer to the pad. The tapering of both the contact and the insulating layer contribute to forcing the cunent towards the die center.
  • Similar integration formulas for the cunent distribution as described above can be used to estimate the cunent distribution for the structure shown in FIGS. 48 A and 48B.
  • FIG. 49 A shows a top view and FIGS. 49B and 49C show cross-sectional views of an additional contact structure 1801. Conductive contacts 1836 extend toward the center of the die, but do not continuously cover the upper surface of the LED between bars 1804a and 1804b.
  • FIG. 50 shows a graph 1850 of estimated normalized junction cunent density as a function of the normalized distance between bars 1804a and 1804b for various contact and die configurations based on the forgoing equations.
  • Line 1856 represents the cunent density for square die with rectangular bars and no oxide
  • line 1858 represents the cunent density for rectangular die with rectangular bars and no oxide
  • line 1860 represents the cunent density for a rectangular die with rectangular bars and tapered oxide
  • line 1862 represents the cunent density for rectangular die with tapered bars and tapered oxide.
  • Graph 1850 shows the improvement in the cunent density distribution for both a rectangular chip and an oxide layer under a portion of the contact.
  • FIG. 51 A shows a top view
  • FIG. 5 IB shows a cross-sectional view of an additional contact structure 1803. Insulating layers 1805a and 1805b are located between the top of the LED and metal pads 1804a and 1804b, respectively.
  • Insulating layers 1805a and 1805b are located under a portion of metal pads 1804a and 1804b, respectively, toward the edge of the die such that a portion of metal pads 1804a and 1804b are supported by insulating layers 1805a and 1805b, respectively, and a portion of metal pads 1804a and 1804b are supported by the top surface of the light emitting diode.
  • Oxide layers 1805a and 1805b reduce the light generation underneath the light absorbing metal pads 1804a and 1804ballowing greater percentage of the generated light to emerge from the surface of the LED. While embodiments described above include a single set of contacts extending from metal pads 1804a and 1804b, multiple sets of contacts could be used.
  • FIG. 53 shows a packaged LED device 1890.
  • the package should be capable of facilitating light collection while also providing mechanical and environmental protection of the die and allowing heat generated in the die to be dissipated.
  • LED 1890 includes conductive pads 1804a and 1804b that allow cunent to be spread to multiple contact fingers 1812 and dissipated to the LED surface.
  • Multiple wire bonds 1892 provide an electrical cunent path between the LED and the package.
  • Wire bonds 1892 can be made of various conductive materials such as gold, aluminum, silver, platinum, copper, and other metals or metal alloys.
  • the package also includes multiple castellations 1894 to transport cunent from a bottom surface of the package to a top surface of the package to facilitate surface mounting on a circuit board.
  • Castellations 1894 include a central region and a plating layer.
  • the central region can be composed of a refractory metal, for example, tungsten and can be relatively thick (e.g., about 100 um to about 1mm).
  • the central region can be plated with an electrically conductive material such as gold.
  • the plating can range in thickness from about 0.5um to about lOum and provides a cunent path that supports relatively high power levels.
  • the package includes a transparent cover 1896 packaged on the LED die to protect the patterned surface 506 (FIG. 36) when an encapsulant is not used.
  • the transparent cover 1896 is attached to the package, for example, using a glassy frit that is melted in a furnace. Alternatively, cover 1896 can be connected using a cap weld or an epoxy for example.
  • the transparent cover 1896 can be further coated with one or more anti-reflection coatings to increase light transmission. Without wishing to be bound by theory, it is believed that the absence of an encapsulant layer allows higher tolerable power loads per unit area in the patterned surface LED 100. Degradation of the encapsulant can be a common failure mechanism for standard LEDs and is avoided not using an encapsulant layer.
  • Packaged device 1890 can be mounted on a circuit board, on another device, or directly on a heat sink.
  • FIG. 54 shows a model of the heat dissipation for a packaged device 1890 placed on a heat sink device.
  • the packaged device 1890 is supported by a core board 1900 that includes insulating and electrically conductive regions (e.g., conductive regions using metals such as Al or Cu) attached to the heat sink.
  • packaged device 1890 can be attached to core board 1900 using solder (examples of solder include AuSn solder, PbSn solder, NiSn solder, InSn solder, InAgSn solder, and PbSnAg solder) or using an electrically conductive epoxy (e.g., silver filled epoxy).
  • Core board 1900 is supported by a layer of heat sink metal 1902 and heat sink fins 1904.
  • core board 1900 can be attached to heat sink metal 1902 using solder (examples of solder include AuSn solder, PbSn solder, NiSn solder, InSn solder, InAgSn solder, and PbSnAg solder) or using epoxy (e.g., silver filled epoxy).
  • solder examples include AuSn solder, PbSn solder, NiSn solder, InSn solder, InAgSn solder, and PbSnAg solder
  • epoxy e.g., silver filled epoxy
  • the thermal resistance of a slice with thickness d x can be estimated according to the following equation _ dx 1 _ dx 1 '" ⁇ ⁇ 0 ⁇ S ⁇ ⁇ K 0 ⁇ (S ' + 2x tan ⁇ ) 2 where Ko is the thermal conductivity and S' is the dimensions of the heat front at the top of the element. Integrating produces the following equation for resistivity R - > K 0 S'(S' + 2d tan ⁇ ) In the case of a rectangle, this resistivity can be calculated generating the results shown in FIG. 55.
  • FIG. 55 shows a calculated ratio of Rth_rectan g ie/Rth_square (where Rth is the thermal resistance) for a system of large thickness and spreading angle of 45°.
  • FIG. 56 shows a graph of junction temperature as a function of aspect ratio. It is believed that a lower junction temperature is desirable for reduced wavelength shift and higher device efficiency.
  • using a rectangular shape for an LED compared, for example, to a square
  • the advantages can include one or more of the following.
  • the rectangular LED can allow a greater number of wire bonds per unit area increasing the power that can be input into the LED.
  • the rectangular shape can be chosen to match a particular aspect ratio of a pixel or microdisplay, thus, eliminating the need for complex beam shaping optics.
  • the rectangular shape can also improve heat dissipation from the LED and reduce the likelihood of failure due to the device overheating. Because the cross section of an individual LEDs cut from a wafer is only slightly larger than the light-emitting surface area of the LED, many individual, and separately addressable LEDs can be packed closely together in an anay. If one LED does not function (e.g., due to a large defect), then it does not significant diminish the performance of the anay because the individual devices are closely packed.
  • the light-emitting device can have any desired thickness, and the individual layers within the light-emitting device can have any desired thickness.
  • the thicknesses of the layers within multi-layer stack 122 are chosen so as to increase the spatial overlap of the optical modes with light-generating region 130, to increase the output from light generated in region 130.
  • Exemplary thicknesses for certain layers in a light-emitting device include the following.
  • layer 134 can have a thickness of at least about 100 nm (e.g., at least about 200 nm, at least about 300 nm, at least about 400 nm, at least about 500nm) and/or at most about 10 microns (e.g., at most about five microns, at most about three microns, at most about one micron).
  • layer 128 has a thickness of at least about 10 nm (e.g., at least about 25 nm, at least about 40 nm) and/or at most about one micron (e.g., at most about 500 nm, at most about 100 nm).
  • layer 126 has a thickness of at least about 10 nm (e.g., at least about 50 nm, at least about 100 nm) and/or at most about one micron (e.g., at most about 500 nm, at most about 250 nm).
  • light-generating region 130 has a thickness of at least about 10 nm (e.g., at least about 25 nm, at least about 50 nm, at least about 100 nm) and/or at most about 500 nm (e.g., at most about 250 nm, at most about 150 nm).
  • a light-emitting diode has been described, other light- emitting devices having the above-described features (e.g., patterns, processes) can be used. Such light-emitting devices include lasers and optical amplifiers.
  • cunent spreading layer 132 has been described as a separate layer from n-doped layer 134, in some embodiments, a cunent spreading layer can be integral with (e.g., a portion of) layer 134. In such embodiments, the cunent spreading layer can be a relatively highly n-doped portion of layer 134 or a heteroj unction between (e.g. AlGaN/GaN) to form a 2D electron gas.
  • any semiconductor materials e.g., III-V semiconductor materials, organic semiconductor materials, silicon
  • any semiconductor materials can be used that can be used in a light-emitting device.
  • Examples of other light-generating materials include InGaAsP, AlInGaN, AlGaAs, InGaAlP.
  • Organic light-emitting materials include small molecules such as aluminum tris-8- hydroxyquinoline (Alq 3 ) and conjugated polymers such as poly[2-methoxy-5-(2- ethylhexyloxy)-l,4-vinylenephenylene] or MEH-PPV.
  • the LEDs can also be small area LEDs (e.g., LEDs smaller than the standard about 300 microns on edge).
  • a dielectric function that varies spatially according to a pattern has been described in which the pattern is formed of holes, the pattern can also be formed in other ways.
  • a pattern can be formed continuous veins and/or discontinuous veins in the appropriate layer.
  • the pattern in varying dielectric function can be achieved without using holes or veins.
  • materials having different dielectric functions can be patterned in the appropriate layer. Combinations of such patterns can also be used.
  • layer 126 has been described as being formed of silver, other materials can also be used.
  • layer 126 is formed of a material that can reflect at least about 50% of light generated by the light-generating region that impinges on the layer of reflective material, the layer of reflective material being between the support and the multi-layer stack of materials.
  • materials include distributed Bragg reflector stacks and various metals and alloys, such as aluminum and aluminum-containing alloys.
  • support 120 can be formed of a variety of materials. Examples of materials from which support 120 can be formed include copper, copper- tungsten, aluminum nitride, silicon carbide, beryllium-oxide, diamonds, TEC, and aluminum.
  • a light-emitting device can include a separate layer (e.g., disposed between layer 126 and submount 120) that serves as a heat sink.
  • layer 126 may or may not be formed of a material that can serve as a heat sink.
  • the varying pattern in dielectric function has been described as extending into n-doped layer 134 only (which can substantially reduce the likelihood of surface recombination carrier losses) in addition to making use of the entire light-generating region, in some embodiments, the varying pattern in dielectric function can extend beyond n-doped layer (e.g., into cunent spreading layer 132, light-generating region 130, and/or p-doped layer 128).
  • n-doped layer e.g., into cunent spreading layer 132, light-generating region 130, and/or p-doped layer 128).
  • air can be disposed between surface 110 can cover slip 140
  • materials other than, or in an addition to, air can be disposed between surface 110 and cover slip 140.
  • such materials have an index of refraction of at least about one and less than about 1.5 (e.g., less than about 1.4, less than about 1.3, less than about 1.2, less than about 1.1).
  • examples of such materials include nitrogen, air, or some higher thermal conductivity gas.
  • surface 110 may or may not be patterned.
  • surface 110 may be non-patterned but may be roughened (i.e., having randomly distributed features of various sizes and shapes less than ⁇ /5).
  • a pre-patterned etch mask can be laid down on the surface of the n-doped semiconductor layer.
  • an etch mask layer can be disposed between the n-doped semiconductor layer and the planarization layer.
  • the method can include removing at least a portion of the etch mask layer (e.g., to form a pattern in the etch stop layer conesponding to the pattern in the n-doped semiconductor layer).
  • surface 110 may be patterned and rough (i.e., having randomly distributed features of various sizes and shapes less than ⁇ /5, less than ⁇ /2, less than ⁇ ).
  • the sidewalls of openings 150 can be rough (i.e., having randomly distributed features of various sizes and shapes less than ⁇ /5, less than ⁇ 2, less than ⁇ ), with or without surface 110 being rough.
  • the bottom surface of openings 150 can be rough (i.e., having randomly distributed features of various sizes and shapes less than ⁇ /5, less than ⁇ /2, less than ⁇ ).
  • Surface 110, the sidewalls of openings 150, and/or the bottom surfaces of openings 150 can be roughened, for example, by etching (e.g., wet etching, dry etching, reactive ion etching).
  • the submount can be machined to include spring-like structures. Without wishing to be bound by theory, it is believed that such spring-like structures may reduce cracking during removal of the substrate.
  • the submount can be supported by an acoustically absorbing platform (e.g., a polymer, a metallic foam).
  • the substrate is treated (e.g., etched, ground, sandblasted) before being removed.
  • the substrate may be patterned before it is removed.
  • the thickness of the layers is selected so that, before removing the substrate and buffer layers, the neutral mechanical axis of the multi-layer stack is located substantially close (e.g., less than about 500 microns, less than about 100 microns, less than about 10 microns, less than about five microns) to the interface between the p-doped semiconductor layer and a bonding layer.
  • portions of the substrate are separately removed (e.g., to reduce the likelihood of cracking).
  • a buffer layer is separate from an n-doped semiconductor layer (e.g., a buffer layer grown on the substrate, with an n-doped semiconductor layer separately grown on the buffer)
  • the single layer can be formed by first depositing a relatively low doped (e.g., undoped) semiconductor material on the substrate, followed by (in one process) depositing a relatively high doped (n-doped) semiconductor material.
  • a substrate is removed by a process that includes exposing a surface of the substrate to electromagnetic radiation (e.g., laser light)
  • electromagnetic radiation e.g., laser light
  • other methods can be used to remove the substrate.
  • removal of the substrate can involve etching and/or lapping the substrate.
  • the substrate can be etched and/or lapped, and then subsequently exposed to electromagnetic radiation (e.g., laser light).
  • the upper surface of the planarization layer can be flattened.
  • a flat object such as an optical flat
  • a pressure can be applied (e.g., using a physical weight or press) to assist with the flattening process.
  • the substrate can be treated before being removed.
  • the substrate can be exposed to one or more processes selected from etching, polishing, grinding, and sandblasting.
  • treating the substrate can include patterning the substrate.
  • treating the substrate includes depositing an antireflective coating on the substrate.
  • a light-emitting device can include a layer of a phosphor material coated on surface 110, cover layer 140 and supports 142.
  • a light-emitting device can include a cover layer 140 that has a phosphor material disposed therein. In such embodiments, surface 110 may or may not be patterned.
  • the light emitted by the light-generating region 130 is UV (or violet, or blue) and the phosphor layer 180 includes a mixture of a red phosphor material (e.g., L 2 O 2 S:Eu 3+ ), a green phosphor material (e.g, ZnS:Cu,Al,Mn), and blue phosphor material (e.g, (Sr,Ca,Ba,Mg) ⁇ 0 (PO 4 ) 6 Cl:Eu 2+ ).
  • a red phosphor material e.g., L 2 O 2 S:Eu 3+
  • a green phosphor material e.g, ZnS:Cu,Al,Mn
  • blue phosphor material e.g, (Sr,Ca,Ba,Mg) ⁇ 0 (PO 4 ) 6 Cl:Eu 2+ .
  • Other embodiments are in the claims.

Abstract

L'invention concerne des structures de contact d'un dispositif électronique.
PCT/US2004/040900 2003-12-12 2004-12-08 Structures de contact d'un dispositif electronique WO2005060586A2 (fr)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US10/735,498 US7166871B2 (en) 2003-04-15 2003-12-12 Light emitting systems
US10/735,498 2003-12-12
US10/794,244 2004-03-05
US10/794,244 US20040259279A1 (en) 2003-04-15 2004-03-05 Light emitting device methods
US10/794,452 2004-03-05
US10/794,452 US7074631B2 (en) 2003-04-15 2004-03-05 Light emitting device methods
US55389404P 2004-03-16 2004-03-16
US60/553,894 2004-03-16
US10/871,877 2004-06-18
US10/871,877 US7105861B2 (en) 2003-04-15 2004-06-18 Electronic device contact structures

Publications (2)

Publication Number Publication Date
WO2005060586A2 true WO2005060586A2 (fr) 2005-07-07
WO2005060586A3 WO2005060586A3 (fr) 2006-03-30

Family

ID=34714664

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/040900 WO2005060586A2 (fr) 2003-12-12 2004-12-08 Structures de contact d'un dispositif electronique

Country Status (2)

Country Link
TW (1) TWI371866B (fr)
WO (1) WO2005060586A2 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006013408A1 (de) * 2006-03-17 2007-09-20 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Leuchtdiodenelement
DE102008019049A1 (de) * 2008-04-15 2009-10-29 Novaled Ag Lichtemittierendes organisches Bauelement und Anordnung
CN109075057A (zh) * 2016-03-09 2018-12-21 应用材料公司 垫结构及制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI471069B (zh) * 2013-05-22 2015-01-21 Takamatsu Plating Co Ltd Ｌｅｄ用的金屬基板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3293513A (en) * 1962-08-08 1966-12-20 Texas Instruments Inc Semiconductor radiant diode
US3922706A (en) * 1965-07-31 1975-11-25 Telefunken Patent Transistor having emitter with high circumference-surface area ratio
US4864370A (en) * 1987-11-16 1989-09-05 Motorola, Inc. Electrical contact for an LED
US6307218B1 (en) * 1998-11-20 2001-10-23 Lumileds Lighting, U.S., Llc Electrode structures for light emitting devices
US20050051785A1 (en) * 2003-04-15 2005-03-10 Erchak Alexei A. Electronic device contact structures

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3293513A (en) * 1962-08-08 1966-12-20 Texas Instruments Inc Semiconductor radiant diode
US3922706A (en) * 1965-07-31 1975-11-25 Telefunken Patent Transistor having emitter with high circumference-surface area ratio
US4864370A (en) * 1987-11-16 1989-09-05 Motorola, Inc. Electrical contact for an LED
US6307218B1 (en) * 1998-11-20 2001-10-23 Lumileds Lighting, U.S., Llc Electrode structures for light emitting devices
US20050051785A1 (en) * 2003-04-15 2005-03-10 Erchak Alexei A. Electronic device contact structures

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006013408A1 (de) * 2006-03-17 2007-09-20 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Leuchtdiodenelement
DE102008019049A1 (de) * 2008-04-15 2009-10-29 Novaled Ag Lichtemittierendes organisches Bauelement und Anordnung
US8466457B2 (en) 2008-04-15 2013-06-18 Novaled Ag Light-emitting organic component, arrangement having a plurality of light-emitting organic components and electrode structure
DE102008019049B4 (de) * 2008-04-15 2013-12-24 Novaled Ag Lichtemittierendes organisches Bauelement und Anordnung
CN109075057A (zh) * 2016-03-09 2018-12-21 应用材料公司 垫结构及制造方法
CN109075057B (zh) * 2016-03-09 2023-10-20 应用材料公司 垫结构及制造方法

Also Published As

Publication number Publication date
WO2005060586A3 (fr) 2006-03-30
TWI371866B (en) 2012-09-01
TW200531311A (en) 2005-09-16

Similar Documents

Publication Publication Date Title
US7934841B2 (en) Optical display systems and methods
US8426872B2 (en) Light emitting diode systems including optical display systems having a microdisplay
US7105861B2 (en) Electronic device contact structures
US7737450B2 (en) Light emitting diode systems
US7341880B2 (en) Light emitting device processes
US7344903B2 (en) Light emitting device processes
US8162526B2 (en) Light-emitting devices for liquid crystal displays
US7667238B2 (en) Light emitting devices for liquid crystal displays
US7166871B2 (en) Light emitting systems
US7521273B2 (en) Light emitting device methods
US7074631B2 (en) Light emitting device methods
US20060043400A1 (en) Polarized light emitting device
WO2006096671A2 (fr) Dispositifs electroluminescents pour affichages a cristaux liquides
US20090023239A1 (en) Light emitting device processes
WO2005060586A2 (fr) Structures de contact d'un dispositif electronique

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase