Classifications

• • G—PHYSICS
  • G02—OPTICS
  • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
  • G02B26/00—Optical devices or arrangements for the control of light using movable or deformable optical elements
  • G02B26/08—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
  • G02B26/0816—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements
  • G02B26/0833—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD
  • G02B26/0841—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD the reflecting element being moved or deformed by electrostatic means

Definitions

• This invention relates to electromechanical micromirror devices and methods of manufacturing the same. When fabricated in an array, such devices can be used as a spatial light modulator.
• Electromechanical micromirror devices have drawn considerable interest because of their application as spatial light modulators (SLMs).
• SLMs spatial light modulators
• a spatial light modulator requires an array of a relatively large number of such micromirror devices. In general, the number of devices required ranges from 60,000 to several million for each SLM.
• SLMs spatial light modulators
• An example of an early generation prior art device is disclosed in US 4592628. US 4592628 describes an array of light reflecting devices on a substrate.
• Each device comprises a hollow post and a deflectable polygonal mirror attached thereto.
• Each mirror acts as a deflectable cantilever beam.
• the mirrors are deflected by a beam of electrons from a cathode ray tube.
• the substrate does not contain any addressing circuits.
• Another early generation device is disclosed in US 4229732. In this case, addressing circuits using MOSFETs were fabricated on the surface of the substrate. Deflectable metallic mirrors were also fabricated on the surface of the substrate. Since the MOSFET circuits and mirrors could not overlap, the fill factor of the array was not as high as if the mirrors could cover the entire surface area.
• a 1st generation Texas Instruments, Inc. (TT) device is described in US 4662746.
• a micromirror is suspended by 1 or 2 hinges. If suspended by 1 hinge, the micromirror deflects like a cantilever beam. If suspended by 2 hinges, the micromirror deflects like a torsion beam.
• Addressing electrodes are located below the micromirrors and addressing circuits are located at the same level in the substrate as the addressing electrodes.
• An improved 1st generation TI device is described in US 5061049. In this patent, each mirror is provided with 2 addressing electrodes and 2 landing electrodes. The landing electrodes soften the landing of the mirrors and are also used to reset the mirrors by a suitable voltage sequence. The use of these landing electrodes allows the mirrors to function as a bistable device.
• a 2nd generation TI device is described in US 5583688. A 2nd generation
• TI device is one in which the torsion hinge is at a different level than the reflective mirror.
• the mirror is supported by a mirror support post, which is attached to the torsion hinge by a yoke.
• the mirrors are actuated by electrostatic forces between the mirror and address electrodes.
• Micromirrors that are described in US 4662746, US 5061049, US 5583688, and US 5535047 are fabricated on top of CMOS circuits.
• the surface of the CMOS chip has certain manufacturing artifacts, namely aluminum hillocks, pinholes, nonplanar surfaces, and steep sidewalk in the protective oxide at edges of aluminum leads.
• US 5216537 discloses an improved architecture in which an air gap is provided between the top surface of the CMOS chip and the mirror addressing electrodes.
• a further advantage of this approach is that because of the low dielectric constant of air, parasitic coupling between the CMOS and the micromirror is reduced.
• the placement of CMOS circuits directly under the micromirrors is also responsible for problems of photosensitivity. As discussed in US 6344672, it was found that the CMOS memory cells are unstable in a high-intensity light environment. The patent provided an active collector region in which photogenerated carriers could recombine before reaching the addressing electrode.
• Reflectivity, Inc. (Sunnyvale, California) is also known to be developing micromirror devices.
• CMOS and micromirrors are solved by placing the micromirrors and CMOS on different substrates.
• a hinge and a micromirror are fabricated on an optically transparent substrate, such that the optically reflective surface of the rmcro ⁇ rror is proximate the optically transparent substrate.
• Addressing circuits including mirror addressing electrodes are fabricated on a 2nd substrate (typically silicon) and the 2 substrates are bonded together with a predetermined gap between the micromirror and the addressing electrodes.
• the hinges are placed on the side of the mirror opposite to the side that is proximate the optically transparent substrate.
• US 6538800 also discusses the use of amorphous silicon as a sacrificial layer. It is shown that amorphous silicon can be deposited for this purpose by LPCVD in a quartz tube of a Tylan furnace. It is also shown that a xenon difluoride etch process can be used to etch amorphous silicon with a selectivity of
• amorphous silicon can be used successfully as a sacrificial layer in addition to photoresists, silicon oxide, silicon nitride, and silicon oxynitride.
• an electromechanical micromirror device comprises a device substrate with a 1st surface and a 2nd surface, control circuitry disposed on said 1st surface, and a micromirror disposed on said 2nd surface.
• the present invention also relates to arrays of such micromirror devices.
• Such arrays may be used as a spatial light modulators (SLMs).
• SLMs spatial light modulators
• the arrays may be 1-dimensional (linear) or 2-dimensional.
• methods of fabricating micromirror devices and arrays of such devices generally involve providing a device substrate with a 1st surface and a 2nd surface, fabricating control circuitry on the 1st surface, and fabricating micromirror(s) on the 2nd surface.
• control circuits are fabricated using CMOS technology.
• the control circuits on the 1st surface are protected by a protective layer during the fabrication of micromirrors on the 2nd surface.
• the device substrate is a silicon-on-insulator (SOI) substrate.
• a 1st advantage of the present invention is that it provides improved dielectric isolation between the control circuit and the micromirror.
• a 2nd advantage of the present invention is that provides improved optical isolation of the control circuit area. This is particularly advantageous when the micromirror array is used as a spatial light modulator (SLM) and the 1st surface (the micromirror side) is exposed to high intensity radiation.
• a 3rd advantage of the present invention is that it provides improved manufacturing yields because the control circuit manufacturing processes and micromirror manufacturing processes can be substantially isolated from each other. In other words, manufacturing artifacts arising from the control circuit process will not damage the micromirror because the micromirror is not built on top of the control circuit.
• Fig. 1 is a schematic diagram of a 4-pixel array of micromirror devices, comprising control circuits, addressing electrodes, and micromirrors.
• Fig. 2 is a schematic cross sectional view of a micromirror device in accordance with the present invention.
• Fig. 3A is a schematic plan view of a micromirror device in accordance with a 1st embodiment of the present invention.
• Fig. 3B is a schematic cross sectional view along line a-b of Fig. 3A.
• Fig. 4A is a schematic plan view of a micromirror device in accordance with a 2nd embodiment of the present invention.
• Fig. 4B is a schematic cross sectional view along line c-d of Fig. 4A.
• Fig. 5A is a schematic plan view of a nricrornirror device in accordance with a 3rd embodiment of the present invention.
• Fig. 5B is a schematic cross sectional view along line e-f of Fig. 5A.
• FIGs. 6A through 6D are schematic plan views of a micromirror device according to a 4th embodiment of the present invention, at varying levels of elevation.
• Figs. 7A through 7D are cross sectional views illustrating the fabrication steps on a 1st device substrate surface, in accordance with a 4th embodiment of the present invention.
• Figs. 8A through 8M are cross sectional views illustrating the fabrication steps on a 2nd device substrate surface, in accordance with a 4th embodiment of the present invention.
• Fig. 9 is a schematic plan view illustrating a micromirror array of rectangular micromirrors according to a 5th embodiment of the present invention.
• Fig. 10 is a schematic plan view illustrating an array of hexagonal micromirrors in accordance with a 6th embodiment of the present invention.
• Fig. 11 A is a schematic plan view of a micromirror device in accordance with a 7th embodiment of the present invention.
• Fig. 11B is a schematic cross sectional view along line i-j of Fig. 11A.
• Fig. 11C is a schematic plan view of a micromirror device in accordance with an 8th embodiment of the present invention.
• the present invention relates to electromechanical micromirror devices and arrays of such devices. Shown schematically in Fig. 1 is an array 100 comprising vertical data lines (101 and 102) and horizontal addressing lines (103 and 104), with each intersection of these data and addressing lines forming an electromechanical micromirror device (105, 106, 107, and 108). Each micromirror device comprises a micromirror (109, 110, 111, and 112), an addressing electrode (113, 114, 115, and 116), and an NMOS transistor (117, 118, 119, and 120). Micromirror 109 is shown to be in a deflected state while the other micromirrors are in their undeflected states.
• a possible scheme for addressing the micromirrors is as follows: The micromirrors (109, 110, 111, and 112) are electrically connected to ground. The deflection of a micromirror is determined by the bias voltage between the micromirror and its addressing electrode. The desired bias voltage is set by the voltages on the vertical data lines (101 and 102). The NMOS transistors are turned on by sending a low-high-low pulse on the addressing lines (103 and 104), which results in the bias voltages being stored between the micromirrors and addressing electrodes. [0035] While array 100 (Fig.
• Fig. 1 shows a plurality of micromirror devices disposed in a 2-dimensional array, 1-dimensional (linear) array are also possible.
• the circuitry as shown in Fig. 1 comprises the following:
• control circuitry consists of the vertical data lines (101 and 102), horizontal addressing lines (103 and 104), NMOS transistors (117,
• control circuitry is understood to mean any circuitry that is provided to control the application of bias voltages between a micromirror and its addressing electrode. As shown in Fig. 1, the control circuitry comprised NMOS transistors.
• control circuitry could comprise other types of circuits, including CMOS circuits, PMOS circuits, bipolar transistor circuits, BiCMOS circuits, DMOS circuits, HEMT circuits, amorphous silicon thin film transistor circuits, polysilicon thin film transistor circuits, SiGe transistor circuits, SiC transistor circuits, GaN transistor circuits, GaAs transistor circuits, InP transistor circuits, CdSe transistor circuits, organic transistor circuits, and conjugated polymer transistor circuits.
• a device substrate 201 has a bottom surface on which control circuitry 202 is fabricated.
• Micromirror 203 and addressing electrodes 204 and 205 are fabricated on the top surface of substrate 201.
• support structures for supporting micromirror 203 are not shown.
• Electrical connections between the addressing electrodes (203 and 204) and control circuitry 202 are provided by electrical routing lines 206 and 207.
• the electrical routing lines 206 and 207 may be in the form of vias in the device substrate 201 with metallization in these vias.
• the device substrate may be selected from among the following: silicon-on-insulator (SOI), silicon, polycrystalline silicon, glass, plastic, ceramic, germanium, SiGe, SiC, sapphire, quartz, GaAs, and InP.
• SOI silicon-on-insulator
• a silicon-on-insulator substrate may be suitable for CMOS circuits
• a glass substrate may be suitable for amorphous silicon thin film transistor circuits.
• a micromirror device comprises a control circuitry, a micrornirror, and addressing electrodes.
• FIG. 3A is a schematic plan view of a portion of a micromirror device 300 in accordance with a 1st embodiment of the present invention.
• Micromirror 301 is shown with its reflective side facing towards the reader.
• the reflective side of micromirror 301 is substantially planar, with neither recessions nor protrusions.
• Micromirror 301 is supported by a torsion hinge 302.
• arrow 303 indicates the projection of the incident light propagation direction on the device substrate plane.
• micromirror 301 has 4 edges and no edge is perpendicular to arrow 303.
• FIG. 3B is a schematic cross sectional view along line a-b through torsion hinge 302.
• Micromirror 301 and torsion hinge 302 are supported by support structures 304 and 305, which are disposed on device substrate 306. Since the micromirror deflects by torsion, the axis of rotation of the micromirror is approximately perpendicular to arrow 303.
• Fig. 4A is a schematic plan view of a portion of a micromirror device 400 in accordance with a 2nd embodiment of the present invention.
• Micromirror 401 is shown with its reflective side facing towards the reader.
• the reflective side of micromirror 401 is substantially planar, with neither recessions nor protrusions.
• Micromirror 401 is supported by a beam 402.
• arrow 403 indicates the projection of the incident light propagation direction on the device substrate plane.
• micromirror 401 has 4 edges and no edge is perpendicular to arrow 403.
• Fig. 4B is a schematic cross sectional view along line c-d through beam 402. Beam 402 is supported by support structure 404, which is disposed on device substrate 406. In contrast to micromirror 301 (Figs. 3A and
• FIG. 5A is a schematic plan view of a portion of a micromirror device 500 in accordance with a 3rd embodiment of the present invention.
• Micromirror 501 is shown with its reflective side facing towards the reader.
• the reflective side of micromirror 501 is substantially planar, with neither recessions nor protrusions.
• micromirror device 500 is disposed in an array for a spatial light modulator (SLM)
• arrow 503 indicates the projection of the incident light propagation direction on the device substrate plane.
• Fig. 5B is a schematic cross sectional view along line e-f.
• Micromirror 501 is supported by a support structure 504, which is disposed on device substrate 506.
• the axis of rotation of micromirror 501 is approximately parallel to arrow 503.
• micromirror device 500 (Figs. 5A and 5B) and micromirror device 500 (Figs. 5A and 5B) is that in device 400, there is a beam 402 which supports the micrornirror 401 on the support structure 404, whereas in device 500, the micromirror is positioned directly on support structure 504. Therefore, in Fig. 5A, the top side 502 of support structure 504 is visible in the plan view.
• Figs. 6A through 6D are schematic plan views of a micromirror device 600 accoding to a 4th embodiment of the present invention, at varying levels of elevation.
• Fig. 6 A shows the reflective side (top side) of a micromirror 601.
• arrow 602 indicates the projection of the incident light propagation vector on the device substrate plane.
• Arrow 602 is not perpendicular to any of the 4 sides of micromirror 601.
• Arrow 602 is shown to be approximately 45 degrees from the leading edges of micromirror 601.
• the reflective side of micromirror 601 is substantially flat, with neither recesses nor protrusions. As a result, there are no diffraction effects that would be caused by recesses or protrusions in the micromirror.
• Fig. 6B shows a plan view that is analogous to Fig. 6A except that micromirror 601 has been removed. Addressing electrodes 603 and 604, micromirror support structure 605, and torsion hinge 606 are visible. Torsion hinge 606 supports micromirror support structure 605. Addressing electrodes
• Micromirror 601 is actuated by electrostatic forces between it and one or both of the addressing electrodes 603 and 604.
• Fig. 6C shows the result of removing the mirror support structure 605.
• Fig. 6D shows the result of removing torsion hinge 606.
• Torsion hinge support structures 607 and 608 are shown.
• Figs. 7A through 7D and 8A through 8M show a fabrication sequence of a micromirror device using a cross sectional view along the line g-h. In many cases, the micromirror device would be fabricated in an array for use as a spatial light modulator. Therefore, although Figs.
• FIG. 7A through 7D and 8A through 8M illustrate the fabrication of a single micromirror device, it should be understood that the teachings can be extended to the fabrication of an array of micromirror devices.
• Figs. 7A through 7D illustrate a fabrication sequence on the control circuitry side.
• Fig. 7A shows a silicon-on-insulator (SOI) substrate 700 comprising an epitaxial top silicon layer 703 with a thickness typically ranging from 50 ran to 600 ran, an intermediate insulator layer 702 with a thickness typically ranging from 50 run to 2 m, and a bottom silicon layer 701 with a thickness of around 775 m.
• SOI silicon-on-insulator
• the SOI substrate is used to improve the dielectric isolation of the control circuitry and micromirror portion.
• Fig. 7B shows the formation of control circuitry 704 on epitaxial layer 703 of the SOI substrate 700.
• any integrated circuit technology can be considered for fabricating the control circuitry.
• CMOS circuitry may be used.
• BiCMOS or DMOS circuitry may be used.
• Fig. 7C shows the step of forming a trench 705 through the top epitaxial silicon layer 703 and insulator layer 702, using standard patterning and an anisotropic etch. The anisotropic etch is stopped before the trench 705 reaches the bottom silicon layer 701.
• a metal deposition and patterning step (Fig. 7D) which forms an electrical connection 706 between the control circuitry and the trench.
• this metal could be any metal that is used in semiconductor fabrication, such as Al alloy, and methods of metal deposition include sputtering, thermal evaporation, and CVD.
• Figs. 8A through 8M illustrate a fabrication sequence on the micromirror side. The control circuitry side is mounted on a carrier to securely hold the substrate for the subsequent step (Fig.
• insulator layer 702 is pattered to form a trench 801, thereby completing the via that had been started in the step of Fig. 7C.
• Another metallization (deposition and patterning) step forms addressing electrodes 802 that are electrically connected, through via 801, to control circuitry 704.
• the torsion hinge and its support structures are formed. An embodiment of this process is illustrated in Figs. 8D through 8H.
• An amorphous silicon sacrificial layer 803 is deposited by LPCVD (Fig. 8D).
• LPCVD LPCVD
• Other suitable methods of depositing amorphous silicon are PECVD, catalytic CVD (also known as hot wire CVD), and sputtering.
• xenon difluoride can be used to etch amorphous silicon with a selectivity of 100 to 1.
• Other possible sacrificial layers are photoresists, silicon oxide, silicon nitride, and silicon oxynitride.
• a photolithographic patterning and anisotropic etching step is carried out to form a recess 804 where the torsion hinge will be formed.
• FIG. 8F Another photolithographic patterning and anisotropic etching step (Fig. 8F) is carried out to form holes 805 and 806 where the torsion hinge support structures will be formed.
• the holes 805 and 806 for the torsion hinge support structures reach the intermediate insulator layer.
• a layer 807 of structural material is deposited.
• the structural material may be an Al alloy comprising 0.2 % Ti, 1 % Si, and the remainder Al.
• a preferred method of depositing this Al alloy is sputter deposition.
• a metal is chosen for the structural material because the micromirror is typically held at ground potential.
• structural material layer 807 is patterned to form a torsion hinge 808 and torsion hinge support structures 809 and 810. Torsion hinge 808 and torsion hinge support structures 809 and 810 are at least partially embedded in sacrificial layer 803.
• a micrornirror support structure is placed between the torsion beam and the micromirror.
• a metal layer is deposited and then patterned to provide a micrornirror support structure 811 on torsion beam 808.
• the metal may be an Al alloy comprising 0.2 % Ti, 1 % Si, and the remainder Al.
• a preferred method of depositing this Al alloy is sputter deposition.
• Another layer of sacrificial amorphous silicon is deposited (Fig. 8J) such that the micromirror support structure 811 is fully covered by sacrificial layer 803.
• a chemical mechanical polishing (CMP) process is carried out to planarize the surface such that the following requirements are satisfied:
• the sacrificial layer 803 is planar; and 3) the top of the rmcromirror support structure 811 and the top of the sacrificial layer 803 are at the same level.
• Fig. 8K The result of the planarization step is shown schematically in Fig. 8K.
• a metallic layer is deposited and patterned to form a micromirror 812 as shown in Fig. 8L.
• the metal may be an Al alloy comprising 0.2 % Ti, 1 % Si, and the remainder Al.
• a preferred method of depositing this Al alloy is sputter deposition.
• the micromirror 812 is connected to the micromirror support structure 811.
• a xenon difluoride etch is carried out to remove the amorphous silicon sacrificial layer (Fig. 8M).
• the preferred micrornirror comprised a metallic coating.
• Fig. 9 shows a 2-dimensional array 900 of rectangular micromirrors (901, 902, 903, and 904), according to a 5th embodiment of the present invention.
• Arrow 906 indicates the projection of the incident light propagation vector on the mirror plane (device substrate plane).
• the reflective side of the micromirror has no edges that are perpendicular to arrow 906. This is a configuration that reduces diffraction into the acceptance cone of the optical system.
• Another possible shape for a micromirror is a hexagon, shown being disposed in an array 1000 in Fig. 10, according to a 6th embodiment of the present invention.
• FIG. 11A is a schematic plane view of a micromirror device
• Fig. 11B is a schematic cross sectional view along line i-j of Fig. 11A.
• An addressing electrode 1108 is located under micromirror 1101 and on top of device substrate 1106. Furthermore, a stopper 1107 has been provided. The purpose of stopper 1107 is to prevent micromirror 1101 from contacting addressing electrode 1108 under deflection.
• Fig. 11C illustrates a modification to micromirror device 1100 in accordance with an 8th embodiment of the present invention.
• Fig. 11C is a plan view of a micromirror device 1100 comprising a micromirror 1101, a support structure 1104, and a stopper 1107. In its undeflected state, the reflective side of micromirror 1101 has no edges that are perpendicular to arrow 1103.
• region 1108 of micromirror 1101 that is adjacent to support structure 1104 gets deflected. Therefore, an edge that is perpendicular to arrow 1103 may appear in region 1108. In order to reduce diffraction effects from this edge, it is possible to coat region 1108 with a light absorbing material.
• a preferred light absorbing material is a black dye.

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• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Optics & Photonics (AREA)
• Mechanical Light Control Or Optical Switches (AREA)
• Micromachines (AREA)
• Mechanical Optical Scanning Systems (AREA)

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• 2003
  • 2003-11-01 US US10/698,620 patent/US20050094241A1/en not_active Abandoned
• 2004
  • 2004-10-29 WO PCT/US2004/035974 patent/WO2005046206A2/en not_active Ceased
  • 2004-10-29 JP JP2006538296A patent/JP4586146B2/ja not_active Expired - Fee Related
• 2005
  • 2005-07-23 US US11/187,248 patent/US7375872B2/en not_active Expired - Lifetime
• 2008
  • 2008-02-12 US US12/069,837 patent/US7746538B2/en not_active Expired - Fee Related

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