WO2005043601A2 - Appareil et procede de formation de circuits integres composes - Google Patents

Appareil et procede de formation de circuits integres composes Download PDF

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Publication number
WO2005043601A2
WO2005043601A2 PCT/US2004/036739 US2004036739W WO2005043601A2 WO 2005043601 A2 WO2005043601 A2 WO 2005043601A2 US 2004036739 W US2004036739 W US 2004036739W WO 2005043601 A2 WO2005043601 A2 WO 2005043601A2
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
integrated circuit
seal ring
master
compound
Prior art date
Application number
PCT/US2004/036739
Other languages
English (en)
Other versions
WO2005043601A3 (fr
Inventor
Stephen Charles Bateman
Douglas John Bailey
David John Coakley
Original Assignee
Chipx Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipx Incorporated filed Critical Chipx Incorporated
Publication of WO2005043601A2 publication Critical patent/WO2005043601A2/fr
Publication of WO2005043601A3 publication Critical patent/WO2005043601A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology

Definitions

  • Memory 304 can include RAM (e.g., SRAM) and/or ROM memory and can be programmed as single-port, dual-port, first- in-first-out, or as other like memory configurations.
  • Inputs 306 and outputs 308 can include one or more simple inputs and output, respectively, such as CMOS, TTL, or the like. Inputs 306 and outputs 308 can be configured to operate jointly to form bi-directional, high-input impedance I/Os.
  • lower seal ring 703 and upper seal ring 702 need not be formed 90 degrees with the substrate and can each be formed by staggering constituent vias horizontally in each subsequent fabrication layer.
  • pad 708 and its underlying pad support 732 are formed vertically over inoperative logic of peripheral master module 730.
  • upper seal ring 702 is formed at least a particular distance from one edge of inoperative logic so as to provide an interconnect area on the surface of peripheral master module 730. This area enables pad 708 to be placed beyond the usual seal ring barrier, which is typically defined as the location of lower seal ring 703.
  • the inoperative logic provides at least some support for pad support 732.

Abstract

La présente invention concerne des circuits modulaires ainsi que des procédés de fabrication à la fois de circuits modulaires ('modules maîtres') et de circuits intégrés composés. Ces modules maîtres sont conçus pour réduire au minimum les pertes et pour répartir uniformément la puissance dans l'ensemble de leur structure. Par ailleurs, un certain nombre de modules maîtres et un circuit intégré composé constitué d'un groupe de ces modules maîtres sont structurés de façon que les effets de contraintes mécaniques soient réduits au minimum. Dans un mode de réalisation, un substrat comprend des modules maîtres répartis sur une surface du substrat, chacun de ces modules maîtres comprenant, par exemple, un ou plusieurs circuits logiques, une mémoire, une interface d'entrée et une interface de sortie.
PCT/US2004/036739 2003-11-03 2004-11-03 Appareil et procede de formation de circuits integres composes WO2005043601A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US70137503A 2003-11-03 2003-11-03
US10/701,375 2003-11-03

Publications (2)

Publication Number Publication Date
WO2005043601A2 true WO2005043601A2 (fr) 2005-05-12
WO2005043601A3 WO2005043601A3 (fr) 2005-12-01

Family

ID=34551413

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/036739 WO2005043601A2 (fr) 2003-11-03 2004-11-03 Appareil et procede de formation de circuits integres composes

Country Status (1)

Country Link
WO (1) WO2005043601A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI823617B (zh) * 2022-10-14 2023-11-21 鯨鏈科技股份有限公司 可重組式容量頻寬記憶體結構及其製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6175952B1 (en) * 1997-05-27 2001-01-16 Altera Corporation Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions
US6226779B1 (en) * 1997-09-29 2001-05-01 Xilinx, Inc. Programmable IC with gate array core and boundary scan capability
US6480989B2 (en) * 1998-06-29 2002-11-12 Lsi Logic Corporation Integrated circuit design incorporating a power mesh
US6564364B1 (en) * 2000-11-15 2003-05-13 Reshape, Inc. Method and system for maintaining element abstracts of an integrated circuit netlist using a master library file and modifiable master library file

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6604228B1 (en) * 1996-05-28 2003-08-05 Altera Corporation Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions
US6175952B1 (en) * 1997-05-27 2001-01-16 Altera Corporation Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions
US6226779B1 (en) * 1997-09-29 2001-05-01 Xilinx, Inc. Programmable IC with gate array core and boundary scan capability
US6480989B2 (en) * 1998-06-29 2002-11-12 Lsi Logic Corporation Integrated circuit design incorporating a power mesh
US6564364B1 (en) * 2000-11-15 2003-05-13 Reshape, Inc. Method and system for maintaining element abstracts of an integrated circuit netlist using a master library file and modifiable master library file

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI823617B (zh) * 2022-10-14 2023-11-21 鯨鏈科技股份有限公司 可重組式容量頻寬記憶體結構及其製造方法

Also Published As

Publication number Publication date
WO2005043601A3 (fr) 2005-12-01

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