WO2005041407A1 - Filtrage numerique - Google Patents

Filtrage numerique Download PDF

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Publication number
WO2005041407A1
WO2005041407A1 PCT/IB2004/052102 IB2004052102W WO2005041407A1 WO 2005041407 A1 WO2005041407 A1 WO 2005041407A1 IB 2004052102 W IB2004052102 W IB 2004052102W WO 2005041407 A1 WO2005041407 A1 WO 2005041407A1
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WO
WIPO (PCT)
Prior art keywords
signal
filtered
signals
linear combination
filtering
Prior art date
Application number
PCT/IB2004/052102
Other languages
English (en)
Inventor
Peter Bode
Rainer Dietsch
Original Assignee
Philips Intellectual Property & Standards Gmbh
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Intellectual Property & Standards Gmbh, Koninklijke Philips Electronics N.V. filed Critical Philips Intellectual Property & Standards Gmbh
Publication of WO2005041407A1 publication Critical patent/WO2005041407A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0233—Measures concerning the signal representation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0225—Measures concerning the multipliers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters

Definitions

  • the present invention relates to the digital filtering of a signal. More particularly, the present invention relates to a method of digitally filtering a signal, a digital filter and a software program product for performing the method of digitally filtering a signal.
  • Digital filters have several advantages over analog filters. Since software or programming code, which resides in the processor's memory, determines the operation of a digital filter, the filter is programmable and may be easily changed or redesigned without changes in the circuitry or hardware. Digital filters are also more stable than analog filters and do not generally suffer from time and temperature induced variations. A widely used type of digital filter is a finite impulse response filter
  • FIR filter Each output of a FIR filter is the sum of a finite number of weighted samples of the input sequence.
  • FIR filters are sometimes also referred to as feed-forward or non-recursive filters, since all paths lead forward from the input to the output. No part of the filter output is fed back to the filter input.
  • Digital FIR filters are applied in e.g. video encoders for filtering or scaling input video signals from sources such as computers into forms suitable for display on devices such as television monitors.
  • Prior art FIR filters comprise three basic building blocks: delay units, multipliers and adders.
  • the multiplier is the most complex and costly one to implement.
  • the operational speed of conventional implementation of multipliers is relatively slow and imposes a fundamental limit on the speed and through-put of the filter.
  • Conventional FIR filters may suffer from the drawback of using a large number of multipliers. It is an object of the present invention to provide an efficient digital filtering of a signal such as a word.
  • the above object may be solved by digitally filtering a first signal, wherein the first signal is a first linear combination of signals including at least a second signal and a third signal, the method comprising the steps of filtering the second signal, which results in a filtered second signal, filtering the third signal, which results in a filtered third signal, and adding the filtered third and second signals to each other, which results in a linear combination of filtered signals.
  • the method according to this exemplary embodiment of the present invention may lead to a reduction in calculation time needed for performing the digital filtering of a signal.
  • both the second signal and the third signal have a width of 1 -bit and the linear combination of filtered signals is buffered in an accumulator.
  • the method according to this exemplary embodiment of the present invention may lead to a digital filtering process of filtering a signal with a word width of 1-bit, which is faster than a digital filtering process of filtering a signal with e.g. an input word width of 20 bit.
  • a serial filtering process of an input signal which consists of a linear combination of a plurality of signals, each signal having a word width of 1-bit, may take much less calculation time than a process of parallel filtering a signal with an input word width of 20 bit.
  • the linear combination of signals includes a forth signal.
  • Digitally filtering of the fourth signal results in a filtered fourth signal.
  • a filtered signal may be understood as a signal which is weighted by a corresponding filter coefficient.
  • a filtered signal may as well be described as a signal, which has been weighted by a respective filter coefficient, or as a weighted signal.
  • the linear combination of filtered signals which is stored in the accumulator is multiplied by a factor k.
  • the factor k is one of 2 and l ⁇ , depending on the order of the incoming linearly combined signals. Since multiplications by 2 or Vi- may be done by left shifts or right shifts, no multiplier is needed.
  • the weighted or filtered fourth signal is added to the linear combination of filtered signals multiplied by the factor & buffered in the accumulator.
  • a linear combination of incoming 1-bit signals is serially filtered by one digital filter and each filtered 1-bit signal is added to an accumulator according to an N-bit two's complement adding scheme, which is described in more detail below.
  • An advantage of this exemplary embodiment of the present invention may be that only one adder and no multiplier is needed for performing the accumulation process (multiplication with 2 or Vz is done by shifting), which may save valuable system resources.
  • a filtering of a fifth signal is performed, resulting in a filtered fifth signal, wherein the fifth signal is part of a second linear combination of signals.
  • the filtered fourth signal is added to the filtered fifth signal before the sum of the filtered fourth signal and the filtered fifth signal is added to the linear combination of filtered signals multiplied by the factor k buffered in the accumulator.
  • an incoming signal which may comprise a linear combination of 2N 1-bit signals is segmented into two linear combinations of signals (a first one and a second one), each linear combination comprising N 1-bit signals. After that, both linear combinations are bit wise filtered and weighted. After that, each filtered and weighted 1-bit signal of the first linear combination of signals is added to the respective filtered and weighted 1-bit signal of the second linear combination of signals and then added to the accumulator.
  • the content of the accumulator is multiplied by a factor 2 or V according to an N-bit two's complement.
  • an incoming signal of a word width bigger than a predetermined number N may be segmented into different serial bit streams. Each of the serial bit streams are then bit wise filtered. This may lead to a reduction of multipliers and adders needed for performing the process of digital filtering.
  • the first signal comprises a linear combination of a first number of sixth signals. Furthermore, a filtering and adding of one signal of the first number of sixth signals defines a cycle.
  • the first number corresponds to the second number.
  • reinitialization of the accumulator may release system resources and prepare the filter for performing further filtering processes.
  • a multiplexer is configured such that, at the next cycle, no further accumulation is performed, but a reinitialization takes place by using the last filtered signal provided by the filter.
  • a constant component occurring in the linear combination of filtered signals is one of subtracted after the filtering and precompensated for during the reinitialization of the accumulator.
  • subtraction or precompensation of an unwanted constant component may alter the filtered signal in such a way, that further processing or readout of the filtered signal may be simplified.
  • the first number of sixth signals which form a linear combination, is set such that a product of the first number and a sampling rate is smaller or equal to a maximum bit rate.
  • the 1-bit filter may be adapted such that, if the first number is one, the scanning or filtering rate equals the maximum bit-rate. If the input word width or first number is greater than one, the resulting scanning rate or filtering rate is the maximum bit rate divided by the first number.
  • the filter is one of a hardware or software implemented FIR filter.
  • a digital filter is provided.
  • the digital filter comprises an input terminal for receiving an input signal, wherein the input signal is a linear combination of at least a second signal and a third signal, a filter for filtering the second signal and the third signal, an adder for adding the filtered third signal to the filtered second signal, resulting in a linear combination of filtered second and third signals, and an accumulator for storing the linear combination of filtered second and third signals.
  • the filter according to this exemplary embodiment of the present invention leads to a reduction of the area needed to implement the digital FIR filter, since the filter operations are serialized. Due to the serialization of the filter operation, no parallel implementation of filter elements, such as delay units, adders and multipliers is needed, resulting in a reduction of the overall filter area.
  • the spatial requirement of the additional accumulator may be considered to be small, compared to the spatial requirement of the multipliers.
  • a filter used for filtering a signal with a width of 1 -bit is smaller than a filter used for filtering a signal with e.g. an input word width of 20 bit. Therefore, a serial filtering of an input signal which consists of a linear combination of a plurality of signals, each signal having a word width of 1-bit, needs much less spatial area than a filter used for parallel filtering a signal with an input word width of 20 bit, since in the 1-bit case no area consuming multipliers are needed.
  • a software program product for execution on a processor of a computer for performing a method of digital filtering a first signal, wherein the first signal is a linear combination of signals including at least a second signal and a third signal, the method comprising the steps of filtering the second signal, resulting in a filtered second signal, filtering the third signal, resulting in a filtered third signal, and adding the filtered third and second signals to each other, resulting in a linear combination of filtered signals.
  • the software program product according to this exemplary embodiment of the present invention may reside in the processor's memory and may determine the operation of a digital filter.
  • the filter may be programmable and may be easily changed or redesigned without changes in the circuitry or hardware.
  • the software program product may lead to a reduction in calculation time needed for performing the digital filtering of a signal. This is due to the fact that, particularly in the case of a 2-bit quantization of the I & Q signals, fewer processor cycles for digital filtering of a signal are needed than by prior art methods based on "multiply and accumulate" operations.
  • an incoming signal is interpreted as a linear combination of N signals u(n), wherein each of the N signals u(n) has a width of 1-bit and is filtered with a 1-bit filter and that after filtering the N signals u(n), the linear combination of the N filtered signals u(n) is carried out. Due to this, the number of multipliers needed is effectively reduced, which, in case of a hardware implementation of the digital FIR filter may lead to a reduction of the area needed for the digital filter, and in the case of a software implementation, the calculation time needed for the filtering process is reduced.
  • Fig. 1 shows a block diagram of a digital filter structure.
  • Fig. 2 shows a block diagram of a digital filter structure according to an exemplary embodiment of the present invention.
  • the block diagram of a digital filter structure such as an FIR filter depicted in Fig. 1 explains the layout of a prior art digital filter and the method which may be used for the digital filtering of data.
  • the FIR filter depicted in Fig. 1 comprises three basic building blocks, namely delay units 2, 3, multipliers 4, 5, 6 and adders 7, 8.
  • Data, which is input into the FIR filter passes a serial interface 1, which converts the incoming multi-bit signal or sequence of signals into a plurality of parallel 1-bit signals. After the serial / parallel conversion of the incoming signal, the converted signals are advanced through delay units 2, 3, which typically impose a delay of one clock cycle each.
  • the delay unit 2 when the input signal coming from the serial/parallel converter is u(n), the delay unit 2 outputs the previous input signal u(n-l) and the delay unit 3 outputs the second previous input signal u(n-2).
  • the delay units 2, 3 are realized in the form of a hardware implementation, the input signals u(n-l), u(n-2) are stored in a memory of the respective delay unit 2, 3 for one clock cycle and then released to the respective output of the delay unit 2, 3.
  • the input signal u(n) and the delayed signals u(n-l), u(n-2) are tapped by respective tap units 9, 10, 11, transmitted to multipliers 4, 5, 6, respectively, and multiplied by filter coefficients ⁇ (n), ⁇ (n-l), ⁇ (n-2), respectively.
  • the digital filter structure depicted in Fig. 1 comprises a so-called tap for each input signal u(n), u(n-l) and u(n-2).
  • An FIR filter comprises the same number of taps as input signals u(n), u(n-l), u(n-2). Therefore, the filter structure depicted in Fig. 1 is said to be a 3-tap filter.
  • the multiplied or weighted signals, which are output from multipliers 4, 5, 6, are added together by adders 7, 8.
  • each output signal may be described as the current weighted input signal added to a linear combination of previously weighted input signals.
  • Fig. 2 shows a block diagram of a digital filter according to an exemplary embodiment of the present invention.
  • the filter structure depicted in Fig. 2 is a form of serialization, which may be advantageous if the word width N of the signals fed into the filter may be configured, such that the product of word width and scanning rate f a is constant or almost constant.
  • the bit stream has to be periodical, each period comprising a certain combination of N I-bits, N Q-bits and N f filling bits.
  • the producer of the RF IC has the freedom to choose the number N of I-bits and Q-bits, such that 1 ⁇ N ⁇ 20, and to set the scanning rate f a corresponding to N.
  • the second fact is the so-called linearity of the filtering process.
  • the first fact that filter structures for 1-bit quantized input signals need less area than filter structures for input signals of a word width of more than 1-bit, may be explained by considering that the weighting of a tapped 1-bit signal is rather simple:
  • the logic 0 and 1 usually represent the signal values 0 and 1, respectively, or the signal values -1 and 1, respectively.
  • the weighting of a tapped signal is performed by passing the respective coefficient or setting the respective coefficient to 0 in the first case and passing the respective coefficient or changing the sign of the respective coefficient in the second case. Therefore, the filter only needs a number of adders to add all weighted tapped signals, but no area consuming multipliers.
  • N denotes the number of taps of the FIR filter
  • equation 2 N denotes the number of linear combinations
  • equation 1 n denotes the sample count, wherein in equation 2 n denotes the count of linear combinations.
  • Linearity is an elementary mathematical property of filters.
  • _4 0 (equation 2)
  • ct k are constants and x ® h symbolizes the convolution of the input signal x (such as a word) with the impulse response h of the filter, x ® h
  • the linear property of the filtering may be described as follows: the filtering of a linear combination of signals has the same result as the linear combination of the filtered signals.
  • the input signal is interpreted as a linear combination of N signals U k -
  • the 1-bit signals U k are filtered with a suitable filter and the linear combination of the filtered signals is carried out.
  • the filter structure depicted in Fig. 2 comprises three basic building blocks, namely delay units 22, 23, 30, multipliers 24, 25, 26, 31 and adders 27, 28, 29, 33. It should be noted that no real multipliers are needed, since an input signal is only 1-bit wide.
  • the incoming bit stream signal passes a serial interface 37 and is put directly into the delay units 22, 23 of the filter, resulting in a segmentation of the incoming bit stream signal into two smaller bit streams comprising N input signals each.
  • the FIR filter does not comprise a tap for each input signal U k , but a first tap 34 positioned before multiplier 24, a second tap 35 positioned after N delay units 22 and before multiplier 25 and a third tap 36 positioned after N delay units 23 and before multiplier 26. Therefore, at any time, only the tap values of one of the N signals U k may be seen at the respective tap. These two tap values are weighted with their respective filter coefficients and added in adders 27 and 28. After that, the resulting signal is added to an accumulator, the accumulator comprising adder 29, delay unit 30 and multiplier 31.
  • the linear combination of filtered signals stored in the accumulator 29, 30, 31 is multiplied by a factor k, wherein the factor k is one of 2 and one half ⁇ ). If the serial interface 37 at the input of the filter structure provides the filter with a series or linear combination of N 1-bit signals u ⁇ such that the 1-bit signal which has the highest bit value is provided to the filter first, the factor k has the value 2. If the serial interface 37 delivers the lowest bit first, the factor k has the value V*.
  • y 1 ((... + y4) * 0.5 + y3) * 0.5 + y2.
  • signals uu in the two's complement representation may take the values 0 or 1, which are represented by the logical levels 0 and 1.
  • the logical levels 0 and 1 of a bit stream produced, for example, by an 1-bit Sigma-Delta modulator may represent the signal values -1 and 1. Since a selected filter implementation may not be able to comply with the requirements of both signal representations, a constant component may evolve at the filter output after adder 28. If this constant component is unwanted, it may be subtracted after the filtering or precompensated for during initialization of the accumulator 29, 30, 31.
  • the present invention has several advantages:
  • the method according to the present invention may also be implemented in a correlation filter from the software side.
  • the multi-bit input signal is divided into partial bit streams. These partial bit streams are correlated separately and the correlation results are weighted according to their sequential order or value.
  • the software implementation of a FIR filter or filter structure needs less processor cycles for digital filtering of a signal than prior art methods based on "multiply and accumulate" operations.
  • the method according to an exemplary embodiment of the present : invention may be implemented in a configurable hardware decimization filter for I & Q base band signals.
  • the filters are part of the receiver of a GSM base band IC and are used for performing a post processing of digitalized I & Q signals, which are transmitted by a GSM radio IC.
  • the two ICs are connected by a serial digital interface, which is adapted to correspond to the "DigRF" standard. This standard is used for providing compatibility between different IC components of different distributors or producers.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

Les réalisations matérielles des multiplicateurs dans les filtres numériques occupent des surfaces importantes. Par ailleurs, l'exécution d'opérations de type « multiplier et accumuler » du côté logiciel d'un filtre numérique de l'état de la technique implique une durée de calcul importante. La segmentation du flux binaire d'un signal d'entrée selon des combinaisons linéaires d'un nombre déterminé de signaux permet un filtrage numérique efficace. Selon un aspect de la présente invention, ce procédé peut être mis en oeuvre du côté matériel d'un filtre numérique de manière à obtenir une réduction de la surface nécessaire à la mise en oeuvre du filtre numérique, ou alors du côté logiciel d'un filtre numérique de manière à obtenir une réduction de la durée de calcul nécessaire à la réalisation du processus de filtrage.
PCT/IB2004/052102 2003-10-24 2004-10-15 Filtrage numerique WO2005041407A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03103943.1 2003-10-24
EP03103943 2003-10-24

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WO2005041407A1 true WO2005041407A1 (fr) 2005-05-06

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3732409A (en) * 1972-03-20 1973-05-08 Nasa Counting digital filters
US4862402A (en) * 1986-07-24 1989-08-29 North American Philips Corporation Fast multiplierless architecture for general purpose VLSI FIR digital filters with minimized hardware
US4868773A (en) * 1985-03-15 1989-09-19 Purdue Research Foundation Digital filtering by threshold decomposition
EP0608665A1 (fr) * 1993-01-29 1994-08-03 STMicroelectronics S.r.l. Méthode de filtrage des signaux numériques à haute résolution et architecture correspondante de filtre numérique

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3732409A (en) * 1972-03-20 1973-05-08 Nasa Counting digital filters
US4868773A (en) * 1985-03-15 1989-09-19 Purdue Research Foundation Digital filtering by threshold decomposition
US4862402A (en) * 1986-07-24 1989-08-29 North American Philips Corporation Fast multiplierless architecture for general purpose VLSI FIR digital filters with minimized hardware
EP0608665A1 (fr) * 1993-01-29 1994-08-03 STMicroelectronics S.r.l. Méthode de filtrage des signaux numériques à haute résolution et architecture correspondante de filtre numérique

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
A. J. GREENBERGER: "Digital Transversal Filter Architecture", ELECTRONICS LETTERS, vol. 21, no. 3, 31 January 1985 (1985-01-31), UK, pages 86 - 88, XP009043825 *
WOODWARD M E ET AL: "A MODULAR APPROACH TO THE HARDWARE IMPLEMENTATION OF DIGITAL FILTERS", RADIO AND ELECTRONIC ENGINEER, INSTITUTION OF ELECTRONIC AND RADIO ENGINEERS. LONDON, GB, vol. 46, no. 8/9, August 1976 (1976-08-01), pages 393 - 400, XP000760556, ISSN: 0033-7722 *

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