WO2005031973A3 - Cmos-schaltkreis-anordnung - Google Patents

Cmos-schaltkreis-anordnung Download PDF

Info

Publication number
WO2005031973A3
WO2005031973A3 PCT/DE2004/002079 DE2004002079W WO2005031973A3 WO 2005031973 A3 WO2005031973 A3 WO 2005031973A3 DE 2004002079 W DE2004002079 W DE 2004002079W WO 2005031973 A3 WO2005031973 A3 WO 2005031973A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit system
cmos circuit
outlet
operating potential
circuit breaker
Prior art date
Application number
PCT/DE2004/002079
Other languages
English (en)
French (fr)
Other versions
WO2005031973A2 (de
Inventor
Joerg Berthold
Ralf Brederlow
Christian Pacha
Arnim Klaus Von
Original Assignee
Infineon Technologies Ag
Joerg Berthold
Ralf Brederlow
Christian Pacha
Arnim Klaus Von
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10348018A external-priority patent/DE10348018B4/de
Application filed by Infineon Technologies Ag, Joerg Berthold, Ralf Brederlow, Christian Pacha, Arnim Klaus Von filed Critical Infineon Technologies Ag
Priority to US10/573,362 priority Critical patent/US7342421B2/en
Publication of WO2005031973A2 publication Critical patent/WO2005031973A2/de
Publication of WO2005031973A3 publication Critical patent/WO2005031973A3/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electric Clocks (AREA)

Abstract

Zwischen den Ausgang eines NMOS-Logikschaltkreis ist ein Takt-Transistor und ein zweites Betriebspotential geschaltet, welcher als Leistungsschalter fungiert.
PCT/DE2004/002079 2003-09-24 2004-09-17 Cmos-schaltkreis-anordnung WO2005031973A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/573,362 US7342421B2 (en) 2003-09-24 2004-09-17 CMOS circuit arrangement

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10344374 2003-09-24
DE10344374.6 2003-09-24
DE10348018.8 2003-10-15
DE10348018A DE10348018B4 (de) 2003-09-24 2003-10-15 CMOS-Schaltkreis-Anordnung

Publications (2)

Publication Number Publication Date
WO2005031973A2 WO2005031973A2 (de) 2005-04-07
WO2005031973A3 true WO2005031973A3 (de) 2005-06-16

Family

ID=34395044

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2004/002079 WO2005031973A2 (de) 2003-09-24 2004-09-17 Cmos-schaltkreis-anordnung

Country Status (2)

Country Link
US (1) US7342421B2 (de)
WO (1) WO2005031973A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7705625B2 (en) 2005-07-08 2010-04-27 Zmos Technology, Inc. Source transistor configurations and control methods
US7516425B2 (en) * 2005-12-22 2009-04-07 Industrial Technology Research Institute Method for generating minimal leakage current input vector using heuristics
US7545177B1 (en) * 2007-03-20 2009-06-09 Xilinx, Inc. Method and apparatus for leakage current reduction
US8598027B2 (en) 2010-01-20 2013-12-03 International Business Machines Corporation High-K transistors with low threshold voltage
US10318681B1 (en) * 2017-06-28 2019-06-11 Xilinx, Inc. Static leakage current and power estimation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247212A (en) * 1991-01-31 1993-09-21 Thunderbird Technologies, Inc. Complementary logic input parallel (clip) logic circuit family

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247121A (en) * 1989-05-23 1993-09-21 L'oreal Alkyl esters of n-carboalkyloxy amino-11-undecanoic acids, their processes of preparation and their use as thickening agents
US5841300A (en) * 1994-04-18 1998-11-24 Hitachi, Ltd. Semiconductor integrated circuit apparatus
US5612638A (en) * 1994-08-17 1997-03-18 Microunity Systems Engineering, Inc. Time multiplexed ratioed logic
DE69739692D1 (de) * 1996-04-08 2010-01-21 Hitachi Ltd Integrierte halbleiterschaltungsvorrichtung
US20020000872A1 (en) * 1998-09-11 2002-01-03 Yibin Ye Method and apparatus for reducing standby leakage current using a leakage control transistor that receives boosted gate drive during an active mode
KR100352767B1 (ko) * 2000-07-19 2002-09-16 삼성전자 주식회사 고속 반도체 디바이스에 적합한 인터페이스 회로 및인터페이싱 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247212A (en) * 1991-01-31 1993-09-21 Thunderbird Technologies, Inc. Complementary logic input parallel (clip) logic circuit family

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
GEROUSIS V ED - INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS: "Design and modeling charenges for 90 NM and 50 NM", PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE. (CICC 2003). SAN JOSE, CA, SEPT. 21 - 24, 2003, IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE.CICC, NEW YORK, NY : IEEE, US, vol. CONF. 25, 21 September 2003 (2003-09-21), pages 353 - 360, XP010671232, ISBN: 0-7803-7842-3 *

Also Published As

Publication number Publication date
US20070085567A1 (en) 2007-04-19
WO2005031973A2 (de) 2005-04-07
US7342421B2 (en) 2008-03-11

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