WO2005027386A1

WO2005027386A1 - Digital data transmission device

Info

Publication number: WO2005027386A1
Application number: PCT/JP2004/012969
Authority: WO
Inventors: Yuji Kasai; Masahiro Murakawa; Tetsuya Higuchi
Original assignee: Japan Industrial Technology Association
Priority date: 2003-09-10
Filing date: 2004-09-07
Publication date: 2005-03-24
Also published as: JPWO2005027386A1; TWI274498B; TW200514398A; JP4296327B2

Abstract

Transmission data is converted into an analog signal appropriate for transmission in the OFDM method by a transmission circuit (10) and outputted via an amplifier (11) to a cable (21) by a hybrid circuit (12). A cancel signal generation circuit (17) generates a cancel signal for erasing an unnecessary signal according to the transmission data. The reception signal from the cable (21) is separated from the transmission signal by the hybrid circuit (12) and deterioration of a waveform caused by frequency characteristic by the cable (21) is compensated by a compensation circuit (13). In a reception circuit (15), the output signal of the compensation circuit (13) is subjected to OFDM demodulation and converted into a digital signal after correcting distortion and echo. The digital signal is subjected to parallel-series conversion and evaluation signal generation processing all at once so as to obtain reception data and an evaluation signal. An adjustment control circuit (18) has a built-in CPU and adjusts each circuit so as to transmit/receive data correctly according to the evaluation signal.

Description

Specification

Digital data transmission equipment

Technical field

The present invention relates to a device for transmitting digital data using a signal cable. In particular, the present invention relates to a transmission device suitable for high-speed data transmission of 1 gigabit per second or more.

Background art

[0002] In general, when digital data is transmitted using a signal cable and bidirectional communication is performed, a hybrid circuit is used. In this hybrid circuit, a transmission signal and a reception signal are separated by a high-frequency transformer. In Ethernet, twisted-pair twisted-pair cables are widely used as cables for transmission.At high frequencies of 500 MHz or more, the attenuation of the cables is extremely large, and the frequency band of signals that can be used for transmission is limited. Therefore, the technique of multi-level pulse amplitude modulation (PAM) has been used. Further, since the waveform is significantly degraded by transmitting a signal through a cable, digital signal processing (DSP) technology has conventionally been used to obtain accurate received data.

[0003] In the conventional digital data transmission apparatus as described above, the communication speed is set to one communication channel as represented by, for example, a 1000 Mbit Ethernet technology as shown in Non-Patent Document 1 below. At 250 megabits per second was the highest, and high-speed data transmission of 1 gigabit per second or more per communication channel was not possible.

[0004] In the OFDM (orthogonal frequency division multiplexing) transmission method used for wireless digital communication, digital signal processing (DSP) technology is used for signal modulation and demodulation. The fast Fourier transform and the fast Fourier inverse transform were performed by performing butterfly operation.

Non-patent document 1: IEEE802.3ab specification http: 〃 grouper.ieee.org/groups/802/3/ab/ Disclosure of the invention

Problems the invention is trying to solve [0005] In the conventional digital data transmission apparatus as described above, high-speed data transmission of 1 gigabit per second or more per communication channel was impossible due to the following problems.

In other words, it is extremely difficult to separate signals with a high-frequency transformer at the frequency of signals used for high-speed communication, and analog-digital converters (AZD converters) and digital processing circuits used for digital signal processing (DSP) operate at high speeds. There was a problem in that it would not be practical in terms of circuit size, power consumption, and cost!

[0006] Further, in pulse amplitude modulation, the influence of noise increases due to multi-level modulation, and further improvement in communication speed has been extremely difficult due to the limited transmission band of the cable. Also, in the OFDM transmission method, it was extremely difficult to handle data with a communication speed of several tens of megabits per second or more due to the restriction on the processing speed of the DSP.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art and to provide a high-speed data transmission device of 1 gigabit per second or more per communication channel.

Means for solving the problem

[0007] The digital data transmission device of the present invention includes: a transmission unit including an OFDM modulation circuit; a reception unit including an evaluation signal generation unit configured to generate an adjustment state evaluation signal from the OFDM demodulation circuit and the received signal; The main feature is that there is provided adjusting means for adjusting the receiving means or the transmitting means of the partner device using the evaluation signal. In the digital data transmission device described above, a hybrid circuit capable of adjusting the balance by a resistance matrix circuit may be further provided, and the adjusting unit may adjust the hybrid circuit.

Further, in the digital data transmission apparatus described above, the evaluation signal generating means determines whether the received signal is biased near a force boundary located near the center of each of the multi-valued determination level ranges, and determines the frequency as a histogram. It may output information. Further, in the digital data transmission device described above, the adjusting means may adjust the circuit using a genetic algorithm!

In the digital data transmission device described above, the receiving means may further include an adjustable echo cancel circuit. In addition, the digital data transmission described above In the apparatus, the receiving means may further include a compensating circuit that is adjustable and that performs analog processing on the received signal to compensate for frequency characteristics of the cable. Further, in the above digital data transmission apparatus, the receiving means may further include an adjustable distortion removing circuit for performing analog processing on the received signal.

Further, in the digital data transmission device described above, the transmitting unit transmits a pilot signal based on a clock signal, and the receiving unit includes a clock recovery circuit that extracts a pilot signal from the received signal and generates a clock signal. You may. In the above digital data transmission apparatus, the transmitting means further includes code modulation means for code modulating data to be transmitted, and the receiving means further includes code inverse modulation means for performing code inverse modulation on the received data. With /!

The invention's effect

[0008] By adopting the OFDM system, a digital data transmission device capable of transmitting a total of 10 Gbps in full duplex using four twisted pairs has been realized. Further, in the hybrid circuit of the present invention, the transmission signal is not canceled by the high-frequency transformer, but is divided into two systems by the resistance matrix circuit RM, and the two systems are balanced by the amplifiers 58 and 59. By combining the signals, the transmitted signal was canceled and the received signal could be extracted efficiently.

Brief Description of Drawings

FIG. 1 is a block diagram showing a configuration of a full-duplex transmission / reception circuit of the present invention.

FIG. 2 is a block diagram showing the configuration of the entire transmission device of the present invention.

FIG. 3 is a block diagram showing a configuration of a transmission circuit 10 of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a hybrid circuit 12 of the present invention.

FIG. 5 is a block diagram showing a configuration of a modulation circuit 32 of the present invention.

FIG. 6 is a block diagram showing a configuration of a compensation circuit 13 of the present invention.

FIG. 7 is a waveform diagram showing an example of a waveform of a signal modulated by OFDM by the modulation circuit 10 of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a cancel signal generation circuit according to the present invention.

FIG. 9 is a block diagram showing a configuration of a receiving circuit 15 of the present invention. FIG. 10 is a block diagram showing a configuration of a demodulation circuit 90 of the present invention.

FIG. 11 is a block diagram showing a configuration of an interference distortion correction circuit 91 of the present invention.

FIG. 12 is a block diagram showing a configuration of a warp signal elimination circuit of the present invention.

FIG. 13 is a block diagram showing a configuration of a clock recovery circuit of the present invention.

FIG. 14 is a flowchart showing the contents of the adjustment processing of the present invention.

FIG. 15 is a block diagram showing a detailed configuration of a receiving circuit of the present invention.

FIG. 16 is a block diagram illustrating a configuration of a transmission circuit according to a second embodiment of the present invention.

FIG. 17 is a block diagram showing a configuration of a receiving circuit according to a second embodiment of the present invention.

FIG. 18 is a circuit diagram and a waveform diagram showing a configuration of an integration circuit 108 of the present invention.

Explanation of symbols

[0010] 10 Transmitter circuit

11 Amplifier

12 Hybrid circuit

21 Cable

22 Remote device

13 Compensation circuit

17 Cancel signal generation circuit

15 Receiver circuit

16 clock recovery circuit

18 Adjustment control circuit

BEST MODE FOR CARRYING OUT THE INVENTION

[0011] A digital data transmission device capable of transmitting a total of 10 Gbps in full duplex by the OFDM method using a conventional LAN cable composed of four twisted pairs will be described below.

Example 1

Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 is a block diagram showing a configuration of a full-duplex transmission / reception circuit 20 of the present invention. FIG. 2 is a block diagram showing a configuration of the entire transmission device of the present invention. This device mainly handles digital data handled by computers. It communicates with such a computer, an external device, a network, or the like.

The transmission device of the present invention is connected to a partner transmission device 22 having the same configuration by a cable 21. In the present invention, the cable 21 is widely used for the Internet, and a twisted pair wire can be used. In this case, it is effective if the already laid cable is available and excellent economic efficiency is obtained.

The transmission device includes four full-duplex transmission / reception circuits 20, a data distribution circuit 23, and a data synthesis circuit 24. The data distribution circuit 23 divides, for example, transmission data into 8 bits, and distributes 2 bits to each of the four full duplex transmission / reception circuits 20. Further, the data synthesizing circuit 24 restores each 2-bit data of the four channels to the original 8-bit data. The data may be distributed to the full-duplex transmission / reception circuit 20 with more than 2 bits as needed, so that error detection and Z correction can be performed.

Hereinafter, the configuration of the full duplex transmission / reception circuit 20 will be described. The transmission data is converted into an analog signal suitable for transmission by the OFDM system by the transmission circuit 10, amplified to a size suitable for transmission by the amplifier 11, and output to the cable 21 by the hybrid circuit 12. A part of the transmission signal generates an unnecessary signal called “echo” due to reflection at a connection point or the like existing in the cable 21. For accurate data transmission, it is necessary to appropriately remove this unnecessary signal. The cancel signal generation circuit 17 generates a cancel signal for erasing an unnecessary signal based on the transmission data.

The reception signal from the cable 21 is separated from the transmission signal by the hybrid circuit 12 and connected to the compensation circuit 13. The compensation circuit 13 compensates for the deterioration of the waveform due to the frequency characteristics of the cable 21 by a method described later.

In the receiving circuit 15, although the details will be described later, the output signal power of the compensating circuit 13 is OFDM demodulated, distortion and echo are corrected by an interference distortion correcting circuit, and the digital signal is converted by an analog-to-digital converter. The digital signal is subjected to parallel-to-serial conversion and evaluation signal generation processing collectively to obtain received data and an evaluation signal described later.

[0015] Regarding the timing of the above-described series of reception operations, a clock signal is extracted by the clock recovery circuit 16, and various timing signals are generated. Adjustment control circuit 18 has a built-in CPU Although details will be described later, each circuit is adjusted so that data can be correctly transmitted and received based on the evaluation signal.

Note that the transmission line 21 may be used as a unidirectional transmission line instead of full-duplex.In this case, the output of the amplifier 11 is directly connected to the transmission cable 21 and the reception cable 21 is compensated. Connected to circuit 13. Also, the hybrid circuit 12 and the cancel signal generation circuit 17 are not required.

FIG. 3 is a block diagram showing a configuration of the transmission circuit 10 of the present invention. The transmission data is converted (distributed) into a plurality of data by the serial / parallel converter 30. The higher the frequency of the cable, the greater the attenuation, so the OFDM assigns more bits to OFDM, lower frequencies, and modulated carriers.

For example, when eight modulation carriers are used from 50 MHz to 400 MHz at intervals of 50 MHz, the number of bits allocated to each carrier is 6 × 2, 5 × 2, 4 × 2, 3 × 2, 3X2, 2X2, 2X2, IX 2 bits. Note that the reason for this is that X 2 !! is used because two carriers orthogonal to one frequency are PAM-modulated and transmitted independently.

The output of the serial / parallel converter 30 is converted into a plurality of multi-value analog signals by a digital / analog converter (DZA converter) 31. The plurality of multi-valued analog signals are converted by a modulation circuit 32 into analog signals modulated by OFDM (Orthogonal Frequency Division Multiplexing). If necessary, the amplitude (current value) of the DZA converter 31 may be adjusted by the adjustment control circuit 18 so as to be optimized by a genetic algorithm.

FIG. 5 is a block diagram showing a configuration of the modulation circuit 32 of the present invention. The carrier signal generation circuit 64 generates carrier signals of a plurality of OFDM frequencies based on the clock signal 62. The carrier signal generation circuit 64 generates the timing of the OFDM carrier signal using a phase locked loop (PLL) circuit and a digital frequency divider. Since this output has insufficient orthogonality due to harmonic components as it is, it is converted into a sine wave signal by the filter circuit 66 and is amplified to an amplitude suitable for driving the multiplier 67.

[0020] LO-1-1 is the lowest (first) carrier signal of OFDM, LO-1-Q is a carrier signal having the same frequency as LO-1-1 and a phase difference of 90 °, 2-1 is the second carrier signal of OFDM LO-2-Q is the carrier signal with the same frequency and a phase difference of 90 ° as LO-2-I, and LO-3-I is the third carrier signal in OFDM. Let n be the number of OFDM carrier signals. Similarly, the n-th carrier signal is LO-nI and LO-nQ, and the phase difference is 90 °. PL is a pilot signal and plays a role of a synchronization signal in the OFDM transmission method of the transmission device 1 of the present invention.

[0021] Using each of the 2n carrier signal frequencies LO-1-I—LO-n-Q obtained here, the multiplier 67 analogically multiplies the input signal 61 corresponding to the carrier signal by the multiplier 67. do. This output is amplified to an appropriate magnitude for each frequency by an amplifier 68, and is combined into one signal by a signal combiner 69. As the multiplier 67, for example, a Gilbert cell multiplier is employed.

Here, the input signal 61 is a multi-valued analog signal in which a plurality of bits of digital data are also generated by the DZA conversion 31. As described above, the above-described bit is used for each frequency of the OFDM carrier signal. It is possible to change the number. As a result, in accordance with the frequency characteristics of the cable 21, the number of bits is increased at frequencies with good characteristics, and the number of bits is decreased at frequencies that are not otherwise good. ) Can be increased.

The carrier signal generation circuit 64 generates a pilot signal PL synchronized with a time reference of a plurality of OFDM carrier signals. The frequency of the pilot signal PL is selected so as to have little overlap with the spectrum of the OFDM signal. For example, 1Z4 frequency of LO-1-I.

The amplification factor of the amplifier 68 may be optimized by a genetic algorithm by the adjustment control circuit 18 if necessary for each frequency of the OFDM carrier signal.

FIG. 7 is a waveform diagram showing an example of a waveform of a signal modulated by OFDM by the modulation circuit 10 of the present invention. Here, the number n of carrier signals is 16, and the number of frequencies of carrier signals is 8.

FIG. 4 is a circuit diagram showing a configuration of the hybrid circuit 12 of the present invention. The connector 35 connected to the cable 21 described above is connected to a resistance matrix circuit RM including resistors 43 to 55, and the resistance matrix circuit RM is connected to high-frequency transformers 41, 56, and 57. Resistance 47 The resistance value is set equal to the characteristic impedance of the cable 21 connected to the connector 35.

[0027] The output of the amplifier 11 is connected to the primary side of the high-frequency transformer 41. The transmission signal is amplified by the amplifier 11 and output to the high-frequency transformer 41. One end of the secondary side of the high-frequency transformer 41 is connected to the connector 35 and the resistor 48 through the resistor 43, and to the resistor 47 and the resistor 50 through the resistor 45. The other end of the high frequency transformer 41 on the secondary side is connected to the connector 35 and the resistor 51 through the resistor 44, and to the resistors 47 and 53 through the resistor 46.

[0028] The connection point Nl is the connection point between the connector 35, the resistance 43 and the resistance 48, the connection point N2 is the connection point between the connector 35, the resistance 44 and the resistance 51, and the connection point is the connection point N2 between the resistance 47, the resistance 45 and the resistance 50. The connection point between N3 and the resistance 47, the resistance 46, and the resistance 53 is referred to as a connection point N4. The transmission signal is output from the connection point N4 to the connection point N1 in the same phase (voltage of the same polarity), and is output from the connection point N2 to the connection point N3 in the opposite phase (voltage of the opposite polarity).

[0029] The resistor 48 and the resistor 53 are connected to the primary side of the high-frequency transformer 56, and are connected to the connection point N1 and the connection point N4, respectively. The resistor 50 and the resistor 51 are connected to the primary side of the high-frequency transformer 57, and are connected to the connection point N3 and the connection point N2, respectively. Therefore, on the secondary side of the high-frequency transformer 56 and the high-frequency transformer 57, the components of the transmission signal occur in opposite phases.

Regarding the reception signal, the reception signal from the connector 35 is connected to the primary side of the high-frequency transformer 56 via the resistor 48 and the resistors 51 and 52, and the high-frequency transformer is connected via the resistors 48, 49 and the resistor 51. Connect to primary side of 57. Therefore, on the secondary side of the high frequency transformer 56 and the high frequency transformer 57, the components of the received signal are generated in the same phase (voltage of the same polarity).

[0031] The secondary sides of the high-frequency transformer 56 and the high-frequency transformer 57 are connected to an amplifier 58 and an amplifier 59, respectively, and the outputs of the amplifier 58 and the amplifier 59 are added and synthesized to obtain a received signal. At this time, since the components of the transmission signal are combined in opposite phases, the reception signal and the transmission signal are separated. The resistors 42, 54, and 55 are used for impedance matching.

[0032] Due to a difference between the characteristic impedance of the cable 21 and the resistance value of the resistor 47, the magnitudes of the components of the out-phase transmission signal at the outputs of the amplifiers 58 and 59 do not always match. Therefore, it is possible to remove the components of the transmission signal by changing the amplification factors of the amplifiers 58 and 59. It is preferable that the amplification factor be optimized by the adjustment algorithm by the genetic algorithm. As described above, the hybrid circuit 12 of the present invention has two signal paths of the amplifier 58 and the amplifier 59, and has a great feature of adjusting the balance between the signal outputs of the two signal paths.

FIG. 8 is a block diagram showing a configuration of the cancel signal generation circuit of the present invention. The transmission data is input to the shift registers 80 connected in multiple stages, and the history of the transmission data is temporarily recorded sequentially in the shift registers. The output of the shift register 80 is input to the selector 81, and a part of the transmission data history is selected by the selector 81. The output of the selector 81 is converted into an analog current value by the DZA converter 82, and a cancel signal is generated. The output (tap position) of the selector 81 and the output (polarity and amplitude) of the DZA converter 82 are optimized by the adjustment control circuit 18 by a genetic algorithm.

FIG. 6 is a block diagram showing a configuration of the compensation circuit 13 of the present invention. The input signal 71 input to the compensation circuit 13 is amplified to an appropriate size by the amplifier 72 and distributed to the same two signals by the distributor 73. One of the divided signals is delayed by a predetermined time in a delay line 74 and input to an amplifier 76. Another distributed signal is input to the amplifier 75 without delay.

After each signal is amplified by amplifiers 75 and 76, it is input to combiner 77 in opposite phase. That is, the synthesizer 77 calculates the difference between the two signals in an analog manner. The output of the synthesizer 77 is appropriately amplified by the amplifier 78 and output as the output signal 79 of the compensation circuit 13.

Here, by optimizing the ratio between the amplification factors of the amplifiers 75 and 76 and the delay amount of the delay line 74, it is possible to obtain frequency characteristics that compensate for the frequency characteristics of the cable 21. By configuring the amplifiers 75 and 76 such that one or both of the amplification factors are variable, it is possible to provide stable transmission even when the cable 21 is changed.

FIG. 9 is a block diagram showing a configuration of the receiving circuit 15 of the present invention. The output signal of the compensation circuit 13 is demodulated by the demodulation circuit 90 into a plurality of multi-level analog signals. From the output signal of the demodulation circuit 90, a multi-noise signal component (warp signal) due to imperfect frequency orthogonality and the use of the cable 21 bundled together is removed by an interference distortion correction circuit 91. In the interference distortion correction circuit 91, an analog product-sum operation is performed. [0038] In the interference distortion correction circuit 91, the output signal of the demodulation circuit 90 and the cancellation signal output from the cancellation signal generation circuit 17 are combined, and unnecessary signals are removed. The output of the interference distortion correction circuit 91 is converted into a digital signal by analog-to-digital conversion. If the received waveform has little distortion, it is possible to omit the interference distortion correction circuit 91 and connect the output of the demodulation circuit 90 to the input of the analog-to-digital converter 92.

The digital signals output from the analog-to-digital converter 92 are collectively subjected to processing such as parallel-to-serial conversion by a parallel-to-serial converter 93, thereby obtaining received data and generating an evaluation signal by an evaluation measurement circuit 94. Is done.

FIG. 10 is a block diagram showing a configuration of the demodulation circuit 90 of the present invention. The clock signal 102 input to the demodulation circuit 90 is supplied from a clock recovery circuit 16 described later. Carrier signal generation circuit 110 generates a plurality of OFDM carrier signals based on a clock signal. The filter circuit 112 outputs a sine wave by removing harmonic components of the carrier signal.

LO-1-1 is the lowest (first) carrier signal of OFDM, LO-1-Q is a carrier signal having the same frequency as LO-1-1 and a phase difference of 90 °, 2-1 is the second carrier signal of OFDM, LO-2-Q is the carrier signal with the same frequency as LO-2-I and the phase difference is 90 °, LO-3-I is the third carrier of OFDM Signal. Let n be the number of OFDM carrier signals. Similarly, the n-th carrier signal is LO-n-I and LO-n-Q, and the phase difference is 90 °.

[0042] The carrier signal generation circuit 110 and the filter circuit 112 can be shared with the modulation circuit 32 when the time reference of the transmission signal and the reception signal in the transmission device match. In this case, one of the transmission devices at both ends generates a clock signal, and the other operates using the clock signal of the other end.

The input signal 101 is amplified by the amplifier 104 to an appropriate size, and further amplified by the amplifier 105 to a size corresponding to the carrier signal. The amplification factor of the amplifier 105 is optimized by the adjustment control circuit 18 using a genetic algorithm. The signal 106 output from the amplifier 105 is input to the multiplier 107. Multiplier 107 performs analog multiplication with signal 106 corresponding to each carrier signal using each of carrier signals LO-1-I—LO-nQ. This output is integrated for a certain period of time for each frequency by the integration circuit 108, and unnecessary frequency components are removed. And, to the appropriate size by the amplifier 109 It is amplified and the output 103 of the demodulator 11 is obtained.

FIG. 18 is a circuit diagram and a waveform diagram showing a configuration of integration circuit 108. Each switch in the circuit also becomes the analog switch circuit power by FET. Each switch is controlled on (noy) and off (low) at the timing shown in the waveform diagram, and alternately integrates, outputs, and resets the input signal alternately by the two capacitors Cl and C2. From the output terminal, the values integrated in the previous data section are sequentially output.

FIG. 11 is a block diagram showing a configuration of the interference distortion correction circuit 91 of the present invention.

SIG—1—I, SIG—1—Q, SIG-2-U SIG—2—Q, SIG—n—I, SIG—n—Q are LO—1—I, LO-1-Q, This is a demodulated signal in OFDM corresponding to the carrier signal of LO-2-1, LO-2-Q, LO-n-1, and LO-nQ.

Two demodulated signals SIG-1-I and SIG-l-Q corresponding to the same frequency of the carrier signal will be described as an example. SIG-1-1 is input to one of the amplifiers 123 and one of the amplifiers 124.

SIG-Q is input to another amplifier 123 and another amplifier 124. Here, the amplifier 123 and the amplifier 124 have variable amplification rates, and further have a polarity inversion function.

The output of the amplifier 123 to which SIG-1-I has been input and the output of the amplifier 124 to which SIG-1-Q has been input are combined by one of the adders 125. Similarly, the output of the amplifier 123 to which SIG-Q has been input and the output of the amplifier 124 to which SIG-1-I has been input are combined by another adder 125. The output of the adder 125 is combined with the cancel signal by the adder 126.

[0047] A received signal corresponding to two carrier signals of the same frequency in OFDM may have incomplete orthogonality due to imperfect transmission characteristics and the like. By adjusting the amplification factors and the polarities of the amplifiers 123 and 124, it is possible to correct the signal distortion due to the imperfect orthogonality.

[0048] The output of the adder 46 is input to a warp signal elimination circuit 127, which will be described later, and a multipath signal component (warp signal) due to the use of the bundled cables 21 or the like is eliminated. The output of the warp signal elimination circuit 127 is amplified by the amplifier 128, and an output signal having a signal size corresponding to the input sensitivity of the AZD converter 92 is obtained.

FIG. 12 is a block diagram showing a configuration of the warp signal elimination circuit 127 of the present invention. An input signal 131 generates a signal that is sequentially delayed step by step by an analog delay circuit 133. The The plurality of signals sequentially delayed in a stepwise manner are input to the variable polarity gain amplifier 134, and their outputs are collectively combined by the combiner 136. Further, the input signal is added and combined by the combiner 136 via the amplifier 135.

Here, the delay time of the analog value delay circuit is equal to the frame interval in OFDM. Even if the signal components before and after the frame interfere with each other due to the loop signal, the interference component can be removed by optimizing the polarity and the gain (amplification factor) of the variable polarizer 54.

It is extremely effective that the adjustment control circuit 18 optimizes many parameters such as the amplification factor and the polarity of the interference distortion correction circuit 91 in the interference distortion removal described above by a genetic algorithm.

FIG. 15 is a block diagram showing a detailed configuration of the receiving circuit 15 of the present invention. For example, in the case of 2-bit analog-to-digital conversion, if four values of “00”, “01”, “10”, and “11” can be determined in accordance with the analog value, the digital data can be obtained. The error rate becomes lower as the value of the analog signal obtained becomes closer to the center of each of the multi-valued judgment level ranges, and the error rate becomes higher as the upper or lower limit of the judgment level range becomes closer to the value. Therefore, in the present invention, each of the four determination levels is further subdivided so that the analog signal value is located near the center of the determination level range, and the analog signal is biased toward the boundary! Are distinguished.

[0052] The input signal is input to the + terminal of each comparator 150, and a threshold voltage to be compared is applied to one terminal. Three comparators 150 are provided for each of the multi-values, and each of the three comparators has a threshold voltage of 1Z3 higher than the lower limit and 1Z3 higher than the lower limit of the respective multi-valued judgment level range and lower than the lower limit. A voltage of 2Z3 high (1Z3 low from the upper limit) is applied. Then, only 1 is output as the comparator power whose threshold value is lower than the input signal, and is stored in the latch 151.

Since the upper latch output is input to one of the AND gates 153 via the NOT gate 152, the output of the AND gate 153 becomes 0 in the case of the upper latch output power 力. After all, only the output of AND gate 153 corresponding to the latest threshold lower than the input signal will output a one. In the figure, the judgment output signal marked with a symbol The values near the center of the signal range are shown, and those marked with a symbol △ indicate that the analog signal values are biased near the threshold. Each of the OR gates 155 to 159 outputs multi-level information by ORing the AND gate outputs belonging to each level of the multi-level. Binary converter 160 converts the multi-valued information into binary information.

The frequency is determined by counting the number of judgments made by the AZD converter 92 and the number of judgments made by the AZD converter 92 in the predetermined period using the OR gates 162 and 163 and the histogram counters 164 and 165. Output histogram information. The histogram value is output to the adjustment control circuit 18 as an evaluation signal.

The adjustment control circuit 18 uses a genetic algorithm to calculate the amplification factors of the amplifiers 58 and 59 in the hybrid circuit 12, the output waveform of the cancel signal generation circuit 17, the amount of delay in the compensation circuit 13, and the gain of the amplifier. In addition to adjusting the gain of the amplifier in the interference distortion correction circuit 91 and the like, the adjustment parameter of the transmission circuit of the partner device is transmitted to the partner device, and the waveform parameter of the transmission signal generated by the transmission circuit 10 of the partner device is also adjusted.

FIG. 13 is a block diagram showing a configuration of the clock recovery circuit of the present invention. In order to demodulate received data from a received signal, it is necessary to regenerate a clock signal corresponding to the received data. In the case of the OFDM transmission method, the circuit configuration for clock recovery is complicated. However, as a result of trial and error, the present inventor transmits the clock signal using the pilot signal PL, and the clock recovery circuit 16 uses a crystal filter. As a result, it has been found that extracting pilot signals is particularly suitable.

The received signal 141 input to the clock recovery circuit 17 is amplified by an amplifier 142, and only a pilot signal component is extracted by a crystal filter 143 using a crystal oscillator. A very stable clock signal can be synchronized with a phase locked loop circuit using the phase comparator and the loop filter circuit 145 and the voltage controlled oscillator 146 based on the extracted pilot signal.

Hereinafter, a method for adjusting a circuit using a genetic algorithm will be described. References to genetic algorithms include, for example, the book Genetic Algorithms in Search, Optimization, and Machine Learning by David E. Goldberg published by ADDISON-WESLEY PUBLISHING COMPANY, INC. In 1989. is there. In addition, The genetic algorithm referred to in the present invention refers to an evolutionary computation technique, and also includes an evolutionary programming (EP) technique. References to evolutionary programming include, for example, "Evolutionary Computation: Toward a New Philosophy of Machine Intelligence" by DB Fogel, published by the publisher IEEE Press in 1995.

[0056] The length of the cable 21 connected to the transmission device 1, the position of the intermediate connection point, the characteristic impedance, the frequency characteristic, and the like change due to cable replacement and the like. Therefore, in accordance with the characteristics of the cable 21, the waveform of the transmission signal generated by the transmission circuit 10, the output waveform of the cancellation signal generation circuit 17, the amplification factors of the amplifiers 58 and 59 in the hybrid circuit 12, the delay amount in the compensation circuit 13 and the amplifier It is necessary to adjust the gain of the amplifier and the gain of the amplifier in the interference distortion correction circuit 91 to an optimum state. A genetic algorithm is particularly suitable for this adjustment. The specific adjustment procedure is described in detail in, for example, Japanese Patent Application Laid-Open No. 2000-156627, “Electronic Circuit and Adjustment Method therefor,” and an outline will be given here.

The adjustment procedure is as follows. First, at the time of device startup, low-speed data transmission / reception between transmission / reception circuits is performed using a protocol that can communicate without being adjusted, such as reducing the number of values or reducing the transmission speed. Establish communication. Next, the training signal is transmitted from the transmitting side, and the evaluation signal is obtained on the receiving side. Then, based on the evaluation signal, the adjustment control circuit 18 adjusts the reception circuit using the genetic algorithm and transmits the adjustment parameters of the transmission circuit of the partner device to the partner device using the low-speed data communication channel. Also, adjust the transmission circuit of the partner device. Through this training process, adjustments are made over a wide adjustment range to some extent, and after adjustments, high-speed data communication between transmission devices is established. After that, while performing actual data transmission, fine-tuning is performed online so that the state of the transmission device is kept optimal. The adjustment range during transmission is limited to a small range centered on the last good adjustment result so as not to significantly affect the communication quality of the transmission device. The evaluation function of the genetic algorithm in the online adjustment uses the signal determination result (evaluation signal) in the AZD converter 92.

FIG. 14 is a flowchart showing an outline of the adjustment processing of the present invention executed by the CPU in the adjustment control circuit 18. In S10, initialization is performed. In S11, the genes of each individual in the initial population were generated focusing on the parts considered to have high evaluation values. Let In the embodiment, the register value of the register storing the adjustment value is directly used as the chromosome of the genetic algorithm. In S12, the fitness of each individual is generated. That is, for an individual whose evaluation value has not been measured, the adjustment value of the individual is set in the circuit and a signal is transmitted for a predetermined period to obtain the above-described evaluation signal. Then, the evaluation function value F of the genetic algorithm is calculated by the following equation, for example.

[0059] = (number of 〇) {(number of 〇) + (number of)}

Here, the number of triangles is the count value of the histogram counter 95 at the end of the predetermined period, and the number of triangles is the count value of the histogram counter 94. The counter is reset every predetermined period. In S13, individual selection and selection are performed. That is, the individuals are arranged in order of the evaluation value, and a predetermined number of lower individuals are deleted. In S14, gene crossover is performed. That is, a predetermined number of pairs of two individuals are randomly selected (copied) and rearranged chromosomes to create offspring chromosomes.

[0061] In S15, a predetermined number of individuals are randomly selected (copied) and a mutation that changes the gene is executed to generate a new individual. In S16, it is determined whether the evaluation criterion is satisfied, that is, the best evaluation function value F is equal to or greater than a predetermined value, and the force is determined to be no more than a predetermined value.If the result is positive, the process is terminated. Return and repeat the process. When finished, the individual with the highest fitness in the current population of organisms will be the solution to the optimization problem sought. As described above, the transmission device is automatically adjusted so that stable communication quality can be obtained even in the online state.

Example 2

FIG. 16 is a block diagram illustrating a configuration of a transmission circuit according to a second embodiment of the present invention, and FIG. 17 is a block diagram illustrating a configuration of a reception circuit according to the second embodiment. The second embodiment is obtained by adding a code modulation technique to the first embodiment, thereby reducing the influence of external noise. In the second embodiment, components other than the code modulation circuit 140 and the code inverse modulation circuit 141 are the same as the components of the first embodiment.

In the case of performing code modulation, continuous digital data corresponding to a plurality of OFDM carrier signals are grouped, for example, every 15 data periods, and modulated with a spreading code such as an M sequence. As a result, 15 code-modulated data are obtained. In FIG. 16, the code modulation circuit 140 collects 15 pieces of data from the serial-parallel converter 30 and multiplies them by a matrix created by shifting a spreading code, thereby obtaining code-spread data.

[0064] Data strings consisting of 15 pieces of data corresponding to one carrier frequency in OFDM transmission are denoted by xl, x2, x3, x4, x5, ..., xl3, xl4, and xl5. In the code modulation, the spreading codes in the transmission circuit are pl, p2, p3, p4, p5, ..., pl3, pl4, pl5, and the spreading codes in the reception circuit are ql, q2, q3, q4, q5, · · · ·, Ql3, ql4, ql5. If the data sequence obtained by code-modulating the data sequence of the transmission data is yl, y2, y3, y4, y5,..., Yl3, yl4, yl5, the operation of code modulation is expressed by the following equation.

[0065] [number 1] I = = ι ^χ χ + Ρι ^χ 2 + + + / f +

twenty five

} ' ₃

_{^{y 4 = Ρ4 χ ι + Ps}} x 2 + i x, + i + p s x s + + ρμ- '+ p 2 x u + 13 | 5 5 =

_{^{+ / V'I4 + 4 λ "ΐ}} 5 y i 3 = ρ:, χ, + ρ] Α χ 2 +

"l4 = Pu ^X i + Pl> ^X 2 +

} 'i 5 = + Ρ ^χ 2 + Ρι ^χ ^ + / f + Ρ + + p „x _u + p _u x ₅

[0066] Since this operation is performed before multiplexing by OFDM, it is possible to perform an arithmetic operation digitally using a DSP whose frequency is low. OFDM transmission is performed using the code-modulated data obtained here.

[0067] The received signal is demodulated by OFDM, and the received data sequence yl, y2, y3, y4, y5, ..., yl3, is output to the output of AZD conversion 92 corresponding to the above carrier signal. yl4 and yl5 are obtained. This data sequence is the same as the data sequence obtained by code-modulating the data sequence of the transmission data. Assuming that the received data sequence is code-inverse-modulated as zl, z2, z3, z4, z5,..., Zl3, zl4, zl5, the operation of code-inverse modulation is represented by the following equation.

[0068] [Equation 2] ^{Z \ = faiJ'l + ¾ 2 +} + ^) '4 +}' 5 + + <? 13 Ί3 + 4! 4 + 5/8 Z 2 = (¾ ') +

^Ζ 3 = + ¾32 + y'i + + 7 5 + '

^Ζ 4 = (¾ Ί + Q} '2 +? 6 3 + 7 4 + ^C ) ^! 5 +' · '· ^{+ i} 7l'] 3 + ¾J "l4 + ^ 13 ^ 15) / ⁸ ^ζ 5 =

+ <?:,, 4 + pair ₁₅ ) / ⁸

• 13-Ί + 4 ァ 2 + 5 3 + 4 + 9 ₂ ); 5 + + W 13 + <? | '14 + 12 J / ⁸ ^Z U = few 1 + ^ 15> 2 + + 2' 4 ^{+ ^ + ...... + C 1 '} ΐ3 + 2 § _{_{14 + ^ .3 1 5) /}} 8 Z XS = l 5 l +}; 2 + <7 2)' 3 + +

[0069] In the case of using an M-sequence, as the spreading code, pl = 0, p2 = l, p3 = 0, p4 = 0, p5 = l, p6 = l, p7 = 0, p8 = l, p9 = 0, plO = l, pll = l, pl2 = l, pl3 = l, pl4 = 0, pl5 = 0, ql = —1, q2 = l, q3 = —1, q4 = —1, q5 = l, q6 = l , Q7 = —1, q8 = l, q9 = —1, qlO = 1, qll = l, ql2 = l, ql3 = l, ql4 = —1, ql5 = —1.

As described above, the spreading code used in the code modulation circuit 140 is an M sequence, but the spreading code used in the code inverse modulation circuit 141 is obtained by changing “0” of the M sequence to “1 1”. In this way, data can be demodulated (inverse modulation) without interfering with data before and after the data.

At this time, the received code-inverse-modulated data sequence zl, z2, z3, z4, z5, zl3, zl4, zl5 is the transmission data sequence xl, x2, x3, x4, x5, · Equal to xl3, xl4, xl5.

[0070] As described above, the code-modulated data is code-inverse-modulated by a receiving circuit without interference between the data. Code modulation and code inverse modulation are similarly performed on other carrier signals in OFDM transmission. The same spreading code is used for all carrier signals of the transmission circuit. Similarly, the same spreading code is used for all carrier signals of the receiving circuit. Further, it is preferable to use a different sequence code for each transmission apparatus as the spread code.

In the above example, if the length of the data to be code-modulated at one time is 15, the power is 7, 2, 15, 31, 63, etc., and if the number is 2—1, an M sequence or a Gold code sequence can be used. . By using code modulation technology, even if the cable 21 is adjacent to the cable of another transmission device, harmful effects such as alien crosstalk can be obtained even if the cable 21 is adjacent to the cable of another transmission device because the spread code has little effect on the noise of the transmission device. Noise can be effectively removed.

Claims

The scope of the claims

[1] In digital data transmission equipment,

Transmitting means having an OFDM modulation circuit;

Receiving means comprising an OFDM demodulation circuit and an evaluation signal generating means for generating an adjustment state evaluation signal from the received signal;

Adjusting means for adjusting the receiving means or the transmitting means of the partner device using the evaluation signal;

A digital data transmission device comprising:

[2] Furthermore, a hybrid circuit that can be balanced by a resistance matrix circuit is provided.

The adjusting means also adjusts the hybrid circuit.

2. The digital data transmission device according to claim 1, wherein:

[3] The evaluation signal generation means determines whether the received signal is biased near a force boundary near the center of each multi-level determination level range, and outputs histogram information indicating the frequency. 2. The digital data transmission device according to claim 1, wherein the digital data transmission device is a digital data transmission device.

[4] The digital data transmission device according to claim 1, wherein the adjustment unit adjusts the circuit by a genetic algorithm.

[5] The digital data transmission device according to claim 2, wherein the receiving means further comprises an adjustable echo cancellation circuit.

6. The digital data transmission device according to claim 1, wherein the receiving unit further includes a compensating circuit that is adjustable and that performs analog processing on the received signal to compensate for frequency characteristics of the cable.

7. The digital data transmission device according to claim 1, wherein the receiving means further comprises an adjustable distortion removal circuit for performing analog processing on the received signal.

[8] The transmission means transmits a pilot signal based on a clock signal, and the reception means includes a clock recovery circuit for extracting a pilot signal from the received signal to generate a clock signal. 2. The digital data transmission device according to 1.

[9] The transmission means further includes code modulation means for code modulating data to be transmitted, and the reception means further includes code inverse modulation means for code inverse modulation of the received data. 2. The digital data transmission device according to claim 1, wherein: