1274498 (1) 九、發明說明 【發明所屬之技術領域】 本發明係關於，使用訊號電纜傳送數位資料之裝置。 特別是關於適於IGbit/sec以上之高速資料傳送的傳送裝 置。 【先前技術】 一般，使用訊號電纜傳送數位資料而進行雙向通訊 時，會使用倂合（Hybrid)電路；於此倂合電路中，傳送 訊號與接收訊號之分離係依高週波變壓器 (Transformer)而進行。又，乙太網路中，普遍使用漆 包絞線（LITZ Wire )構造之雙絞線（Twisted-pair Cable)作爲傳送用之電纜，但500MHz以上的高頻率 下，電纜所致之衰減非常大，可利用於傳送之訊號的頻率 頻寬有所限制，故使用多値化之脈衝調變（PAM )技術。 並且，在電纜上傳送訊號會使波形顯著地劣化，故爲得正 確的接收資料，以往均使用數位訊號處理（DSP )技術。 如上所述，以往的數位資料傳送裝置中，係以如下述 非專利文獻1所示之1 000Mbit乙太網路技術爲代表，其 通訊速度以在1個通訊通道上250Mbit/sec爲最高；而在 1個通訊通道上IGbit/sec以上之高速資料傳送則不可能 達到。 又，用於無限數位通訊之OFDM (正交頻分多工）傳 送方式中，訊號之調變以及解調上使用數位訊號處理 (2) 1274498 (DSP )技術，以數位方式進行蝴蝶（Butterfly )運算， 以進行快速傅利葉轉換以及快速傅利葉逆轉換。 〔非專利文獻1〕IEEE 8 02.3 ab仕樣書 http://grouper.ieee.Org/groups/802/3/ab/ 【發明內容】 〔發明所欲解決之課題〕 如上所述之以往的數位資料傳送裝置中，由於以下所 示之問題，使得不可能達到在1個通訊通道上1 Gbit/sec 以上之高速資料傳送。 亦即，問題係在於，在用於高速通訊之訊號的頻率之 下，以高週波變壓器之訊號分離係十分困難，用於數位訊 號處理（DSP )之類比數位轉換器（A/D轉換器）以及數 位處理電路因動作速度、電路規模、消耗電力以及成本等 因素而無法實用化。 又，脈衝振幅調變下會因多値化而使雜音的影響增 大，電纜的傳送頻寬被限制，故通訊速度難以進一步提 高。又，OFDM傳送方式下，DSP之處理速度的制約使得 每秒數十百萬位元以上的通訊速度的資料之處理十分困 難。 本發明之目的在於解決上述以往技術之問題點，提供 在1個通訊通道上lGbit/sec以上之高速資料傳送裝置。 〔解決課題之方法〕 -6- (3) 1274498 本發明之數位資料傳送裝置之 OFDM調變電路之傳送手段、具有 接收訊號產生調整狀態之評價訊號 接收手段、使用上述評價訊號，進 之傳送手段之調整之調整手段。又 置中，進一步具備電阻矩陣電路所 電路，且可使上述調整手段亦調整 又，上述數位資料傳送裝置中 段亦可爲，判定接收訊號係在多値 央附近或偏在境界附近，並輸出3 又，上述數位資料傳送裝置中，亦 遺傳演算法（Genetic Algorithm) ·· 又，上述數位資料傳送裝置中 進一步具備可調整的回音消除（ 又，上述數位資料傳送裝置中，亦 步具備，將接收訊號作類比處理而 可調整的補償電路。又，上述數位 使上述接收手段進一步具備，將接 調整的歪斜除去電路。 又，上述數位資料傳送裝置中 係基於時脈訊號而傳送導引訊號i 由接收訊號抽出導引訊號而生成 (Clock Recovery)電路。又，上 中，亦可使上述傳送手段進一步具 主要特徵爲，具備具有 由OFDM解調電路以及 之評價訊號產生手段之 行接收手段或對方裝置 ，上述數位資料傳送裝 成之可調整平衡之倂合 上述倂合電路。 ，上述評價訊號產生手 之各判定基準範圍之中 笔頻度之直方圖資訊。 可使上述調整手段係依 宋進行電路之調整。 ，亦可使上述接收手段 Echo Cancel )電路。 可使上述接收手段進一 補償電纜之頻率特性之 資料傳送裝置中，亦可 收訊號作類比處理之可 ，亦可使上述傳送.手段 且上述接收手段具備， 時脈訊號之時脈回復 .述數位資料傳送裝置 備，將傳送資料作符號 (4) 1274498 調變之符號調變手段；上述接收手段進一步具備，將接收 資料作符號逆調變之符號逆調變手段。 〔發明之效果〕 採用OFDM方式，使用4條絞對線，可實現全雙工共 計lOGbps之傳送的數位資料傳送裝置。又，本發明之倂 合電路中，並非以高週波變壓器進行傳送訊號的相抵，而 係以電阻矩陣電路RM將訊號分配至2系統，而以增幅器 5 8以及5 9平衡調整並合成此2系統之訊號，以使傳送訊 號相抵，而可高效率地取出接收訊號。 【實施方式】 以下說明，使用4條絞對線所成之以往的LAN電 纜’依OFDM方式可達成全雙工共計1〇個Gbps之傳送 的數位資料傳送裝置。 〔實施例1〕 以下詳細說明本發明之實施形態。第1圖係表示本發 明之全雙工傳收訊電路之構造之方塊圖。又，第2圖係表 示本發明之傳送裝置之全體構造之方塊圖。此裝置主要係 將電腦處理之數位資料與其他電腦、外部裝置或網路等爲 通訊之裝置。 本發明之傳送裝置與相同構造之對方傳送裝置22以 電纜2 1連接。本發明中，電纜2 1係利用於網路上被普遍 -8- (5) 1274498 使用的雙絞線（τ W i s t e d - p a i r C a b 1 e )。此情形下，已經鋪 設之電纜即可利用，故具有十分優越的經濟性之效果。 傳送裝置係由4個全雙工傳收訊電路20、資料分配 電路23以及資料合成電路24而構成。資料分配電路23 係將傳送資料依例如8位元而切割，並將之分配給4個全 雙工傳收訊電路20各2位元。又，資料合成電路24將4 個通道的各2位兀資料復原爲原來的8位元資料。而，亦 可因應需要，而使分配至全雙工傳收訊電路20之資料多 於2位元而成爲可檢出/訂正錯誤之資料結構。 以下說明全雙工傳收訊電路20之構造。傳送資料被 傳送電路10依OFDM方式轉換爲適於傳送之類比訊號， 並被增幅器1 1增幅爲適於傳送之大小，然後被倂合電路 12輸出至電纜21。 傳送訊號之一部會因存在於電纜21之連接點等上的 反射，而產生稱爲「回音（Echo )」之無用訊號。爲求正 確之資料傳送，必須適切地除去此一無用訊號。消除訊號 產生電路1 7基於傳送資料，產生消除無用訊號所需的消 除訊號。 電纜21而來的接收訊號依倂合電路12而與傳送訊號 分離，並連接至補償電路1 3。於補償電路1 3中，以後述 手段補償電纜21之頻率特性所致之波形之劣化。 於接收電路15中，補償電路13之輸出訊號被OFDM 解調’且被干涉歪斜補正電路補正其歪斜或回音，並被類 比數位轉換器轉換爲數位訊號；詳細情形將在後面敘述。 -9- (6) 1274498 數位訊號被統一起來進行並列串列轉換以及評價訊號 處理，而可得接收資料以及後述之評價訊號。 關於上述一連串接收動作之時機，係依時脈回復 16抽出時脈訊號而產生各種定時訊號（Ti Signal )。調整控制電路18內藏CPU，係基於評價 而調整各電路，以使資料之傳收訊正確；詳細情形將 面敘述。 而，傳送路徑21亦可使用單向傳送路徑，而不 全雙工；此時，增幅器11之輸出連接至直接傳送用 2 1，接收用電纜2 1連接至補償電路1 3。又，倂合電5 與消除訊號產生電路17即爲不必要。 第3圖係表示本發明之傳送電路1 0之構造之 圖。傳送資料被串列並列轉換器3 0而轉換（分配） 數之資料。由於若電纜之頻率越高，衰減越大， OFDM中頻率之低調變載波（Carrier)之數目之來切 配位元數。 例如，調變載波於50MHz至400MHz以50MHz 隔使用8個之情形下，分配給各載波之位元數係由頻 較低者開始，分別爲 6x2、5x2、4x2、3x2、3x2、2x x2、1x2。而，x2係爲了，使與1個頻率正交之2個 各自獨立並爲P AM調變而傳送之。 串列並列轉換器3 0之輸出被數位類比轉換器（ 轉換器）3 1轉換爲複數之多値類比訊號。此複數之 類比訊號被調變電路32依OFDM (正交頻分多工） 產生 電路 ming 訊號 在後 必爲 電纜 咨12 方塊 爲複 故依 割分 之間 率之 2、2 載波 D/A 多値 轉換 (7) 1274498 爲被調變之類比訊號。若有必要，D/A轉換器3 1之振幅 (電流値）亦可以調整控制電路1 8依遺傳演算法而調 整，以使之最適化。 第5圖係表示本發明之調變電路32之構造之方塊 圖。載波訊號產生電路64基於時脈訊號62而產生OFDM 之複數頻率的載波訊號。此一載波訊號產生電路64係使 用鎖相迴路（PLL)電路與數位除頻（DiWde)電路以產 生OFDM之載波訊號的時機。由於此一輸出因其本身之高 調波成份，正交性並不充分，故被濾波器電路66轉爲正 弦波訊號之同時，將之增幅爲能夠驅動乘法器.67之振 幅。 LO-bl爲OFDM之最低（第1)載波訊號，L0-卜Q爲 與L0-1-I相同頻率而相位差90°之載波訊號；L0-2-I爲 OFDM之第2載波訊號，L0-2-Q爲與L0-2-I相同頻率而 相位差90°之載波訊號；L0-3-I爲OFDM之第3載波訊 號。OFDM之載波訊號數爲η。同樣地，第η載波訊號爲 L0-n-I與LO-n-Q，相位差爲90°。PL爲引導訊號，擔當 本發明之傳送裝置1之OFDM傳送方式中同步訊號之任 以此處所得2n之載波訊號頻率LOU-I〜L0-n-Q，各自 依乘法器67，與載波訊號所分別對應之輸入訊號6 1，進 行類比乘法運算。以增幅器68將此輸出，就個別頻率作 適當的增幅，並以訊號合成器69將之合成爲1個訊號。 乘法器67方面，可採用例如吉伯特（Gilbert Cell )乘法 -11 - 12744981274498 (1) Description of the Invention [Technical Field of the Invention] The present invention relates to a device for transmitting digital data using a signal cable. In particular, it relates to a transfer device suitable for high-speed data transfer of IGbit/sec or higher. [Prior Art] Generally, when a digital cable is used to transmit digital data for two-way communication, a hybrid circuit is used. In this combined circuit, the separation of the transmitted signal and the received signal is based on a high-frequency transformer (Transformer). get on. In addition, in the Ethernet network, a twisted-pair cable (LIW Wire) is commonly used as a cable for transmission, but at a high frequency of 500 MHz or more, the attenuation caused by the cable is very large. The frequency bandwidth of the signal that can be used for transmission is limited, so multi-channel pulse modulation (PAM) technology is used. Moreover, the transmission of signals on the cable causes the waveform to be significantly degraded, so digital signal processing (DSP) technology has been used in the past for accurate reception of data. As described above, the conventional digital data transmission device is represented by the 1 000 Mbit Ethernet technology as shown in Non-Patent Document 1 below, and the communication speed is the highest at 250 Mbit/sec on one communication channel; High-speed data transmission above IGbit/sec on one communication channel is impossible. In addition, in the OFDM (Orthogonal Frequency Division Multiplexing) transmission method for unlimited digital communication, signal modulation and demodulation using digital signal processing (2) 1274498 (DSP) technology, digitally performing butterfly (Butterfly) Operation for fast Fourier transform and fast Fourier inverse transform. [Non-Patent Document 1] IEEE 8 02.3 ab sample book http://grouper.ieee.Org/groups/802/3/ab/ [Summary of the Invention] [Problems to be Solved by the Invention] The above-described digital data as described above In the transmission device, it is impossible to achieve high-speed data transmission of 1 Gbit/sec or more on one communication channel due to the problems described below. That is, the problem is that under the frequency of the signal for high-speed communication, the signal separation of the high-frequency transformer is very difficult, and the analog-to-digital converter (A/D converter) for digital signal processing (DSP) is very difficult. And digital processing circuits cannot be put into practical use due to factors such as operating speed, circuit scale, power consumption, and cost. Further, under the pulse amplitude modulation, the influence of the noise is increased due to the multi-turn, and the transmission bandwidth of the cable is limited, so that the communication speed is hard to be further improved. Moreover, under the OFDM transmission mode, the processing speed of the DSP restricts the processing of data of communication speeds of several tens of millions of bits per second or more. SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems of the prior art and to provide a high-speed data transmission device of 1 Gbit/sec or more on one communication channel. [Means for Solving the Problem] -6- (3) 1274498 The transmission means of the OFDM modulation circuit of the digital data transmission device of the present invention, the evaluation signal receiving means having the adjustment state of the received signal generation, and the use of the above evaluation signal are transmitted. Means of adjustment of the means of adjustment. Further, the circuit further includes a circuit of the resistor matrix circuit, and the adjusting means can be adjusted. The middle portion of the digital data transmission device can also determine that the receiving signal is near or near the boundary, and outputs 3 Further, in the digital data transmission device, a genetic algorithm is also included. Further, the digital data transmission device further includes an adjustable echo cancellation (in addition, the digital data transmission device further includes a receiving signal And a compensation circuit that can be adjusted by analog processing. Further, the digital device further includes the receiving means for removing the adjusted skew removal circuit. Further, the digital data transmission device transmits the pilot signal i based on the clock signal to receive The signal is extracted by the signal to generate a (Clock Recovery) circuit. Further, the above-mentioned transmission means may further have a main feature of providing a receiving means or a counterpart device having an OFDM demodulating circuit and an evaluation signal generating means. , the above digital data transmission is assembled into an adjustable balance The above-mentioned matching circuit, the above-mentioned evaluation signal generates histogram information of the pen frequency among the respective determination reference ranges of the hand. The adjustment means can be adjusted according to the circuit of Song. The receiving means Echo Cancel can also be used. In the data transmission device capable of making the receiving means into a frequency characteristic of the compensation cable, the receiving signal may be analogized, and the transmitting means and the receiving means may be provided, and the clock signal of the clock signal is recovered. The data transmission device prepares the transmission data as a symbol (4) 1274498 modulation symbol modulation means; the receiving means further comprises means for inversely modulating the received data as a symbol inverse modulation. [Effects of the Invention] The OFDM method uses four twisted pairs to realize a digital data transmission device that transmits a total of 10 Gbps of total duplex. Moreover, in the coupling circuit of the present invention, the transmission signal is not offset by the high-frequency transformer, and the signal is distributed to the 2 system by the resistor matrix circuit RM, and the balance is adjusted and combined by the amplifiers 58 and 59. The signal of the system is such that the transmitted signal is offset, and the received signal can be taken out efficiently. [Embodiment] Hereinafter, a digital data transmission device in which a conventional LAN cable formed by using four twisted pairs is used to realize full-duplex transmission of one Gbps by OFDM can be realized. [Embodiment 1] Hereinafter, embodiments of the present invention will be described in detail. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing the construction of a full duplex transmission and reception circuit of the present invention. Further, Fig. 2 is a block diagram showing the overall configuration of the transport apparatus of the present invention. This device is mainly used to communicate digital data processed by computers with other computers, external devices or networks. The transfer device of the present invention is connected to the counterpart transfer device 22 of the same configuration by a cable 2 1 . In the present invention, the cable 21 is utilized in a twisted pair (τ W i s t e d - p a i c C a b 1 e ) which is commonly used on the network by -8-(5) 1274498. In this case, the already laid cable can be utilized, so it has a very superior economic effect. The transmission device is constituted by four full-duplex transmission and reception circuits 20, a data distribution circuit 23, and a data synthesizing circuit 24. The data distribution circuit 23 cuts the transmission data by, for example, 8 bits and distributes it to 2 bits of each of the 4 full duplex transmission and reception circuits 20. Further, the data synthesizing circuit 24 restores the data of each of the two bits of the four channels to the original octet data. Further, the data allocated to the full-duplex transmission and reception circuit 20 may be more than two bits as a data structure for detecting/correcting errors, as needed. The configuration of the full duplex transmission and reception circuit 20 will be described below. The transmission data is converted by the transmission circuit 10 into an analog signal suitable for transmission by the OFDM method, and is amplified by the amplifier 11 to a size suitable for transmission, and then output to the cable 21 by the combining circuit 12. One of the transmitted signals generates an unwanted signal called "Echo" due to reflection at the connection point of the cable 21 or the like. In order to properly transmit the data, this useless signal must be removed appropriately. The cancellation signal generation circuit 17 generates a cancellation signal required to eliminate the useless signal based on the transmission data. The reception signal from the cable 21 is separated from the transmission signal by the combining circuit 12 and is connected to the compensation circuit 13. In the compensation circuit 13, the means for compensating for the deterioration of the waveform due to the frequency characteristics of the cable 21 will be described later. In the receiving circuit 15, the output signal of the compensating circuit 13 is demodulated by OFDM' and the skew or echo is corrected by the interference skew correcting circuit, and converted into a digital signal by an analog digital converter; the details will be described later. -9- (6) 1274498 The digital signal is unified for parallel serial conversion and evaluation signal processing, and the received data and the evaluation signal described later are available. Regarding the timing of the above-mentioned series of receiving operations, various timing signals (Ti Signal) are generated according to the clock recovery 16 to extract the clock signal. The control control circuit 18 has a built-in CPU, and the circuits are adjusted based on the evaluation so that the data transmission and reception are correct; the details will be described. However, the transmission path 21 can also use a unidirectional transmission path instead of full duplex; at this time, the output of the amplifier 11 is connected to the direct transmission 2 1, and the receiving cable 2 1 is connected to the compensation circuit 13. Further, the combination of the power generation 5 and the cancellation signal generation circuit 17 is unnecessary. Fig. 3 is a view showing the configuration of the transmission circuit 10 of the present invention. The data is converted (allocated) by the serial-to-parallel converter 30. Since the higher the frequency of the cable, the greater the attenuation, the number of low-modulation carriers in the OFDM band is matched by the number of bits. For example, when the modulation carrier is used at 50 MHz from 50 MHz to 400 MHz, the number of bits allocated to each carrier starts from the lower frequency, which is 6x2, 5x2, 4x2, 3x2, 3x2, 2x x2, respectively. 1x2. On the other hand, x2 is transmitted so that two orthogonal to one frequency are independent and modulated by P AM. The output of the serial-parallel converter 30 is converted by the digital analog converter (converter) 3 1 into a plurality of complex analog signals. The complex analog signal is modulated by the modulating circuit 32 according to OFDM (Orthogonal Frequency Division Multiplexing). The ming signal is generated after the cable is used. The block is 12, and the rate between the split points is 2, 2 carrier D/A. Multi-turn conversion (7) 1274498 is an analog signal that is modulated. If necessary, the amplitude (current 値) of the D/A converter 3 1 can also be adjusted by the control circuit 18 in accordance with the genetic algorithm to optimize it. Fig. 5 is a block diagram showing the construction of the modulation circuit 32 of the present invention. The carrier signal generating circuit 64 generates a carrier signal of a complex frequency of OFDM based on the clock signal 62. The carrier signal generating circuit 64 uses a phase locked loop (PLL) circuit and a digital division (DiWde) circuit to generate an OFDM carrier signal. Since this output is not sufficiently orthogonal due to its own high-modulation component, it is amplified by the filter circuit 66 into a sine wave signal and amplified to a amplitude capable of driving the multiplier .67. LO-bl is the lowest (first) carrier signal of OFDM, L0-Bu Q is the carrier signal with the same frequency as L0-1-I and the phase difference is 90°; L0-2-I is the second carrier signal of OFDM, L0 -2-Q is a carrier signal with a phase difference of 90° at the same frequency as L0-2-I; L0-3-I is the third carrier signal of OFDM. The number of carrier signals for OFDM is η. Similarly, the nth carrier signal is L0-n-I and LO-n-Q, and the phase difference is 90°. The PL is a pilot signal, and the carrier signal frequencies LOU-I to L0-nQ of 2n obtained here are the synchronization signals in the OFDM transmission mode of the transmission device 1 of the present invention, respectively, corresponding to the carrier signals by the multiplier 67. The input signal 6 1 is used for analog multiplication. The output of the amplifier 68 is appropriately increased for the individual frequencies and combined by the signal synthesizer 69 into one signal. For the multiplier 67, for example, Gilbert Cell multiplication -11 - 1274498 can be employed.
器。 於此，輸入訊號61雖爲依D/A轉換器31，由複數位 元之數位資料而生之多値類比訊號；但如前所述，每一 OFDM之載波訊號之頻率下，上述之位元數均可能改變。 結果，因應電纜2 1之頻率特性，使良好頻率下之位元數 較多，反之則位元數較少，則可避免傳送品質之低落而提 高傳送速度（通訊速度）。 又，載波訊號產生電路64會產生，與OFDM之複數 載波訊號之時間基準同時之引導訊號PL。引導訊號PL之 頻率係選擇與OFDM之訊號的頻譜（Spectrum)重疊較少 之頻率。例如，L0-1-I之頻率的1/4之頻率。 增幅器 6 8之增幅率方面，若有必要，可就每一 OFDM之載波訊號的頻率，以調整控制電路18，依遺傳演 算法而最適化。 第7圖係表示依本發明之調變電路10，以OFDM調 變之訊號的波形之例之波形圖。此處，載波訊號數η爲 16，載波訊號之頻率之數爲8。 第4圖係表示本發明之倂合電路12之構造之電路 圖。連接至前述之電纜21之連接器35與電阻43〜55所成 之電阻矩陣電路RM連接；又，電阻矩陣電路RM與高週 波變壓器41、56、57連接。電阻47之電阻値與連接至連 接器35之電續21之特性阻抗（Impedance)相等。 增幅器Π的輸出連接至高週波變壓器4 1之1次側。 傳送訊號被增幅器Π增幅，輸出至高週波變壓器41。高 -12- (9) 1274498 接 阻 而 阻 點 點 f 送 之 相 次 電 連 波 電 次 器 5 7 電 連 週波變壓器41之2次側的一端透過電阻43而連接至連 器35與電阻48;透過電阻45而連接至電阻47與電 5 0。高週波變壓器4 1之2次側之另一端則透過電阻44 連接至連接器35與電阻51;透過電阻46而連接至電 4 7與電阻5 3。 連接器35與電阻43與電阻48之連接點爲連接 N1 ;連接器35與電阻44與電阻5 1之連接點爲連接 N2;電阻47與電阻45與電阻50之連接點爲連接點N3 電阻47與電阻46與電阻53之連接點爲連接點N4。傳 訊號係相對於連接點N4而與連·接點N i同相（同極性 電壓）被輸出；相對於連接點N2而與連接點N3逆 (逆極性之電壓）被輸出。 電阻48與電阻53連接至高週波變壓器56之1 側，並分別連接至連接點N1與連接點N 4。電阻5 0與 阻5 1連接至高週波變壓器5 7之1次側，並分別連接至 接點N3與連接點N2。從而，高週波變壓器56與高週 變壓器5 7之2次側中，產生傳送訊號成份的逆相。 接收訊號方面，由連接器35而來的接收訊號經由 阻48以及電阻51、52而連接至高週波變壓器56之i 側；經由電阻48、49以及電阻51而連接至高週波變壓 5 7之1次側。從而，高週波變壓器5 6與高週波變壓器 之2次側中’產生接收訊號成份的同相（同極性之 壓）。 高週波變壓器5 6與高週波變壓器5 7之2次側分別 -13- (10) 1274498 接至增幅器58與增幅器59;增幅器58與增幅器59之輸 出被加法合成而得到接收訊號。此時，傳送訊號之成份係 以逆相合成，故進行接收訊號與傳送訊號的分離。電阻 4 2、電阻5 4、電阻5 5係爲阻抗整合之用。 由於電纜2 1之特性阻抗與電阻47之阻抗値之差等因 素，增幅器58與增幅器59之輸出中逆相之傳送訊號的成 份之大小不一定會一致。因此，使增幅器58與增幅器59 之增幅率爲可變，則可除去傳送訊號之成份。此增幅率可 由調整控制電路1 8依遺傳演算法而最適化。 如此，本發明之倂合電路1 2具有增幅器5 8與增幅器 59等2個訊號路徑；而其最大之特徵爲，此2訊號路徑 而來的訊號輸出之平衡係可調整。 第8圖係表示本發明之消除訊號產生電路之構造之方 塊圖。傳送資料被輸入至多段地連接的移位暫存器（Shift Register) 80，傳送資料的履歷被依序暫時記錄在移位暫 存器。位移暫存器80的輸出被輸入至選擇器81;選擇器 81選擇傳送資料之履歷的一部份。選擇器81之輸出被 D/A轉換器82轉換爲類比電流値，產生消除訊號。選擇 器81之輸出（接點（Tap)位置）以及D/A轉換器82之 輸出（極性以及振幅）由調整控制電路1 8依遺傳演算法 而最適化。 第6圖係表示本發明之補償電路1 3之構造之方塊 圖。輸入至補償電路1 3之輸入訊號7 1被增幅器72增幅 爲適當大小，並被分配器73分配爲相同之2個訊號。所 -14- (11) 1274498 分配之1個訊號以延遲線路74作一定之時間延遲後被輸 入增幅器76。所分配之另1個訊號則不經延遲而輸入至 增幅器75。 個別訊號被增幅器75與76增幅後，以逆相位被輸入 至合成器77。亦即，在合成器77中，係類比計算2個訊 號之差分。合成器77之輸出係以增幅器78適當地增幅， 並作爲補償電路13之輸出訊號79而被輸出。 於此將增幅器75與76之增幅率之比與延遲線路74 之延遲量最適化，則可得補償電纜2 1之頻率特性的頻率 特性。增幅器75.與76其中一方或兩方之增幅率爲可變， 故即使對於電纜2 1的變更亦可提供穩定的傳送。 第9圖係表示本發明之接收電路15之構造之方塊 圖。補償電路1 3之輸出訊號被解調電路90解調爲複數之 多値類比訊號。解調電路90之輸出訊號依干涉歪斜補正 電路9 1而消除其，頻率之正交性的不完全以及限制了使 用電纜21等所引起之多路徑（Multi-path )訊號成份（扭 曲（Warp )訊號）。於干涉歪斜補正電路91所進行者爲 類比積和演算。 干涉歪斜補正電路91中，解調電路90之輸出訊號與 消除訊號產生電路17所輸出之消除訊號被合成，無用訊 號則被消除。干涉歪斜補正電路9 1之輸出被類比數位轉 換器92轉換爲數位訊號。接收波形之歪斜不大時，亦可 省略干涉歪斜補正電路91，而將解調電路90之輸出連接 至類比數位轉換器9 2之輸入。 -15- (12) 1274498 類比數位轉換器92之輸出的數位訊號被統一起來， 由並列串列轉換器93進行並列串列轉換等處理，與得到 接收資料同時地，依評價測定霉路94而產生評價訊號。 第10圖係表示本發明之解調電路90之構造之方塊 圖。輸入至解調電路90之時脈訊號102係由後述之時脈 回復電路1 6供給。載波訊號產生電路1 1 0係基於時脈訊 號而產生OFDM之複數載波訊號。濾波器電路1 12則消除 載波訊號之高調波成份而輸出正弦波。 L0-1-I爲OFDM之最低（第1)載波訊號，L0-1-Q爲 與L0-1-I相同頻率而相位差90°之載波訊號；L0-2-I爲 OFDM之第2載波訊號，L0-2-Q爲與L0-2-I相同頻率而 相位差90°之載波訊號：L0-3-I爲OFDM之第3載波訊 號。OFDM之載波訊號數爲η。同樣地，第η載波訊號爲 LO-η-Ι 與 L0-n-Q，相位差爲 90°。 載波訊號產生電路110、濾波器電路Π2在傳送裝置 上的傳送訊號與接收訊號之時間基準一致之時，可共用調 變電路32。此時，兩端之傳送裝置之其中一端產生時脈 訊號；另一端則利用對方的時脈訊號而動作。 輸入訊號1〇1被增幅器1〇4增幅至適當大小，並進一 步被增幅器1 〇 5增幅至與載波訊號相對應之大小。增幅器 1 0 5之增幅率由調整控制電路1 8依遺傳演算法而最佳 化。增幅器105之輸出訊號1〇6被輸入至乘法器107。乘 法器107係將載波訊號L0-卜I〜L0-n-Q，與各載波訊號分 別對應之訊號1 〇 6，進行類比乘法運算。此輸出在積分電 -16- (13) 1274498 路1 08中，就每一頻率進行一定時間的積分運算，除 餘的頻率成份。接著，被增幅器1 09增幅爲適當大小 得到解調器1 1的輸出103。 第18圖係表示本發明之積分電路108之構造之 圖以及波形圖。電路中之各開關（Switch)係由FET 之類比切換電路所構成。各開關被以波形圖所示之時 控制其開（高）、關（低）；並依 2 個1 (Condenser) Cl、C2而交互重複輸入訊號的積分、 與重設。輸出端子則依序輸出1個前的各資料區間中 分値。 第1 1圖係表示本發明之干涉歪斜補正電路9 1之 之方塊圖。SIG-1-I、 SIG-l-Q、 SIG-2-I、 SIG-2-Q、 n-I、SIG-n-Q 分別爲 L0-1-I、L0-1-Q、L0-2-I、L0-2 L0-n-I、L0-n-Q之載波訊號所對應之，以OFDM解調 訊號。 以下以與載波訊號相同頻率對應之2個解調 SIG-1-I、SIG-1-Q爲例來說明。SIG-1-I被輸入至增 123中之1個與增幅器124中之1個。SIG-1-Q則被 至另一增幅器123之與另一增幅器124。於此，增 123與增幅器124之增幅率爲可變，且具有極性反 能。 SIG-1-I所輸入之增幅器123之輸出，與SIG-1- 輸入之增幅器124之輸出，於加法器125中之1個 成。同樣地，SIG-bQ所輸入之增幅器123之輸出 去多 ，而 電路 所成 機而 電容 輸出 的積 構造 SIG- -Q、 後之 訊號 幅器 輸入 幅器 轉功 Q所 被合 ，與 (14) 1274498 SIG-1-I所輸入之增幅器124之輸出，於另一加法器125 中之1個被合成。加法器125之輸出依加法器126而與消 除訊號合成。 對應於OFDM之同一頻率的2個消除訊號的接收訊號 有時會有，傳送特性之不完全等所致之正交性不完全的情 形。調整增幅器123與增幅器124之增幅率以及極性，可 補正此一正交性之不完全所致之訊號歪斜。 加法器46之輸出被輸入至後述之扭曲訊號消除電路 127，捆束使用電纜21等所引起之多路徑訊號成份（扭曲 訊號）被消除。扭曲訊號消除電路127之輸出以增幅器 128增幅，可得合於A/D轉換器92之輸入感度之訊號大 小之輸出訊號。 第12圖係表示本發明之扭曲訊號除去電路127之構 造之方塊圖。輸入訊號131依類比遲延電路133而依序、 階段地產生延遲的訊號。這些依序階段地延遲的複數訊 號，分別被輸入極性增益（Gain )可變增幅器134，而其 輸出則統一於合成器1 3 6被加法合成。又，輸入訊號經由 增幅器135而於合成器136被加法合成。 於此，類比値延遲電路之延遲時間等於在OFDM下之 片段（Frame )間隔。即使因扭曲訊號而致使片段前後之 訊號成份發生干涉時，亦可依極性增亦可變增幅器5 4之 極性以及增益（增幅率）之最適化而除去干涉成份。 如以上說明之，千涉歪斜之除去中，干涉歪斜補正電 路91之增幅率與極性等多數參數，係由調整控制電路1 8 -18- (15) 1274498 依遺傳演算法而最適化；其效果極爲顯著。 第1 5圖係表示本發明之接收電路1 5之細部構造 塊圖。例如2bit之類比數位轉換之時，對應類比値 可判定「〇 〇」、「〇 1」、「1 0」、「1 1」4個値，貝[J 數位資料；而，接收之類比訊號之値若越靠近多値各 判定基準範圍的中央，則錯誤率越低，越靠近判定基 圍之上限或下限閾値，則錯誤率越高。因此，本發明 値之個別判定基準作進一步細分，以區別類比訊號値 定基準範圍之中央附近之情形、以及偏於境界閾値附 情形。 輸入訊號被輸入至各比較器（Comparator) 150 端子；-端子則施以比較之閾値電壓。針對多値之每 値均設置3個比較器1 5 0 ; 3個比較器上分別施以多 自之判定基準範圍的下限、高於下限1 /3、高於下限 (低於上限1 /3 )之電壓，以作爲閾値電壓。然後， 閾値較輸入訊號爲低之比較器輸出1，並記憶至 (Latch ) 15 1。 AND閘153之一方係由其上段之閂鎖輸出透過 閘152而輸入，故上段之閂鎖輸出爲1之時，AND _ 之輸出爲〇。結果，僅有對應於較輸入訊號爲低之最 値的AND閘1 5 3輸出1。圖中，附有〇記號之判定 訊號係表示，類比訊號値係在判定基準範圍之中央 者；附有△記號者則爲，類比訊號値偏於閾値附近者 OR閘155〜159係將屬於多値各自之基準的AND閘輸 之方 ，若 可得 自之 準範 將4 在判 近之 之+ 一個 値各 2/3 僅由 閂鎖 NOT 153 近閾 輸出 附近 。各 出聯 -19- (16) 1274498 集（Disjunction)而輸出多値資訊。2進位轉換器160則 將多値資訊轉換爲2進位資訊。 在一定期間內，將A/D轉換器92之判定結果中，〇 之數目與△之數目，以OR閘162、163以及直方圖計數 器（Histogram Counter) 164、165計算，而輸出頻度之 直方圖資訊。直方圖値係作爲評價訊號而被輸出至調整控 制電路1 8。 調整控制電路1 8使用遺傳演算法，調整倂合電路1 2 中增幅器58、59之增幅率、消除訊號產生電路17之輸出 波形、補償電路1 3中延遲量與增幅器之增益、干涉歪斜 補正電路91中增幅器之增益等，同時將對方裝置之傳送 電路的調整參數傳送至對方裝置；亦調整於對方裝置之傳 送電路10所產生之傳送訊號之波形參數等。 第13圖係表示本發明之時脈回復電路之構造之方塊 圖。爲由接收訊號解調接收資料，必須回復對應於所接收 之資料的時脈訊號。OFDM傳送方式下，雖然時脈回復所 需之電路構造係屬複雜，但本件之發明者依試誤之結果得 知，使用引導訊號PL以進行時脈訊號之傳達，並在時脈 回復電路16中，以晶體濾波器（Crystal Filter)來進行 引導訊號之抽出之手段，特別適用。 輸入時脈回復電路17之接收訊號141被增幅器142 增幅；而使用水晶晶振之晶體濾波器1 43僅抽出其引導訊 號成份。以此處抽出之引導訊號爲基準，依相位比較器、 迴圈濾波器電路145、以及使用電壓控制型發振器146之 -20- (17) 1274498 鎖相迴圈（Phase-lock Loop)電路，可使時脈訊號的同步 化十分穩定。 以下說明使用遺傳演算法之電路的調整手段。而，遺 傳演算法的參考文獻例如 ，ADDISON-WESLEY PUBLISHING COMPANY，INC.於 1 9 8 9 年出版之，D a v i d E Goldberg 著之 「 Genetic Algorithms in Search, Optimization, and Machine Learning」。而，本發明戶斤謂 遺傳演算法係指進化的計算技巧，且亦含進化的程式 (Programming )( EP )技巧。進化的程式的參考文獻例 如 IEEE Press於 1 995年出版之，D· B. Fogel著之 「Evolutionary Computation: Toward a New Philosophy of Machine Intelligence」。 連接至傳送裝置1之電纜21之長度或中間連接點的 位置、特性阻抗、頻率特性等，會因電纜之交換等而變 化。於此，必須配合電纜2 1之特性，將傳送電路1 〇所產 生之傳送訊號的波形、消除訊號產生電路1 7之輸出波 形、倂合電路12中增幅器5 8、5 9之增幅率、補償電路 13中延遲量與增幅器之增益、干涉歪斜補正電路91中增 幅器之增益等，調整至最適狀態。此一調整特別適合依遺 傳演算法而進行。具體的調整順序例如日本特開2000-156627號公報「電子電路及其調整手段」中有詳細說 明，故此處僅槪要說明。 調整順序之第一步係，於起動裝置之際，減少多値 數，降低傳送速度等，使用未調整亦可通訊之協定 -21 - (18) 1274498 (Protocol )以確立傳收訊電路間之低速資料通訊。其 次，使傳送側發出訓練（Training )訊號而在接收側得到 評價訊號。接著，基於此一評價訊號，調整控制電路1 8 使用遺傳演算法調整接收電路，同時使用低速資料通訊通 道來將對方裝置之傳送電路之調整參數傳送至對方裝置， 且亦調整對方裝置的傳送電路。依此一訓練處理以進行某 程度之廣泛調整，以確立調整後傳送裝置間之高速資料通 訊。其後，一面進行實際之資料傳送，一面在線上進行微 調以使傳送裝置保持在最適狀態。限定傳送中的調整範圍 在，以之前的良好調整結果爲中心之微小範圍內，以使對 傳送裝置之通訊品質不至於有大影響。線上之調整中的遺 傳演算法之評價函數係利用A/D轉換器92之訊號的判定 結果（評價訊號）。 第1 4圖係表示，調整控制電路中實行之，本發明的 調整處理之內容之流程圖。S 1 0中，進行初期化。S 1 1 中，使作爲初期集團之各個體之遺傳因子，以評價値高之 部份爲中心而發生。實施例中，直接使用納入調整値之登 錄器的登錄値，作爲遺傳演算法的染色體。S 1 2中，進行 各個體適應度之產生。亦即，對於未測定評價値之個體， 將個體的調整値設定於電路而僅於一定期間傳送訊號，得 到前述之評價訊號。然後，以例如下式來計算遺傳演算法 之評價函數値F。 F = (〇之數目）/{(〇之數目）+ (△之數目）} (19) 1274498 於此，〇之數目係上述一定期間末之直方圖計數器 95之計數値；△之數目係直方圖計數器94之計數値。計 數器於每一定期間重設。S13中，實行個體之選擇、淘 汰。亦即將個體依評價値順序排列，刪去下方一定個數之 個體。S14中，實行遺傳因子之交叉。亦即，隨機地選擇 (複寫）一定數目的2個個體之配對，組合變換染色體而 製作子染色體。 S15中’隨機地選擇（複寫）一定數目的個體，實行 變化該遺傳因子之突變而產生新個體。S16中，判斷.是否 滿足評價基準，亦即最佳評價函數値F是否在所定値以 上；結果爲肯定則結束處理，否定則回到S 1 2並重複處 理。若爲結束處理之情形，則該時點之生物集團中適應度 最高之個體爲所求之最適化問題之解。如上所述，傳送裝 置即使在線上狀態亦可自動調整，以得穩定之通訊品質。 〔實施例2〕 第1 6圖係表示本發明之第2實施例的傳送電路之構 造之方塊圖；第17圖係表示本發明之第2實施例的接收 電路之構造之方塊圖。第2實施例係於第1實施例上追加 符號調變技術；依此可降低外來雜音之影響。第2實施例 中’符號調變電路1 40以及符號逆調變電路1 4 1以外之構 成要素與第1實施例之構成要素相同。 進行符號調變時，將對應於OFDM之複數載波訊號的 -23- (20) 1274498 連續數位資料，以例如每1 5資料週期而整合，並以M系 列等之擴散符號來進行調變。依此可得1 5個符號調變資 料。 第1 6圖中，於符號調變電路1 4 0中，將1 5個由串列 並列轉換器30而來的資料整合，並乘上平移（Shift)擴 散符號所作成之行列，而得到符號擴散之資料。 對應於〇 F D Μ傳送中1個載波頻率之1 5個資料所成 之資料列以 xl、 χ2、 χ3、 χ4、 χ5、…、χ13、 χ14、 χ15 表 示。又，符號調變中傳送電路上的擴散符號以pl、p2、 ρ3、ρ4、ρ5、…、ρ13、ρ14、ρ15表示；接收電路上的擴 散符號以 ql、q2、q3、q4、q5、…、ql3、ql4、ql5 表 示。將接收資料的資料列符號調變之資料列以y 1、y 2、 y3、y4、y5.....yl3、yl4、yl5表示，則符號調變之演 算如下式所示。Device. Here, although the input signal 61 is a multi-signal analog signal generated by the digital data of the plurality of bits according to the D/A converter 31, as described above, the frequency of the carrier signal of each OFDM is as described above. The number of elements may change. As a result, in response to the frequency characteristic of the cable 21, the number of bits at a good frequency is large, and if the number of bits is small, the transmission quality can be avoided and the transmission speed (communication speed) can be improved. Further, the carrier signal generating circuit 64 generates a pilot signal PL at the same time as the time reference of the complex carrier signals of the OFDM. The frequency of the pilot signal PL is selected to be less frequent than the spectrum of the OFDM signal. For example, the frequency of 1/4 of the frequency of L0-1-I. In terms of the amplification rate of the amplifier 68, if necessary, the frequency of the carrier signal for each OFDM can be adjusted by the adjustment control circuit 18 according to the genetic algorithm. Fig. 7 is a waveform diagram showing an example of a waveform of a signal modulated by OFDM according to the modulation circuit 10 of the present invention. Here, the number of carrier signals η is 16, and the number of frequencies of the carrier signals is 8. Fig. 4 is a circuit diagram showing the construction of the coupling circuit 12 of the present invention. The connector 35 connected to the aforementioned cable 21 is connected to the resistor matrix circuit RM formed by the resistors 43 to 55; further, the resistor matrix circuit RM is connected to the high-frequency transformers 41, 56, 57. The resistance 値 of the resistor 47 is equal to the characteristic impedance (Impedance) of the electrical connection 21 connected to the connector 35. The output of the amplifier Π is connected to the primary side of the high-frequency transformer 41. The transmission signal is amplified by the amplifier and output to the high-frequency transformer 41. High-12- (9) 1274498 Resistor and resistance point f is sent to the phase electric wave substation 5 7 The end of the secondary side of the electric coupling transformer 41 is connected to the connector 35 and the resistor 48 through the resistor 43. Connected to resistor 47 and capacitor 50 through resistor 45. The other end of the secondary side of the high-frequency transformer 41 is connected to the connector 35 and the resistor 51 through the resistor 44, and is connected to the resistor 47 through the resistor 46. The connection point between the connector 35 and the resistor 43 and the resistor 48 is a connection N1; the connection point between the connector 35 and the resistor 44 and the resistor 51 is a connection N2; the connection point between the resistor 47 and the resistor 45 and the resistor 50 is a connection point N3. The connection point with the resistor 46 and the resistor 53 is the connection point N4. The transmission number is output in phase with the connection point N i (the same polarity voltage) with respect to the connection point N4, and is inverted (voltage of the reverse polarity) with respect to the connection point N2 and the connection point N3. The resistor 48 and the resistor 53 are connected to one side of the high-frequency transformer 56, and are connected to the connection point N1 and the connection point N 4, respectively. The resistor 50 and the resistor 5 1 are connected to the primary side of the high-frequency transformer 57, and are connected to the contact N3 and the connection point N2, respectively. Thus, in the secondary side of the high-frequency transformer 56 and the high-cycle transformer 57, an inverse phase of the transmitted signal component is generated. In terms of receiving signals, the received signal from the connector 35 is connected to the i-side of the high-frequency transformer 56 via the resistor 48 and the resistors 51, 52; and connected to the high-frequency transformer 5 7 via the resistors 48, 49 and the resistor 51. side. Therefore, the high-frequency transformer 57 and the secondary side of the high-frequency transformer generate the same phase (the same polarity) of the received signal components. The high-frequency transformer 57 and the secondary side of the high-frequency transformer 57 are respectively -13-(10) 1274498 connected to the amplifier 58 and the amplifier 59; the outputs of the amplifier 58 and the amplifier 59 are combined to obtain a reception signal. At this time, the components of the transmitted signal are synthesized in reverse phase, so that the separation of the received signal and the transmitted signal is performed. Resistor 4 2, resistor 5 4, and resistor 5 5 are used for impedance integration. Due to factors such as the difference between the characteristic impedance of the cable 21 and the impedance 値 of the resistor 47, the magnitude of the component of the transmission signal of the inverse phase in the output of the amplifier 58 and the amplifier 59 does not necessarily coincide. Therefore, by increasing the rate of increase of the amplifier 58 and the amplifier 59, the components of the transmitted signal can be removed. This rate of increase can be optimized by the adjustment control circuit 18 in accordance with the genetic algorithm. Thus, the combining circuit 12 of the present invention has two signal paths such as an amplifier 58 and an amplifier 59; and the greatest feature is that the balance of the signal output from the two signal paths can be adjusted. Fig. 8 is a block diagram showing the construction of the cancel signal generating circuit of the present invention. The transfer data is input to a shift register (Shift Register) 80 connected in multiple stages, and the history of the transferred data is temporarily recorded in the shift register in this order. The output of the shift register 80 is input to the selector 81; the selector 81 selects a portion of the history of the transmitted data. The output of the selector 81 is converted by the D/A converter 82 to an analog current 値 to generate a cancellation signal. The output (tap position) of the selector 81 and the output (polarity and amplitude) of the D/A converter 82 are optimized by the adjustment control circuit 18 in accordance with the genetic algorithm. Fig. 6 is a block diagram showing the construction of the compensation circuit 13 of the present invention. The input signal 7 1 input to the compensation circuit 13 is amplified by the amplifier 72 to an appropriate size and distributed by the distributor 73 as the same two signals. The -14-(11) 1274498 assigned one signal is input to the booster 76 after a certain time delay of the delay line 74. The other signal assigned is input to the amplifier 75 without delay. The individual signals are amplified by the amplifiers 75 and 76 and input to the synthesizer 77 in reverse phase. That is, in the synthesizer 77, the analogy calculates the difference between the two signals. The output of synthesizer 77 is suitably amplified by booster 78 and output as output signal 79 of compensation circuit 13. Here, the ratio of the amplification ratio of the amplifiers 75 to 76 and the delay amount of the delay line 74 are optimized, and the frequency characteristic of the frequency characteristic of the cable 2 1 can be obtained. The increase rate of one or both of the amplifiers 75. and 76 is variable, so that a stable transmission can be provided even if the cable 21 is changed. Fig. 9 is a block diagram showing the construction of the receiving circuit 15 of the present invention. The output signal of the compensation circuit 13 is demodulated by the demodulation circuit 90 into a plurality of analog signals. The output signal of the demodulation circuit 90 is eliminated by the interference correction circuit 91, the orthogonality of the frequency is incomplete, and the multi-path signal component (Warp) caused by the use of the cable 21 or the like is limited. Signal)). The analog product and the calculation are performed on the interference skew correction circuit 91. In the interference skew correction circuit 91, the output signal of the demodulation circuit 90 and the cancellation signal outputted by the cancellation signal generation circuit 17 are combined, and the useless signal is eliminated. The output of the interference skew correction circuit 9 1 is converted into a digital signal by the analog digital converter 92. When the skew of the received waveform is not large, the interference skew correction circuit 91 may be omitted, and the output of the demodulation circuit 90 may be connected to the input of the analog digital converter 92. -15- (12) 1274498 The digital signals of the output of the analog-to-digital converter 92 are unified, and the parallel-serial converter 93 performs parallel-serial conversion and the like, and simultaneously determines the mold path 94 according to the evaluation. Generate evaluation signals. Fig. 10 is a block diagram showing the construction of the demodulation circuit 90 of the present invention. The clock signal 102 input to the demodulation circuit 90 is supplied from a clock recovery circuit 16 which will be described later. The carrier signal generating circuit 1 1 0 generates a complex carrier signal of OFDM based on the clock signal. The filter circuit 1 12 cancels the high-modulation component of the carrier signal and outputs a sine wave. L0-1-I is the lowest (first) carrier signal of OFDM, L0-1-Q is the carrier signal with the same frequency as L0-1-I and the phase difference is 90°; L0-2-I is the second carrier of OFDM The signal, L0-2-Q is a carrier signal with the same frequency as L0-2-I and a phase difference of 90°: L0-3-I is the third carrier signal of OFDM. The number of carrier signals for OFDM is η. Similarly, the nth carrier signal is LO-η-Ι and L0-n-Q with a phase difference of 90°. The carrier signal generating circuit 110 and the filter circuit Π2 can share the modulation circuit 32 when the transmission signal on the transmitting device coincides with the time reference of the received signal. At this time, one end of the transmitting device at both ends generates a clock signal; the other end operates with the other party's clock signal. The input signal 1〇1 is amplified by the amplifier 1〇4 to an appropriate size, and further amplified by the amplifier 1 〇 5 to correspond to the carrier signal. The amplification rate of the amplifier 1 0 5 is optimized by the adjustment control circuit 18 according to the genetic algorithm. The output signal 1〇6 of the amplifier 105 is input to the multiplier 107. The multiplier 107 performs analog-like multiplication by the carrier signals L0-Bu I~L0-n-Q and the signals 1 〇 6 corresponding to the respective carrier signals. This output is integrated in the -16- (13) 1274498 way 108, and the integral operation is performed for each frequency for a certain time, except for the frequency components. Next, the booster 109 is amplified to an appropriate size to obtain the output 103 of the demodulator 11. Fig. 18 is a view showing the configuration of the integrating circuit 108 of the present invention and a waveform chart. Each switch (Switch) in the circuit is composed of an analog switching circuit such as a FET. Each switch is controlled to be on (high) and off (low) as shown in the waveform diagram; and the integral and reset of the input signal are alternately repeated according to two 1 (Condenser) Cl and C2. The output terminal outputs the sub-divisions in each of the previous data sections in sequence. Fig. 1 is a block diagram showing the interference skew correction circuit 9 1 of the present invention. SIG-1-I, SIG-lQ, SIG-2-I, SIG-2-Q, nI, SIG-nQ are L0-1-I, L0-1-Q, L0-2-I, L0-2, respectively Corresponding to the carrier signals of L0-nI and L0-nQ, the signals are demodulated by OFDM. Hereinafter, two demodulation SIG-1-I and SIG-1-Q corresponding to the same frequency as the carrier signal will be described as an example. SIG-1-I is input to one of the increments 123 and one of the boosters 124. The SIG-1-Q is passed to another booster 123 and another booster 124. Here, the increase rate of the 123 and the enhancer 124 is variable and has a polarity inversion. The output of the booster 123 input by the SIG-1-I and the output of the booster 124 of the SIG-1-input are one of the adders 125. Similarly, the output of the booster 123 input by SIG-bQ is much larger, and the circuit is formed by the product and the product of the capacitor output is constructed by SIG--Q, and the subsequent signal-amplifier input is converted to work Q, and 14) 1274498 The output of the booster 124 input by SIG-1-I is synthesized in one of the other adders 125. The output of adder 125 is combined with the cancellation signal by adder 126. The reception signals of the two cancellation signals corresponding to the same frequency of OFDM may have an incomplete orthogonality due to incomplete transmission characteristics and the like. Adjusting the amplification rate and polarity of the amplifier 123 and the amplifier 124 can correct the signal skew caused by the incompleteness of the orthogonality. The output of the adder 46 is input to a distortion signal eliminating circuit 127, which will be described later, and the multipath signal component (distorted signal) caused by the bundle using the cable 21 or the like is eliminated. The output of the distorted signal canceling circuit 127 is amplified by the booster 128 to obtain an output signal that is equal to the signal level of the input sensitivity of the A/D converter 92. Fig. 12 is a block diagram showing the construction of the distortion signal removing circuit 127 of the present invention. The input signal 131 generates a delayed signal sequentially and in stages by the analog delay circuit 133. These successively delayed complex signals are respectively input to the polarity gain (Gain) variable amplifier 134, and the outputs thereof are unified by the synthesizer 136 to be combined. Further, the input signal is added to the synthesizer 136 via the amplifier 135 to be combined. Here, the delay time of the analog 値 delay circuit is equal to the frame interval under OFDM. Even if the signal component before and after the segment interferes due to the distortion signal, the interference component can be removed by changing the polarity and the gain (amplification rate) of the amplitude enhancer 54 by the polarity increase. As described above, in the removal of the skew, the majority of the parameters such as the amplification rate and the polarity of the interference correction circuit 91 are optimized by the genetic algorithm in the adjustment control circuit 1 8 -18-(15) 1274498; Extremely significant. Fig. 15 is a block diagram showing a detailed structure of the receiving circuit 15 of the present invention. For example, when the analog conversion of 2bit is used, the corresponding analogy can determine four 値, 〇1, "0", and "1 1", and [J digital data; and, the analog signal received If the closer to the center of each of the determination reference ranges, the lower the error rate is, the closer to the upper or lower threshold of the determination base is, the higher the error rate is. Therefore, the individual decision criteria of the present invention are further subdivided to distinguish the analog signal from the vicinity of the center of the reference range and the boundary threshold. The input signal is input to each of the Comparator 150 terminals; the - terminal is applied with a comparison threshold voltage. Three comparators 1 5 0 are set for each of the multiple turns; the lower limit of the multi-self determination reference range is applied to the three comparators, the upper limit is 1 / 3, and the upper limit is higher than the lower limit (1 / 3 below the upper limit) The voltage is used as the threshold voltage. Then, the comparator whose threshold is lower than the input signal outputs 1 and memorizes to (Latch) 15 1. One of the AND gates 153 is input by the latch output of the upper stage through the gate 152. Therefore, when the latch output of the upper stage is 1, the output of AND_ is 〇. As a result, only the AND gate 1 5 3 corresponding to the lowest input signal is output 1 . In the figure, the judgment signal with the 〇 mark indicates that the analog signal is at the center of the judgment reference range; if the △ mark is attached, the analog signal 値 is adjacent to the threshold OR, the OR gate 155~159 will belong to the The side of the AND gate of each of the benchmarks, if available, is 4 in the vicinity of the nearest + 2 / 3 only by the latch near NOT 153 near the threshold output. Each output -19- (16) 1274498 (Disjunction) and output multiple information. The 2-bit converter 160 converts the multi-turn information into 2-bit information. In a certain period of time, the number of 〇 and the number of Δ in the determination result of the A/D converter 92 are calculated by the OR gates 162 and 163 and the histogram counters 164 and 165, and the histogram of the output frequency is calculated. News. The histogram is output to the adjustment control circuit 18 as an evaluation signal. The adjustment control circuit 18 uses the genetic algorithm to adjust the amplification rate of the amplifiers 58, 59 in the combining circuit 12, the output waveform of the cancellation signal generating circuit 17, the delay amount in the compensation circuit 13 and the gain of the amplifier, and the interference skew. The gain of the amplifier in the circuit 91 is corrected, and the adjustment parameters of the transmission circuit of the counterpart device are transmitted to the counterpart device; the waveform parameters of the transmission signal generated by the transmission circuit 10 of the counterpart device are also adjusted. Figure 13 is a block diagram showing the construction of the clock recovery circuit of the present invention. In order to demodulate the received data by the received signal, it is necessary to reply to the clock signal corresponding to the received data. In the OFDM transmission mode, although the circuit structure required for the clock recovery is complicated, the inventor of the present invention knows that the pilot signal PL is used to transmit the clock signal, and the clock recovery circuit 16 is used. Among them, a means for extracting a pilot signal by a crystal filter is particularly suitable. The received signal 141 input to the clock recovery circuit 17 is amplified by the amplifier 142; and the crystal filter 143 using the crystal crystal extracts only the pilot signal component. Based on the pilot signal extracted here, the phase comparator, the loop filter circuit 145, and the -20- (17) 1274498 phase-lock loop circuit using the voltage-controlled oscillator 146 It can make the synchronization of the clock signal very stable. The following describes the adjustment means of the circuit using the genetic algorithm. However, references to genetic algorithms are, for example, ADDISON-WESLEY PUBLISHING COMPANY, INC., published in 1989, D a v i d E Goldberg, "Genetic Algorithms in Search, Optimization, and Machine Learning." However, the present invention refers to genetic algorithms as evolutionary computational techniques and also includes evolutionary programming (EP) techniques. Examples of evolutionary programs are published by IEEE Press in 1995, and D. B. Fogel, "Evolutionary Computation: Toward a New Philosophy of Machine Intelligence." The length of the cable 21 connected to the conveyor 1, or the position, characteristic impedance, frequency characteristics, and the like of the intermediate connection point may vary due to the exchange of cables or the like. Herein, the waveform of the transmission signal generated by the transmission circuit 1 , the output waveform of the cancellation signal generating circuit 17 , the amplification rate of the amplifiers 58 8 and 59 in the combining circuit 12 must be matched with the characteristics of the cable 2 1 . The delay amount in the compensation circuit 13 and the gain of the amplifier, the gain of the amplifier in the interference skew correction circuit 91, and the like are adjusted to an optimum state. This adjustment is particularly suitable for the algorithm of the legacy. The specific adjustment procedure is described in detail in the "Electronic circuit and its adjustment means" in Japanese Laid-Open Patent Publication No. 2000-156627, and is hereby incorporated by reference. The first step in the adjustment sequence is to reduce the number of turns, reduce the transmission speed, etc. when starting the device, and use the unadjusted communication protocol - 21 - (18) 1274498 (Protocol) to establish the communication between the circuits. Low speed data communication. Secondly, the transmitting side sends a training signal and the receiving side receives an evaluation signal. Then, based on the evaluation signal, the adjustment control circuit 18 uses the genetic algorithm to adjust the receiving circuit, and uses the low-speed data communication channel to transmit the adjustment parameters of the transmission circuit of the counterpart device to the counterpart device, and also adjusts the transmission circuit of the counterpart device. . According to this training process, a certain degree of adjustment is made to establish high-speed data communication between the adjusted transmission devices. Thereafter, the actual data transfer is performed while fine-tuning is performed on the line to keep the transfer device in an optimum state. The adjustment range in the limited transmission is within a small range centered on the previous good adjustment result so that the communication quality of the transmission device is not greatly affected. The evaluation function of the genetic algorithm in the adjustment on the line is the judgment result (evaluation signal) of the signal of the A/D converter 92. Fig. 14 is a flow chart showing the contents of the adjustment processing of the present invention carried out in the adjustment control circuit. In S 1 0, initialization is performed. In S 1 1 , the genetic factors of each body of the initial group are caused to be centered on the evaluation of the high part. In the embodiment, the registration 纳入 of the register incorporating the adjustment 直接 is directly used as the chromosome of the genetic algorithm. In S 1 2, the generation of individual body fitness is performed. That is, for an individual who has not measured the evaluation, the individual adjustment 値 is set in the circuit and the signal is transmitted only for a certain period of time, and the aforementioned evaluation signal is obtained. Then, the evaluation function 値F of the genetic algorithm is calculated by, for example, the following formula. F = (number of 〇) / {(number of 〇) + (number of △)} (19) 1274498 Here, the number of 〇 is the count of the histogram counter 95 at the end of the above certain period; the number of △ is a histogram The count of the counter 94 is 値. The counter is reset every time period. In S13, individual selection and elimination are implemented. Individuals are also arranged in the order of evaluation, and a certain number of individuals below are deleted. In S14, the intersection of genetic factors is implemented. That is, a pair of two individual pairs are randomly selected (rewritten), and the chromosomes are combined to produce a sub-chromosome. In S15, a certain number of individuals are randomly selected (rewritten), and mutations of the genetic factors are changed to produce new individuals. In S16, it is judged whether or not the evaluation criterion is satisfied, that is, whether the optimum evaluation function 値F is above the predetermined value; if the result is affirmative, the processing is terminated, and if not, the processing returns to S1 2 and the processing is repeated. In the case of the end of the treatment, the individual with the highest fitness in the biota at that point in time is the solution to the optimal problem sought. As described above, the transmitting device can be automatically adjusted even on the line to achieve stable communication quality. [Embodiment 2] Fig. 16 is a block diagram showing a configuration of a transmission circuit of a second embodiment of the present invention, and Fig. 17 is a block diagram showing a configuration of a reception circuit according to a second embodiment of the present invention. In the second embodiment, the symbol modulation technique is added to the first embodiment; accordingly, the influence of the external noise can be reduced. In the second embodiment, the constituent elements other than the 'symbol modulation circuit 1 40 and the sign inverse modulation circuit 141 are the same as those of the first embodiment. When symbol modulation is performed, -23-(20) 1274498 consecutive digital data corresponding to the complex carrier signal of OFDM is integrated, for example, every 1 5 data periods, and modulated by a spreading symbol such as M series. According to this, 15 symbolic changes can be obtained. In Fig. 16, in the symbol modulation circuit 1404, 15 pieces of data from the tandem parallel converter 30 are integrated and multiplied by the Shift diffusion symbol. Information on the spread of symbols. The data columns corresponding to 15 data of one carrier frequency in the transmission of 〇 F D Μ are represented by xl, χ2, χ3, χ4, χ5, ..., χ13, χ14, χ15. Moreover, the diffusion symbols on the transmission circuit in the symbol modulation are represented by pl, p2, ρ3, ρ4, ρ5, ..., ρ13, ρ14, ρ15; the diffusion symbols on the receiving circuit are ql, q2, q3, q4, q5, ... , ql3, ql4, ql5 said. The data of the data column of the received data is expressed by y 1 , y 2 , y3 , y4 , y5 . . . yl3 , yl 4 , yl 5 , and the calculation of the symbol modulation is as follows .
yi = PlXl + Ρ2χ2 + P3X3 + P4X4 + PsX5 + ……+ 尸13X13 + 外4 七4 + A5X15 y2 = p2xx + p3x2 + p,x3 + p5x4 + p6x5 + ……+ A4x13 + A5x14 + Ah y3 = P3Xl + P4X2 + P5X3 + P6X4 + PlX5 + ……+ ^5X13 + + 户2'5 y4 = P4Xl + P$X2 + ΡβΧ3 + PlXA + + ……+ A 七3 + 户 2尤14 + 七5 y5 = psxx + p6x2 + ρΊχ3 + p8x4 + p9x5 + ……+ 户2x13 + 夕3七4 + p4x15 yi3 = PnX\ + PuX2 + P\5X3 + P\x4 + PlX5 + ……+ /½½ + A'14 + A2X15 ^14 = P\4Xl + Pl5X2 + PlX3 + PlX4 + ΛΧ5 + ……+ ^15 = P\5X\ + P\X2 + PlX3 + P3X4 + PaX5 + ……+ Pl2X13 + Pl3X14 + 此一演算係以OFDM多重化之前爲之，故可作頻率 低、使用D S P之數位演算處理。使用此處所得符號調變 -24- (21) 1274498 資料而進行OFDM傳送。 所接收之訊號以OFDM解調，於對應上述載波之A/D 轉換器92之輸出中，可得接收之資料列yl、y2、y3、 y4、y5.....yl3、yl4、yl5。此資料列與將傳送資料的 資料列符號調變後之資料列相同。將所接收之上述資料列 符號逆調變後之資料列，以 zl、z2、z3、z4、z5..... z 1 3、z 1 4、z 1 5表示，則符號逆調變之演算如下式所示。 A =(仏乃+分2少2 +〜y3 +《4少4切5少5 +……+ 1^+^14+^15)/8 = +^4^3 +^5^4 +^5 + ……+ ^4^3+^5^4+43^)/8 = + ^4y2 + + ^y4 + ^7y5 + ……+少 u + 仏+ )/8 = (^4^1 + ^y2 + + + ^y5 + ……+ ^:^3+72^4+^3^15)/8 = + + + + + ……+ 923^3+^3^4+^^^5)/8 ^13 =(^1 +^2 +^15^3 +^1^4+^5 + ……+ 如知 + 〜Α V 8 ^14 = fel4 + ^15^2 + + + + ……+ ^1^13+^:^14+^^15)/8 之15 =(仏5乃+仏少2 +《2少3 +%少4 +《4少5 +……+ ^2^3+^3^4+^^5)/8 擴散符號於使用 Μ系列時，pl=0、p2=l、p3 = 0、 p 4 = 0 、 p 5 = 1 、p 6 =1 、 p 7 = 0 、p 8 = 1 、 p 9 = 0 、 plO=l 、 p1 1 = 1、p 1 2 = 1、pl3 = l、pl4 = 0、p 1 5 =0 ； q1 = — 1、q2 =1、 q3= — 1、q4= — 1、q5 = l、q6=l、q7=— 1、q8=l、q9=— 1、q 1 0 = 1 ' qll = l、ql2 = l、ql3 = l、ql4=— 1、ql5=— 1。 如此，符號調變電路1 40上使用之擴散符號雖係M 系列，但符號逆調變電路1 4 1上所用之擴散符號則將Μ 系列之「〇」改爲「一 1」。如此則可將資料解調（逆調 變），又不至使其與前後之資料發生干涉。 -25- (22) 1274498 此時，接收後符號逆調變之資料列zl、z2、z3、Z4、 z5、…、zl3、zl4、zl5與傳送資料之資料列χ1、χ9、 χ 3 ' χ4、χ5、···、χ13、χ14、χ15 相寺。 如此，符號調變資料在不發生資料間干涉之情形下， 於接收電路被符號逆調變。對於OFDM傳送中其他的載波 訊號，亦進行相同的符號調變以及符號逆調變。於傳送電 路之全部載波訊號上使用同一擴散符號。同樣地，於接收 電路之全部載波訊號上，亦使用同一擴散符號。又，擴散 符號若就個別傳送裝置而使用其他系列之符號則更佳。 上述之例中，雖一度將符號調變之資料的長度設爲 15，但若爲7、15、31、63等2Ak-l之數，則可利用Μ系 列或黃金符號系列。使用符號調變技術，可使擴散符號不 同的傳送裝置所生雜音之影響較小，故即使電纜2 1與其 他傳送裝置之電纜鄰接，亦可有效除去鄰線串擾（Alien Cross-talk )等有害雜音。 【圖式簡單說明】 〔第1圖〕表示本發明之全雙工傳收訊電路之構造之 方塊圖。 〔第2圖〕表示本發明之傳送裝置之全體構造之方塊 圖。 〔第3圖〕表示本發明之傳送電路10之構造之方塊 圖。 〔第4圖〕表示本發明之倂合電路12之構造之電路 -26- (23) 1274498 圖。 〔第5圖〕表示本發明之調變電路32之構造之方塊 圖。 〔第6圖〕表示本發明之補償電路13之構造之方塊 圖。 〔第7圖〕表示依本發明之調變電路10，以OFDM 調變之訊號的波形之例之波形圖。 〔第8圖〕表示本發明之消除訊號產生電路之構造之 方塊圖。 〔第9圖〕表示本.發明之接收電路15之構造之方塊 圖。 〔第10圖〕表示本發明之解調電路90之構造之方塊 圖。 〔第11圖〕表示本發明之干涉歪斜補正電路91之構 造之方塊圖。 〔第12圖〕表示本發明之扭曲訊號除去電路之構造 之方塊圖。 〔第13圖〕表示本發明之時脈回復電路之構造之方 塊圖。 〔第1 4圖〕表示本發明之調整處理之內容之流程 圖。 〔第1 5圖〕表示本發明之接收電路之細部構造之方 塊圖。 〔第1 6圖〕表示本發明之第2實施例的傳送電路之 -27- (24) 1274498 構造之方塊圖。 〔第17圖〕表示本發明之第2實施例的接收電路之 構造之方塊圖。 〔第18圖〕表示本發明之積分電路108之構造之電 路圖以及波形圖。 【主要元件符號說明】 10 傳送電路 1 1增幅器 1 2倂合電路 2 1電纜 22對方裝置 13補償電路 17消除訊號產生電路 1 5接收電路 1 6時脈回復電路 1 8調整控制電路Yi = PlXl + Ρ2χ2 + P3X3 + P4X4 + PsX5 + ...... + corpse 13X13 + outer 4 VII 4 + A5X15 y2 = p2xx + p3x2 + p, x3 + p5x4 + p6x5 + ...... + A4x13 + A5x14 + Ah y3 = P3Xl + P4X2 + P5X3 + P6X4 + PlX5 + ...... + ^5X13 + + household 2'5 y4 = P4Xl + P$X2 + ΡβΧ3 + PlXA + + ...... + A 七 3 + household 2 especially 14 + 7 5 y5 = psxx + P6x2 + ρΊχ3 + p8x4 + p9x5 + ......+ household 2x13 + eve 3 seven 4 + p4x15 yi3 = PnX\ + PuX2 + P\5X3 + P\x4 + PlX5 + ......+ /1⁄21⁄2 + A'14 + A2X15 ^14 = P\4Xl + Pl5X2 + PlX3 + PlX4 + ΛΧ5 + ......+ ^15 = P\5X\ + P\X2 + PlX3 + P3X4 + PaX5 + ......+ Pl2X13 + Pl3X14 + This calculus is before OFDM multiplexing For this reason, it can be used as a low frequency and digital processing using DSP. The OFDM transmission is performed using the symbol-modulated -24-(21) 1274498 data obtained here. The received signal is demodulated by OFDM. In the output of the A/D converter 92 corresponding to the carrier, the received data columns yl, y2, y3, y4, y5.....yl3, yl4, yl5 are available. This data column is the same as the data column after the symbol of the data column of the data to be transmitted. The data column of the received data column symbol is inversely modulated, and is represented by zl, z2, z3, z4, z5..... z 1 3, z 1 4, z 1 5 , and the symbol is inversely modulated. The calculation is as shown in the following equation. A = (仏乃+分2少2 +~y3 + "4 less 4 cut 5 less 5 +...+ 1^+^14+^15)/8 = +^4^3 +^5^4 +^ 5 + ......+ ^4^3+^5^4+43^)/8 = + ^4y2 + + ^y4 + ^7y5 + ......+ less u + 仏+ )/8 = (^4^1 + ^y2 + + + ^y5 + ......+ ^:^3+72^4+^3^15)/8 = + + + + + ......+ 923^3+^3^4+^^^5) /8 ^13 =(^1 +^2 +^15^3 +^1^4+^5 + ......+ know + Α V 8 ^14 = fel4 + ^15^2 + + + + ...... + ^1^13+^:^14+^^15)/8 of 15 =(仏5是+仏少2 + "2 less 3 +% less 4 + "4 less 5 +... + ^2^3 +^3^4+^^5)/8 Diffusion symbol When using the Μ series, pl=0, p2=l, p3 = 0, p 4 = 0, p 5 = 1 , p 6 =1 , p 7 = 0, p 8 = 1 , p 9 = 0 , plO=l , p1 1 = 1, p 1 2 = 1, pl3 = l, pl4 = 0, p 1 5 =0 ; q1 = — 1, q2 =1, Q3= — 1, q4= — 1, q5 = l, q6=l, q7=— 1, q8=l, q9=— 1, q 1 0 = 1 ' qll = l, ql2 = l, ql3 = l, Ql4=— 1, ql5=— 1. Thus, although the diffusion symbol used in the symbol modulation circuit 140 is the M series, the diffusion symbol used on the symbol inverse modulation circuit 14 1 changes the "〇" of the series to "1". In this way, the data can be demodulated (reversely modulated) without interfering with the data before and after. -25- (22) 1274498 At this time, the data of the inverse sign of the symbol after reception is zl, z2, z3, Z4, z5, ..., zl3, zl4, zl5 and the data of the transmitted data χ 1, χ 9, χ 3 ' χ 4 Χ5,···,χ13,χ14,χ15 相寺. In this way, the symbol modulation data is inversely modulated by the symbol in the receiving circuit without interference between the data. For the other carrier signals in the OFDM transmission, the same symbol modulation and symbol inverse modulation are also performed. The same spread symbol is used on all carrier signals of the transmission circuit. Similarly, the same spread symbol is used on all carrier signals of the receiving circuit. Further, it is preferable that the diffusion symbol use other series of symbols for the individual transfer device. In the above example, although the length of the data of the symbol modulation is once set to 15, but the number of 2Ak-1 such as 7, 15, 31, 63, etc., the series of Μ or the symbol of gold can be used. By using the symbol modulation technology, the influence of the noise generated by the transmission device having different diffusion symbols can be made small, so that even if the cable 21 is adjacent to the cable of the other transmission device, the alien crosstalk (Alien Cross-talk) can be effectively removed. Noise. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1] is a block diagram showing the construction of a full duplex transmission and reception circuit of the present invention. Fig. 2 is a block diagram showing the entire configuration of a conveying apparatus of the present invention. [Fig. 3] is a block diagram showing the configuration of the transmission circuit 10 of the present invention. [Fig. 4] shows a circuit of the construction of the coupling circuit 12 of the present invention -26-(23) 1274498. [Fig. 5] is a block diagram showing the configuration of the modulation circuit 32 of the present invention. [Fig. 6] is a block diagram showing the construction of the compensation circuit 13 of the present invention. [Fig. 7] is a waveform diagram showing an example of a waveform of a signal modulated by OFDM according to the modulation circuit 10 of the present invention. [Fig. 8] is a block diagram showing the construction of the cancel signal generating circuit of the present invention. [Fig. 9] is a block diagram showing the configuration of the receiving circuit 15 of the present invention. Fig. 10 is a block diagram showing the construction of the demodulation circuit 90 of the present invention. [Fig. 11] is a block diagram showing the construction of the interference skew correction circuit 91 of the present invention. [Fig. 12] is a block diagram showing the construction of the distortion signal removing circuit of the present invention. [Fig. 13] A block diagram showing the construction of the clock recovery circuit of the present invention. [Fig. 14] is a flow chart showing the contents of the adjustment processing of the present invention. Fig. 15 is a block diagram showing the detailed structure of the receiving circuit of the present invention. [Fig. 16] Fig. 16 is a block diagram showing the configuration of the transmission circuit -27-(24) 1274498 of the second embodiment of the present invention. [Fig. 17] Fig. 17 is a block diagram showing the configuration of a receiving circuit of a second embodiment of the present invention. [Fig. 18] shows a circuit diagram and a waveform diagram of the construction of the integrating circuit 108 of the present invention. [Main component symbol description] 10 Transmission circuit 1 1 Amplifier 1 2 Coupling circuit 2 1 cable 22 counterpart device 13 Compensation circuit 17 Elimination signal generation circuit 1 5 Receive circuit 1 6 clock recovery circuit 1 8 adjustment control circuit