JP2000082961A - Analog pre-circuit in digital subscriber line communication system and its processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the constitution of an analog pre-function for a asynchronous digital subscriber line communication modem and to integrate it in a single integrated circuit. SOLUTION: An analogue pre-function 12 is integrated in a single integrated circuit and it contains a transmission side and a reception side. The transmission side contains an over sampler 44C and a digital filter 46C and they operate to improve the sampling rate of digital data. Consequently, down stream analog LPF 50C is realized by a comparatively simple low-order filter since a DA converter 48C operates by an over-sampling method. For reducing the complicated reception side analog LPF 58C, a digital filter 64C is contained in the down stream of an AD converter 62C. For conquering the influence of line attenuation to high frequency down stream transmission, a remote DSL modem contains an equalizer function boosting signal amplitude as the frequency becomes higher.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to the field of telecommunications systems, and more particularly to signal processing and interface circuits in a subscriber line modem.

[0002] The rapid exchange of digital information between remote computers is now almost an integral part of modern computing in many contexts, including business, educational and personal computer applications. It is anticipated that current and future applications of high speed data communications will sustain the demand for systems and services in this area. For example, video-on-demand (VOD) is one area that has promoted technology development for some time in the area of digital information exchange. Quite recently, the rapid growth in the use and popularity of the international Internet (hereinafter simply "Internet")
In particular, in achieving fairly high bit rates using existing infrastructure, there has been further motivation for research and preparation and development of systems aiming for advanced communication of information between remote computers.

One type of technology that arises from the above and evolving situations is referred to in the art as Digital Subscriber Line (DSL). DSL generally refers to PSTN technology that provides relatively high bandwidth over conventional telephone company copper wiring. DSL is further divided into several different categories of technology according to specific expected data rates, the type and length of the medium over which the data is communicated, and the manner in which the data to be communicated is encoded and decoded.

In each case, the DSL system can be thought of as a pair of communication modems, one of which is at a customer site, such as a home or office computer, and the other of which is a network. At the controller site, typically at the telephone company central office. Within the telephone company system, the modem is connected to communicate with one type of network, often referred to as a mains network, which connects devices such as routers or digital subscriber line access multiplexers (DSLAMs). Communicate with other communication paths via Through these devices, the mains network can also communicate further with dedicated information sources and the Internet.
As a result, information accessible via the mains network, such as Internet information, can also be communicated between the central office DSL modem and a customer site having its own compatible DSL modem.

[0005] Within this overall system, it is also expected that the data rates between DSL modems will be much higher than current voice modem rates. Current DSL systems being tested or planned range in speed from as low as 500 Kbps to 18 Mbps or more. According to certain DSL technologies, the data rate is asymmetric, so-called downstream communication, i.e. communication from the central office to the customer site, uses a significantly higher data rate than upstream communication from the customer site to the central office. Is done. Most DSL technologies also do not use the entire bandwidth of the twisted pair wire, but instead reserve a relatively low bandwidth for conventional voice communications (commonly referred to as "ordinary telephone service", POTS). As a result, voice and data communication can be performed simultaneously over the same line.

As further background, examples of DSL technology currently under development include high bit rate digital subscriber lines (HDS).
L), Single Line Digital Subscriber Line (SDSL) and Very High Data Rate Digital Subscriber Line (VDSL). H
DSL has a symmetric data rate and communicates at the same rate in both the upstream and downstream directions. Currently approved speed is 1.544Mbps
Modest bandwidth, but requires two copper twisted pairs. However, the effective working distance of HDSL is limited to some extent, ie, currently about 3.658 k
m (12,000 feet) or less, beyond which a signal repeater is required. SDS
L provides symmetric data rates comparable to HDSL, but achieves this with a single copper twisted pair. here,
A single copper twisted pair limits the effective range of an SDSL system to about 10,000 feet (3.048 km). Finally, VDSL is from 13 Mbps to 52 Mbps
s downstream and 1.5 Mbps to 2.
It has a much higher data transfer rate, such as 3Mbps upstream, but from 305m to 1.372k
m (1,000 feet to 4,500 feet).

The most advertised DSL technology currently under development, called Asymmetric Digital Subscriber Line or ADSL, corresponds to ANSI standard T1E1.413. AD
SL technology involves communication according to discrete multitone (DMT) modulation, and also includes frequency domain multiplexing (FDM). Other modulation techniques such as carrier-free amplitude / phase modulation (CAP) are also known in the art. In any case, according to the current state of the technology, ADSL is from 1.5 Mbps to 6 Mbps.
bps downstream (remote DSL from central office)
It is expected to communicate data over a single copper twisted pair at speeds (to the modem) and upstream speeds ranging from 16 kbps to 640 kbps. A specific example of ADSL technology is a 25 kHz to 1104 kHz downstream (from central office to remote) signal bandwidth and 2 kHz.
Utilizes an upstream (remote to central office) signal bandwidth of 5 kHz to 138 kHz. In this implementation, echo cancellation is particularly necessary with remote DSL modems because its transmission bandwidth is within the bandwidth of its received traffic. In any case, if the telephone company is only envisioning Internet access using ADSL technology, because ADSL technology can achieve these high bandwidths through existing twisted-pair infrastructures, Instead, consider providing remote LAN access services and VOD services using this approach.

Of course, in addition to performance considerations and the distance over which DSL communications can be carried by conventional twisted-pair infrastructure, the cost of modem hardware is also an important factor in selecting a communication technology. Therefore,
Low data rate technology has been developed for downstream data rates over 1 Mbps over existing twisted pair networks and for 56k modems, It is expected that high speed data communications will be performed at a cost comparable to conventional non-DSL modems, such as 34 modems and ISDN modems.

Due to the nature of DSL communications, for both central offices and remote subscribers, so-called mixed-signal circuits that handle both analog and digital signals are provided by DS.
Required in implementing L-modem. Conventional D
SL modem designs include a feature called "analog prefix". This feature includes digital-to-analog and analog-to-digital conversion, power amplification, and (low-pass,
Perform some amount of filtering (including band-pass and high-pass filtering). Because of the frequencies involved in DSL technology, which range from tens of kHz to MHz, and because of the large dynamic range required to accommodate wide variations in subscriber loop length and quality, The filter operation associated with a conventional DSL modem is very complicated. As a result, typical analog pre-circuits have heretofore been subject to manufacturing variations.
It has been realized by discrete analog circuits that use narrow tolerance components to eliminate uring variations. The complex filter characteristics in these traditional modems
In particular, when preparing a filter having a steep band rejection requirement of the DSL standard, the filter characteristic is digital /
Considering that the process variations in the analog converter must be followed, it prevents these analog filters from being effectively integrated into an integrated circuit. In particular, the integration of this analog pre-circuit into a mixed signal integrated circuit is expected to require significant trimming of the analog filter bandwidth to compensate for process variations.

[0010]

Accordingly, it is an object of the present invention to provide an integrated circuit having an analog prefix function in a DSL modem system.

It is a further object of the present invention to provide such an integrated circuit which minimizes the complexity of the analog filter operation performed by the analog prefix function.

It is a further object of the present invention to provide such an integrated circuit that utilizes finite impulse response (FIR) digital filtering to minimize delay distortion.

It is a further object of the present invention to provide such an integrated circuit that minimizes filter bandwidth trimming.

It is a further object of the present invention to provide such an integrated circuit that is well suited for DSL modems that perform echo cancellation.

It is a further object of the present invention to provide such an integrated circuit in which the digital filter coefficients are programmable.

[0016] Other objects and advantages of the present invention will become apparent to those skilled in the art when the following description is taken in conjunction with the drawings.

[0017]

SUMMARY OF THE INVENTION The present invention can also be implemented in an analog pre-integrated circuit for a digital subscriber line (DSL) modem, in which analog input / output signals other than high voltage interface functions. Processing functions are integrated. Analog pre-integrated circuit, remote or central office DS
It is effective for both L modems. In the analog pre-circuit of the present invention, the finite impulse response type digital filter is preferably applied to the transmission signal before the digital / analog conversion or to the received signal after the analog / digital conversion. Reduce operational complexity. The coefficients of these filters may be preset with a relatively small number of non-zero digits, or programmed if desired. This digital filter operation allows the analog filter to be relatively simple and allows its integration into an analog pre-integrated circuit.

[0018]

FIG. 1 shows a telecommunications system,
Thus, the present invention can be realized. This system will be described. The system of FIG. 1 illustrates the proposed Digital Subscriber Line (DSL) application of the present invention, and particularly that using asymmetric DSL (ADSL) technology. That the present invention also provides advantages for other system applications,
Of course, as expected. However, given the stringent requirements imposed by the modem DSL standard, especially with respect to filter performance and bit rate, the present invention provides a D
It is expected to be particularly well suited for applications associated with SL technology.

FIG. 1 illustrates a typical system implementation of DSL services, in which a number of remote subscribers interface with a telephone system central office. In this example, a user in a home or office environment operates a remote computer system R, such as a personal computer or workstation or, alternatively, a video-on-demand (VOD) context entertainment device. Each of the remote computer systems R serves as a remote source and a remote destination of the communication data, and the communication data is a sentence, a graphic, a moving image, a voice, or the like. Each remote system R is associated with a remote DSL modem 15 via which the remote system R communicates with a conventional twisted-pair telephone facility TW.
It communicates with the central office DSL modem 8 through P. POTS
One or more telephones (not shown) may be connected to each twisted pair facility TWP such that voice communications are alternatively or additionally communicated through the twisted pair facility TWP.

As shown in FIG. 1, each of the twisted pair facilities TWP is received by a central office DSL modem 8. This modem is expected to be at the local or long distance telephone service provider's central office. In this example, the central office D
SL modem 8 is capable of receiving a number of twisted-pair line facilities TWP (only two of which are shown in this example). The central office DSL modem 8 communicates data between twisted pair facilities TWP, and therefore between the remote system R and a host computer (not shown in FIG. 1). The host computer acts as a source or destination of data or a relay gateway to the Internet or a network such as a dedicated "dial-call" content provider or provider network. Of course, the central office will typically also include a switchgear for routing a call, such as a call originated by the remote system R (or the associated telephone), through the twisted pair facility TWP. As mentioned above, the central office modem 8 is probably connected to the mains network. The mains network communicates with other communication paths via devices such as routers or digital subscriber line access multiplexers (DSLAMs). In applications where the POTS service overlays ADSL data traffic, such devices separate the POTS traffic from the data traffic, route and forward the POTS traffic to a conventional telephone network (PSTN), and transmit the data over a wide area. It may also include some type of "splitter" for routing and forwarding to the network (WAN).

In the specific example of FIG. 1, the DSL technology is of the asymmetric type (ie, ADSL), with a signal bandwidth of 25 kHz to 1,104 kHz from the central office DSL modem 8 to the remote DSL modem 15 (ie, Downstream) running traffic and 25kHz to 13
It has traffic traveling from remote DSL modem 15 to central office DSL modem 8 (ie, upstream) with a signal bandwidth of 8 kHz. Of course, as will be apparent to one of ordinary skill in the art upon reviewing this specification, the present invention may be adapted to other ADSL configurations and other configurations by appropriately adjusting the particulars of the filters and other functions. It can also be implemented to provide benefits to the DSL configuration.

In the example of FIG. 1, the remote DSL modem 15
Each is configured as a plurality of functions. These features
In this exemplary embodiment of the invention, it corresponds approximately to an individual integrated circuit. Of course, it should be understood that the particular integrated circuit or "chip" boundary between these various functions may vary between implementations, and the exemplary implementation shown in FIG. 1 is merely exemplary. In this example, each of the remote DSL modems 15 includes a host interface 7, which interfaces digital transceiver function 13 with its associated remote system R. Host interface 7
Is of a conventional structure for such an interface function, and of course, the type of bus to which the DSL modem 15 is connected (eg, serial bus, PCI bus, ISA
Bus). An example of a host interface 7 is the TNETD2100 digital serial bus interface circuit available from Texas Instruments.

According to this embodiment of the invention, the remote DS
The digital transceiver function 13 of the L modem 15
A programmable device that performs the digital processing operations required for both transmitting and receiving data payloads.
These operations, which are described in more detail below, include the ability to format digital data (e.g., into packets or frames) from the host computer, encode the data into appropriate subchannels for transmission, Includes the ability to perform an inverse Fourier transform (IFFT) to transform the coded data into a time domain signal. On the receiving side,
Digital transceiver function 13 performs not only the reverse of these functions, but also echo cancellation processing. In particular, at the data rates discussed above, the digital data processing capacity and processing capability of digital transceiver function 13 is preferably of a high level. An example of a suitable architecture for use as digital transceiver function 13 is a digital signal processor such as the TMS320C6x, available from Texas Instruments.

FIG. 2 illustrates the signal flow through the digital transceiver function 13 and the digital functions performed by this function according to the preferred embodiment of the present invention. This will be described. As shown in FIG. 2, the digital transceiver function 13 includes a transmitting side DTx and a receiving side DR.
x through which signals are transmitted from the remote system R to the twisted pair facility TWP and received from the twisted pair facility TWP to the remote system R. As noted above, digital transceiver function 13 is preferably a programmable processor according to this embodiment of the present invention, and the block diagram of FIG.
It corresponds to the function performed by function 13 rather than specific hardware components within transceiver function 13. Digital transceiver function 13 shown in FIG.
All of the operations described above are performed in the digital domain.

On the transmitting side DTx, the signal received by the digital transceiver function 13 from the PC interface 7 is first supplied to the framing and coding process 20R. In this embodiment of the invention, these received signals take the form of digital words to be communicated over the twisted pair facility TWP. The framing and coding process 20R generally organizes these data words into packets within a physical layer frame, which modulates a number of DMT subcarriers or subchannels. This configuration is accomplished by formatting each packet to include a data header field for synchronization before the data and a cyclic redundancy code (CRC) following the data field to enable error detection. It is also performed by inserting "dummy" data to maintain modem synchronization, to check the signal-to-noise ratios of the various sub-channels, and to ensure that no bad sub-channels are used. . The encoding of the packetized data is then performed in process 20R. For example, according to the DMT approach,
The digital data is represented by an amplitude-phase constellation
n) is coded to correspond to a certain point. DMT
A discussion of data encoding can also be found in the following literature: That is, Shioffi, "Introduction to Multicarrier", a personal lecture to the IEEE Standard Committee T1 (1991) (Cioffi, "A Multicarrier Prime
r ”, Tutorial submitted to Standards Committee T1
of IEEE (1991)), Shaw et al., "Discrete Multitone Transceiver System Applied to HDSL", Journal on Selected Areas in Communications, Vol. 9, No. 6 (IEEE, 1991) August), pages 895-908 (Chow, et al., "A Disc
rete Multitone Transceiver system for HDSL Applica
tions ”, Journal on Selected Areas in Communicatio
ns, Vol. 9, No. 6 (IEEE, Aug. 1991), pp. 895-90
8) and Bingham, "Multicarrier Modulation for Data Transmission: The Idea of Time Coming," IEEE Magazine (199
May 2005), pp. 5-14 (Bingham, "Multicarrier Mo
dulation for Data Transmission: An IdeaWhose Time
has Come ”, IEEE Communications Magazine (May, 199
0), pp. 5-14)), all of which are incorporated herein by reference. As is known in the art, a DMT associates each possible digital value (which depends on bit loading for a particular sub-channel or sub-carrier) with a combination of amplitude and phase. For example, if a sub-carrier is assigned a bit loading of four, that carrier constellation includes 16 possible amplitude-phase combinations, each of which is one of 16 possible digital values. Related. If the sub-carriers are assigned eight bit loadings, there are 256 amplitude-phase combinations in the constellation, each of these combinations representing 256 possible digital values represented by eight bits. Associated with one. To facilitate coding, the small constellation is preferably a subset of the maximum (8-bit) constellation. However, the sub-carriers in the less-populated configuration have less power than the sub-carriers in the higher-density configuration, so that the gain scaling of the sub-carriers amplifies the sub-carriers in the lower-density configuration. Is preferred. Still further
Preferably, the subcarriers are coded as a group to increase the efficiency of operation when the digital transceiver function 13 is implemented via a pipelined digital processor (DSP). This grouping confines multiple subcarriers to 16-bit words such that each subcarrier is confined within a word boundary. Certain sub-carriers have their bit loading reduced by one or several bits as necessary to maintain this grouping. It is also preferable to pre-group the sub-carriers as part of an initialization process that generates a pre-stored macro of the sub-carrier grouping, and Eliminates the need for conditional call operations and conditional branch operations.

In this example, the ordering of the data according to the subcarriers and the unpacking of the data is performed by the process 20R.
And, preferably, together with the mapping of data into constellation points within each sub-carrier through the use of a look-up table. Various sub-carrier amplitude scaling is also performed in process 20R. Process 20R
Is a sequence of amplitude and phase values (encoded by constellation), and the order in that sequence corresponds to the frequency of the associated subcarrier, so the grouping and coding performed in process 20R is: Each of the data words received from interface 7 is effectively converted to the frequency domain. Then, if appropriate, clipping control can be added by simply monitoring the overflow flag in the status register of digital transceiver function 13. Upon detecting an overflow, certain bits (operating and sustaining bits (referred to as OAM bits)) are set and a pilot tone is added to allow the transmitter to repair the clipped frame over the next two frames. Show that there is. In this example, these two frames will be combined and decoded by the receiving modem 8.

Next, an IFFT process 22R is performed on the coded data received from the framing and coding process 20R to generate a time domain signal corresponding to the coded subcarrier. In this example, the IFFT
Process 22R generates 32 tones (for relatively low frequency upstream signals) for this communication. I
Following the FFT process 22R, a process 24R adds a cyclic prefix to the interframe portion of the column as guard time, which allows the time domain equalizer filter in the central office DSL modem 8 to have an appropriate impulse response.
The coded time domain digital data with the cyclic prefix is provided to the analog prefix function 11 in the form of a bitstream via an analog prefix function (AFE) interface process 26R.

At the receiving end DRx, the digital transceiver function 13 receives a digital data bit stream from the analog prefix function 11 via the analog prefix function interface process 30R. An automatic gain control (AGC) process 23R maintains proper gain control within analog pre-function 11 in a conventional manner. In accordance with this exemplary implementation, a time domain equalizer (TEQ) process 31R is provided within digital transceiver function 13. This may be present and as described in more detail below, in particular, the twisted pair facility TWP
This is to remove the intersymbol interference (ISI) introduced by the analog filter in the analog pre-function 11 that separates the upstream and downstream through. The time domain equalizer process 31R according to an embodiment of the present invention is a conventional finite impulse response (FIR) filter implemented via software routines performed by a digital signal processor (DSP). Since the coefficients of the time domain equalizer (TEQ) process 31R depend on the response of the twisted pair facility TWP, these coefficients are determined during initialization.

Following the intersymbol interference filter operation of the time domain equalizer process 31R, the digital transceiver function 13 applies the process 32R to the bitstream to remove the cyclic prefix. A Fast Fourier Transform (FFT) process 33R converts the 128 tones used in the high frequency downstream transmission received by the remote DSL modem 15
Perform a 56-point FFT. Clipping control process 3
4R recovers any words separated during transmission due to overflow, as described above, and the resulting frequency domain sequence is provided to a frequency equalizer and phase compensation process 35R. A frequency domain equalizer (EEQ) and phase compensation process 35R flattens the signal spectrum of the received signal and compensates for phase distortion. A decoding and deframing process 40R performs the reverse of the transmission order, which includes bit demapping and gain scaling, a tone reordering and packing process, and a deframing and flow control. And this is supplied to the remote system R via the host interface 7.

Referring back to FIG. 1 and shown in FIG. 2, the digital transceiver function 13 is bi-directionally connected to the analog pre-function 11 according to the preferred embodiment of the present invention. In this exemplary embodiment of the invention, each analog prefix 11 is a mixed signal (i.e., with both digital and analog operation) integrated circuit, which includes a DSL other than those with high voltages. Prepare all loop interface components necessary for communication. In this regard, the analog prefix function 11 within each of the remote DSL modems 15 may be configured in a manner described in further detail below.
Performs both transmission and reception interface functions.

The analog prefix 11 in each of the remote DSL modems 15 interfaces bi-directionally with a line driver 17 which drives and receives ADSL signals on the twisted pair line facility TWP. And receiver. An example of a line driver integrated circuit suitable for use in accordance with a preferred embodiment of the present invention is Texas Texas Instruments.
THS6002 commercially available from Instruments
It is a line driver. The line driver 17 in the remote DSL modem 15 is a 4-wire to 2-wire "hybrid" integrated circuit 19
Circuit 19 is connected to the line driver 1 in a full-duplex manner.
7 is converted into a two-wire configuration of the twisted pair line facility TWP.

At the central office, the central office DSL modem 8 includes a host interface 9. This interface connects the modem 8 to a host computer (not shown).
The host interface 9 is, as described above, a TNETD available from Texas Instruments.
It can also be implemented by a conventional circuit such as a 2100 digital serial bus interface circuit. As mentioned above, the host computer comprises a splitter for separating POST from data traffic and a central office DSL.
A conventional telephone network (PSTN) to interface the modem 8 and therefore be appropriate for the service provided.
And a wide area network (WAN). Central office DSL modem 8 includes a digital transceiver function 10, which connects to a number of analog prefix functions (AFEs) 12, as shown in FIG.

The digital transceiver function 10 is a digital transceiver function 1 in the remote DSL modem 15.
3 and perform similar processing,
As will be described in more detail below, there are certain functional differences that result from differences in the frequencies of the received traffic and the transmitted traffic between the two functions. As noted above, the digital transceiver function 10 is preferably a TMS32, commercially available from Texas Instruments.
It is implemented as a high performance digital signal processor such as OC6x.

FIG. 3 shows the signal flow and function of the digital transceiver function 10 in the central office DSL modem 8. The same reference numbers used in FIG.
The suffix C) indicates a function equivalent to that described above for the digital transceiver function 13 in the remote DSL modem 15.

In summary, at the transmitting side DTx, the signal received by the digital transceiver function 10 from the host interface 9 is first provided to a framing and coding process 20C, which codes the data in frame format, With this data, in embodiments of the present invention, the DMT sub-carrier or sub-channel is modulated, followed by scaling and clipping control, as described below. An IFFT process 22C converts the coded data into a time domain signal corresponding to a coded subcarrier, and a process 24C adds a cyclic prefix to the interframe portion of the column. This coded time-domain digital data with a cyclic prefix is
Next, the analog prefix function interface process 2
Via 6C, it is supplied to the analog prefix function 12 in the form of a bit stream.

At the receiving end DRx, the digital transceiver function 10 receives a digital bit stream from the analog prefix function 12 via the analog prefix function data interface function 30C. digital·
As described above for transceiver function 13, AGC
Process 23C is included in digital transceiver function 10. Time domain equalizer (TEQ) process 31
C uses a finite impulse response (FIR) filter to remove intersymbol interference (ISI), and then process 32C removes the cyclic prefix from the bitstream. As described above, the FFT process 33C converts the time domain signal into a digital frequency domain representation, and the clipping control process 34C recovers words separated due to overflow. A frequency domain equalizer and phase compensation process 35C flattens the signal spectrum of the received train and compensates for phase distortion. Finally, the decoding and deframing process 40C performs the reverse of the transmission order, which includes bit demapping and gain scaling, tone reordering and packing processes, deframing and flow control, and Which is supplied to the host system via the host interface 9.

As shown in FIG. 1, the central office DSL modem 8 also preferably includes a number of analog prefix functions 12, arranged in a master / slave fashion between each other. Each of these communicates with one of the twisted-pair line facilities TWP, and thus communicates with one of the remote DSL modems 15 for a DSL session, as shown.

Many of the operations performed by the analog prefix function 12 in the central office DSL modem 8 are similar to those performed by the analog prefix function 11 in the remote DSL modem 15, but in ADSL technology, In particular, the difference in the frequency of the received traffic at each location (as described above, the received traffic of the central office DSL modem 8 is
(At a frequency substantially lower than the received traffic of the SL modem 15), there is some difference between them. As will be described in more detail below with respect to the analog prefix function 11 in the remote DSL modem 15, frequency dependent attenuation across the twisted pair line facility TWP particularly affects high frequency traffic received by the remote DSL modem 15. This attenuation is controlled by the analog pre-function 11 of the remote DSL modem 15 in accordance with a preferred embodiment of the present invention.
Is taken into account by the equalizer function contained within. In addition, since the transmit traffic of the central office DSL modem 8 is typically at a much higher frequency than its receive traffic, analog echo cancellation can be performed by the modem 8.
It is not expected to be required for the analog prefix function 12 within. Of course, if an echo cancellation function is desired, it may be provided in the analog prefix function 12. In any case,
These functional differences are reflected in the hardware of the analog prefix functions 11 and 12.

Each of the analog prefix functions 12 in the central office DSL modem 8 communicates with an associated line driver 14.
This driver may be the same line driver as described above for the remote DSL modem 15. Line driver 14
Each has its modem associated with a twisted pair line facility T
Related 4-wire to interface with WP-
The two-wire hybrid 16 is bidirectionally coupled.

The exemplary system shown in FIG. 1 is well suited for DSL communications, especially for ADSL communications where the upstream and downstream bandwidths are different from one another, and takes into account the strict requirements of this technology. including.
In particular, for example, as advocated in the T1E1.413 standard, analog signal processing constraints presented by DSL communication require high performance filter operation, which has previously required discrete realization of analog pre-functions. By way of illustration, the bandwidth of ADSL communications is very wide, in an exemplary embodiment the downstream (from central office to remote) signal bandwidth is 25 kHz to 1,104 kHz, and the upstream (remote to central office) signal is It is from 25 kHz to 138 kHz. In addition, the subscriber loops vary widely in length and quality, so that the ADSL analog pre-function will have a very large dynamic range (as large as possible) to accommodate as many of the potential loop populations as possible. (For example, about 100 dB to 102 dB). Overlaying DSL data communications with POTS communications using ring signals above 100V requires D
Requesting that the SL receiver must include a wide-pass filter capable of tolerating these high voltages;
This further complicates the analog processing.

In accordance with the preferred embodiment of the present invention, as described above, the analog pre-functions 11, 12 are implemented by an integrated circuit that performs all analog loop functions that are not exposed to high voltages (a wide variety of components). It eliminates the need for complex analog filter operation (which is not suitable for integration due to the need for trimming), but is implemented in a way that meets these requirements.

FIG. 4 shows the structure of the analog prefix function 12 in the central office DSL modem 8 according to a preferred embodiment of the present invention. This will be described in detail. As described above, this structure allows the analog pre-function 12 to be integrated into a single integrated circuit, which adds less cost, improved system reliability and improved telecommunications implemented by the system of FIG. It offers significant advantages including component matching. The integrated circuit of the analog prefix function 12 is of the so-called "mixed signal" type, which allows for performing both digital and analog processing. Of course, the additional scale of integration may also apply to the analog pre-function 12 as described herein with either the digital transceiver function 10 or the line driver 14 or both, as appropriate to the available manufacturing technology. Again, this can be achieved by integration.

The analog prefix function 12 includes a transmitter and a receiver, similar to the digital transceiver function 10 described above. In this embodiment of the invention, the sender and receiver share an interface and control function 42C through which the analog pre-function 12
Communicates with the digital transceiver function 10. The interface and control function 42C includes a parallel digital interface, over which digital words transmitted by the central office DSL modem 8 are received by the analog prefix function 12, through which
Data received from the twisted pair facility TWP and processed by the analog prefix function 12 is communicated to the digital transceiver function 10 as a digital word.
In accordance with a preferred embodiment of the present invention, the parallel interface is a 16-bit parallel interface, and has an edge-triggered read strobe input and Has a write strobe input. In addition, interface and control functions 42C
Includes a number of registers for storing control words, which bypass or operate (as described below) various programmable amplifier gain values, various filter blocks and functions. In the case of switch control to enable and analog pre-function 12, analog pre-function 1 such as switch control for input impedance matching at the receiving end (described below and in more detail).
2 sets the status of various functions.

Interface and control function 42C also includes a suitable signal interface for receiving and providing control information from digital transceiver function 10. In this embodiment of the invention, the serial port SP is:
As described below, it is provided for receiving control information such as used to set the frequency of the clock signal. Conventional scanning tests, such as according to the JTAG standard, are also preferably performed via the interface and control functions 42C.

The clock circuit 66C has the analog pre-function 1
2 is shared by the transmitting side and the receiving side, and performs corresponding clock control for their synchronous operation. In accordance with a preferred embodiment of the present invention, clock circuit 66C generates an internal (and external, if desired) clock signal based on an external voltage controlled crystal oscillator (VCXO) 65X. In the analog prefix function 12, a digital / analog (DA) converter 63C is provided, which (in particular via an update signal supplied to the serial port SP in this function).
In response to the control signal generated by the interface and control function 42C, an analog signal is generated, which is provided to and therefore controls the voltage controlled crystal oscillator 65X. The D / A converter 63C is, in the preferred embodiment, a 12-bit serial D / A converter, which produces a fine resolution suitable for high frequency (eg, 35.328 MHz) VCXO65X.

A reference voltage source 68C, preferably a stable reference voltage circuit such as a bandgap reference voltage, is also shared by the transmitting and receiving sides of the analog pre-function 12 to provide digital / analog conversion operation and analog / digital conversion. Not only operation, but also other components of the analog pre-function 12 may be implemented by conventional circuitry to establish the required reference voltage levels used.
Other circuits used in the operation of the analog prefix function 12 and including standard integrated circuit functions such as power distribution and regulation, general purpose port communication, etc., can of course be included in this analog prefix function, but this description Not shown for simplicity purposes. The analog pre-function 12 also includes an oversampling register 44C, as shown in FIG. 4, which controls the transmission and reception of the analog pre-function 12 in implementing the digital filtering operation described below. It includes one or more register stages that may be used on both sides.

Referring to the transmitter side of the analog pre-function 12, a digital filter 46C receives the digital data words from the oversampling register 44C and applies a digital filter to these digital data words prior to analog / digital conversion. Perform the operation. FIG. 5 shows the data flow through a digital filter 46C combined with an oversampling register 44C for an exemplary implementation of the preferred embodiment of the present invention. This will be described in detail.

As shown in FIG. 5, the analog prefix function 1
The digital filter operation process performed by 2 includes a number of options. These options are
Selectable by switches S1 to S4 depending on the frequency and characteristics of the digital data provided by digital transceiver function 10. Interpolation filter process 70 doubles the sampling rate to provide an oversampled digital-to-analog conversion downstream. In this exemplary implementation, simply the oversampling register 44
The sampling rate is increased from 2,208 kHz to 4,416 kHz by loading one of Cs alternately as follows. That is, the zero-valued sample is loaded between each input sample value, and the output of the register 44C is sampled at twice the speed of loading the actual input sample into the oversampling register 44C. Inserting the zeroed samples rather than performing the interpolation filter process 70 is by simply sampling each loaded input sample value twice, otherwise cos which may result from oversampling. It provides the advantage of removing [πf / f _c] attenuation. Instead, cos [πf /
f _c ] If computational power to compensate for the decay is available,
It is expected that this can be compensated for by the IFFT process 22C in the digital transceiver function 10.

With or without bypassing the interpolation filter process 70, a digital low-pass filter 71 is then applied to the incoming digital sample input value. Digital low pass filter 71 is provided to compensate for gain loss caused by zero insertion oversampling of process 70. Further, if the interpolation filter process 70 is performed by inserting zero-valued samples, cos [πf / f _c] attenuation is not performed. Digital low-pass filter 71 provides the desired power spectral density (ps) expected to be implemented for DSL communications.
q) Probably needed to achieve roll-off specification. Regarding the gain loss associated with the interpolation filter process 70, the digital low pass filter 71 preferably provides a 6 dB gain if not bypassing the interpolation filter process 70, but closes switch S1 and switches S3. If the filter process 70 is bypassed by opening, it will provide 0 dB gain.

According to a preferred embodiment of the present invention, the digital low-pass filter 71 is a 32-tap finite impulse response (FIR) low-pass filter that applies symmetric coefficient tap weights (for zero group delay distortion). Have. In a preferred implementation, the b (ie, feed forward) coefficient b
₀ ~b ₃₂ is as follows.

[0051]

(Equation 1)

The digital low-pass filter 71 provides an appropriate in-band power spectral density in the 1,104 kHz to 2,208 kHz band according to the current TIE 1.413 standard.

Next, a digital high pass filter 72 may be performed by the analog pre-function 12 as part of the digital filter 46C of FIG. The digital high-pass filter 72 is preferably a first-order high-pass filter, for example, an infinite impulse response (II
R) The filter has a −3 dB breakpoint frequency of 10.7 kHz implemented via conventional digital filter design techniques. In an exemplary implementation, the total ripple resulting from filter 72 is from 25 kHz to 1,104 kHz.
Is approximately 0.55 dB over a bandwidth of
It varies from 1.7 μs at 5 kHz to 1.7 ns at 1,104 kHz. Filter 72, when used in combination with a central office POTS splitter,
Satisfies the POTS band interference specification of 1E1.413 standard.

Interpolation filter process 74 is used to perform one or more oversampling registers 44C
Is another process that doubles the sampling rate, again by inserting nulled samples between each actual input sample. In the case of the interpolation filter process 74, the oversampling register 44C
Is loaded at 4,416 kHz, and its output is sampled at 8,832 kHz and the process 7
Produces a transfer function similar to that shown above for 0,
It is by following a different frequency f _c. As a result of the interpolation filter processes 70, 74, the digital-to-analog conversion to be performed will be performed at the oversampling rate, ie, eight times the signal bandwidth, and as described below, the downstream analog filter Reduce operational complexity.

Next, a digital low-pass filter process 76 is applied to the oversampled output of the interpolation filter process 74 to place a bandwidth limit on the digital data and reduce the complexity of the downstream analog filter operation. Also relax. In accordance with a preferred embodiment of the present invention, a digital low pass filter process 76 is implemented via a finite impulse response with symmetric tap weights, which minimizes overall delay distortion through the analog pre-function 12. A particularly advantageous implementation of the digital low pass filter process 76 is a seven tap and one tap.
Using four non-zero bits, this allows the multiplication to be easily performed with a few digit shift and add circuits in the analog pre-function 12. In this example, the tap weights are set as follows.

[0056]

(Equation 2)

According to a preferred embodiment of the present invention, in particular T
To implement a known standard such as the 1E1.413 standard, these two power tap weighting factors are preferably
Hardwired within the analog prefix function 12. Alternatively, analog pre-function 12 may include registers or other addressable locations, particularly considering the speed at which telecommunications standards may change over time, including the number of taps and taps. The weighting factor may be programmable. The output of the digital low-pass filter process 76 is preferably multiplied by the value (2-1 / 64) so that its gain does not exceed 6 dB at any frequency. The result of the digital low pass filter process 76 is then applied to the D / A converter 48 as shown in FIG.
C.

If a digital high pass filter 72 is used, this filter and the digital low pass filter process 76 result in a downstream
The complexity of analog filter operation is greatly reduced from that required by the current DSL standard. The stopband requirement for analog signals is the digital low pass filter 7
2. Although not modified by the interpolation filter process 74, in this embodiment the transient band characteristics are greatly relaxed so that no additional attenuation is required at 1.5 MHz, and -4 dB attenuation is required at 3 MHz. It will only be. The amount of filtering is relatively easily implemented with simple analog filtering, as described below.

The states of the switches S1 to S4 are as follows.
Depending on the frequency of the digital output provided by digital transceiver function 10, in this embodiment of the present invention will be determined by the control signal from digital transceiver function 10. For example, if the output of digital transceiver function 10 is 2,208 k
Hz, switches S3 and S4 will be closed and switches S1 and S2 will be open, so that both interpolation filter processes 70, 74 and also digital high-pass filter 72
Will be applied to the data. Alternatively, if the output of digital transceiver function 10 is already 4,41
If at 6 kHz, switch S1 is closed and switch S1 is closed.
3 is opened and switches S2 and S4 are connected to the high-pass filter 71.
Will open or close depending on whether it is needed. This gives a considerable degree of flexibility to the implementation of the analog prefix function 12.

Referring again to FIG. 4, the filtered digital data is provided to DA converter 48C. FIG. 6 illustrates a DA converter 48C according to a preferred embodiment of the present invention.
An example of the structure of FIG. DA according to a preferred embodiment of the present invention
Converter 48C is a 14-bit current steering architecture D / A converter that operates at 4X oversampling for a conversion rate of 8,832 kHz. According to a preferred embodiment of the present invention, the DA converter 48C comprises:
Two time interleaved 7-bit fine sub DA
7-bit coarse MSB sub D / A converter array 7 combined with LSB sub D / A converter array 80 including a converter
8 is realized. The coarse MSB sub-DA converter array 78 comprises a 128 PMOS cascode current source, in combination with which the two fine sub-DA converters in the LSB sub-DA converter array 80 provide two additional calibrated PMOS current sources. Form a cascode. All of these sub-DA converters utilize a common centroid layout topology.

According to modem manufacturing techniques at present, it is expected that process control will be sufficient to guarantee the required linearity of the LSB to DA converter, but not to the MSB to DA converter. The current sources of the MSB sub D / A converter array 78 and the LSB sub D / A converter array 80 are the calibration circuit 8
5 and is continuously calibrated via calibration logic 84. This calibration is performed at a rate that is in the unused portion of the frequency spectrum between 4 kHz and 25 kHz, eg, 4.190 kHz, while avoiding the instability caused by spurious tones at that calibration frequency. , To compensate for estimation errors due to charge leakage from the calibrated PMOS gate in each current source. This calibration technique is described in DWJ Gronebeld et al., “Self-calibration technique of monolithic high-resolution DA converter”, Solid State Circuit Magazine, Volume SC-24 (IEEE, December 1989), 1517.
-1522 (DWJ Groeneveld et al., “A Self-
Calibration Technique for Monolithic High Resolu
tion D / A Converters ”, J. Solid State Circ., Vol.S
C-24 (IEEE, Dec. 1989), pp. 1517-1522). This calibration is preferably done linearly up to the full 14-bit resolution of the D / A converter 48C, but to be linear up to 7-bit resolution, the 7-bit sub-D
Only an A-converter is needed.

The DA converter 48C includes a current output switch 82
These switches switch the current sources of the arrays 78, 80 either to an amplifier 88 (D / A converter output) or to a calibration circuit 85. The two fine sub D / A converters in the LSB sub D / A converter array 80 form two additional calibrated PMOS cascodes, with one sub D / A cascode being switched into the calibration circuit 85 while the other. Are time-interleaved such that the sub-D / A converter is connected to the amplifier 88 on the D / A converter output. Further, a spare MS for the MSB sub DA converter array 78
B current source and both sub D / A converters in LSB sub D / A converter array 80 are “held” by current output switch 82
State, in which case no current is switched to amplifier 88 or calibration circuit 85.

A binary-thermometer decoder 85 performs thermometer decoding for the coarse sub D / A converter in the array 78. 7-bit fine sub D / A converter in array 80 uses a combination of 5-bit thermometer and 2-bit binary decoding for 5-2 segmented decoding for chip area reduction purposes I do.

The output current from arrays 78 and 80 is an integer multiple of the reference current generated in bias and reference current circuit 86. The reference current circuit 86 converts the precise reference bandgap voltage to a reference current using an amplifier in unity gain feedback connection having an output connected to a resistor. A connection made to complete the feedback loop around this reference amplifier is digitally selectable with 16 taps on the reference resistor. The digitally trimmed resistors in the reference current circuit 86 have a selectable ± 8% range at 1% intervals. Further, this reference resistor is preferably matched with the feedback resistor in the amplifier 88 because of the process margin in order to convert the D / A converter output current to the output voltage via resistive feedback. Can be This matching causes the output voltage of the D / A converter 48C to be the ratio of the resistors present in the amplifier 88 and the reference current circuit 86, so that the absolute value of these resistors in the output voltage of the D / A converter 48C. Remove dependencies on values to first order. The remaining error mechanisms include the offset voltage of amplifier 88 and the inherent offset current between the reference current and the calibration current. These residual offset errors contribute to the full scale D / A converter gain error, and reduce the gain of the D / A converter 48C to its desired value of one.
Requires ± 8% trim width on reference resistor to trim to within%.

Because of this structure of the DA converter 48C, its output waveform is a staircase (zero order holding type). Therefore, the power spectral density of the output of the DA converter 48C (p
sd) is effectively modulated by the following frequency response:

[0066]

(Equation 3)

[0067] In this case, as described above, the sampling frequency f _c is 8,832KHz. This modulation is
The 1,104 kHz passband is not noticeably distorted. If desired, this distortion is pre-compensated with digital transceiver function 10 during IFFT process 22C. In any case, the power spectral density modulation applied to the output of A / D converter 48C performs some of the stopband rejection that would otherwise require downstream analog filter operation, and therefore Reduce the complexity of analog filters.

As shown in FIG. 4, the analog output of the DA converter 48C is supplied to an analog low-pass filter 50C. Analog low-pass filter 50C according to a preferred embodiment of the present invention is a third-order Chebyshev continuous-time filter, implemented in accordance with the prior art, with the associated ripple preferably ± 0.3 at a nominal 1.325 MHz passband.
It is less than 5 dB. This relatively simple analog filter is enabled to the extent of the digital filter operation previously performed by the filter 46C in the filter processes 72, 76 discussed above.

Depending on the specific power spectral density specifications of the operative DSL standard, the analog low-pass filter 50C may or may not be trimmable to meet these specifications over the estimated process variation. You may. Regardless of the break frequency variation that may occur, it is preferred that the analog low-pass filter 50C is not trimmed, of course, because it implements the integration of the analog pre-function 12. However, given the current T1E1.413 "Issue II" standard, it would be necessary to add one trimming bit (fuse) for the analog pre-function 12 to meet its overall power spectral density requirements. is expected.

Further, it has been observed that the worst case group delay caused by the analog low pass filter 50C varies with frequency from about 285 ns to about 655 ns at a breakpoint frequency that is 40% lower than nominal. This small group delay results directly from the low complexity of the analog low-pass filter 50C enabled by the implementation of the digital filter 46C discussed above. Combined with the worst case group delay introduced by digital filter 46C, the total worst case group delay through the transmitter of analog pre-function 12 is about 1.78 μs, which is DSL
Suitable for communication.

The output of the analog low pass filter 50C is provided to a programmable attenuator 52C, which is constructed according to conventional techniques. Programmable attenuator 52C is selectable in 1 dB steps via a control word written to analog pre-function 12 (eg, interface and control function 42C) from 0 dB to -2.
Give 4 dB. The input referred noise provided to programmable attenuator 52C is preferably on the order of -138 dBm / Hz so as not to degrade the signal to noise ratio of the output signal from DA converter 48C.
Such noise requirements are believed to be within the capabilities of the current art. The output of the programmable attenuator 52C is provided on lines TXP, TXM to the line driver 14 and corresponds to an analog signal corresponding to data transmitted and encoded in a manner implemented by the digital transceiver function 10. And an applicable DSL such as T1E1.413
Has frequency characteristics specified by the standard.

If POTS traffic is to be transported through the twisted pair facility TWP, the use of an external high pass filter between the analog prefix function 12 and the twisted pair facility TWP is preferred to eliminate POTS transitions. .

Referring to the receiving side of the analog pre-function 12, the lines RXP, RXM are received from the line driver 14 into a programmable gain amplifier 54C. The programmable gain amplifier 54C preferably converts the incoming signal from 0 dB to 3 dB selectable in 1 dB steps via a control word.
Amplify in a fine manner. According to a preferred embodiment of the present invention, the input impedance of the programmable gain amplifier 54C, as described with respect to FIGS.
Regardless of the selected gain of amplifier 54C, line RX
It is adjusted by the impedance matching circuit 56 to generate a constant input impedance to the line driver 14 on P, RXM.

FIG. 7 shows a programmable gain amplifier 54C implemented in a conventional manner. In this example, the input line RXP is connected to a bonding pad BP of an integrated circuit (such as the integrated circuit forming the analog prefix function 12) (the boundary B in FIG. 7 indicates the chip boundary of the integrated circuit). It is capacitively coupled to the integrated circuit via an external high pass coupling capacitor 89. Programmable gain amplifier 54C adjusts its gain to switches S12, S23, S3X.
Are set to be programmable through the operation of these switches.
2, R3 and RX, these switches are connected between the output of the amplifier 90 and the external coupling capacitor 89.
Are connected in series. Resistors R1, R2, R
3, The value of RX typically varies between these resistors depending on the range and resolution of the programmable gain level desired for amplifier 54C. The non-inverting input of amplifier 90 is biased to ground and the output of amplifier 90 is transferred to analog low pass filter 58C (FIG. 4). Alternatively, the amplifier 90 may be implemented as a differential amplifier, and in particular, in this case, as described above, two lines are used to communicate analog signals (one skilled in the art will recognize a single-ended input It is anticipated that different versions of the amplifier circuits described herein with respect to can easily be implemented). The states of switches S12, S23, S3X determine the gain of programmable gain amplifier 54C by setting the ratio between the feedback resistance and the input resistance, as seen in amplifier 90. As is technically fundamental, the inverting gain of an operational amplifier is proportional to the ratio between its feedback resistance and input resistance. For example, if switch S23 is closed and all other switches S12, S3X are open, the gain of programmable gain amplifier 54C will be proportional to (RX + R3) / (R1 + R2). Other combinations of switches S12, S23, S3X will select different ratios of the feedback resistance to the input resistance, and therefore different gains. However, changing the gain of the programmable amplifier 54C will change its high frequency behavior. In particular, the capacity C ₈₉
The high-pass filter established by the external capacitor 89 with has a pole determined by 1 / R _in C ₈₉ . Here, R _in is the input resistance. Therefore, these changes in high frequency operation will change the frequency response of the entire circuit.

FIG. 8 illustrates an implementation of a programmable gain amplifier 54C combined with an impedance matching circuit 56 in accordance with a preferred embodiment of the present invention. This will be described. The structure and operation of the programmable gain amplifier 54C remains the same as described above with respect to FIG.
In the preferred embodiment of the present invention shown in FIG. 8, the impedance matching circuit 56 includes an external coupling capacitor 89 between the bonding pad BP and a first input resistor R1 on the input of the programmable gain amplifier 54C. Connected to. The impedance matching circuit 56 in this embodiment of the present invention includes a number of resistors connected in series between the input of the programmable gain amplifier 54C and ground. Switches S3X ', S23' and S12 'are connected to resistors RIX,
RI3, RI2, and RI1 are connected between their respective intermediate connection points and ground, so that the switch S3
When closed, each of X ', S23' and S12 'is connected to a resistor RI3, RI2, RI in the impedance matching circuit 56.
Short one or more of the ones. According to a preferred embodiment of the present invention, switches S3X ', S23', S12 'are controlled in tandem with switches S3X, S23, S12, respectively. For example, switch S23 is closed and switch S
When 3X and S12 are opened, switch S23 'is closed and switches S3' and S12 'are all open.

The values of resistors RIX, RI3, RI2, and RI1 are such that resistors R1, R2, R3, and RX1 maintain the input resistance across bonding pad BP substantially constant over the available gain. Is selected to correspond to the value of This is a programmable gain amplifier 5
This is because the frequency response of the combination of 4C and the impedance matching circuit 56 will be proportional to:

[0077]

(Equation 4)

Here, R ₅₆ is the switch S3X ′, S2
3 ', S12' corresponds to the resistance through the impedance matching circuit 56 for a given selection.

In the configuration of FIG. 8, the bonding pad BP
Is connected to resistors R1, R2, and R3, which are selected as input resistors to the amplifier 90, and to the bonding resistors through the impedance matching circuit 56 in parallel with these resistors.
Resistor R connected in series between pad BP and ground
It is equal to the sum of IX, RI3, RI2, and RI1 and their counterparts. For example, if switch S23 and switch S
23 'closed and programmable gain amplifier 5
Opening 4C and all other switches in impedance matching circuit 56, the input resistance created by programmable gain amplifier 54C is the combined resistance of resistors R1, R2 and resistors RIX, RI3 in parallel with them, ie, Equivalent to.

[0080]

(Equation 5)

Similarly, if the switches S12 and S12 'are closed and all other switches are open, the input resistance produced by the programmable gain amplifier 54C and the impedance matching circuit 56 corresponds to:

[0082]

(Equation 6)

The resistors R1, R2, R3, Rx are arranged in such a way as to minimize the variation of the input resistance through all available choices of the switches S3X ', S23', S12 '.
In addition, the values of the resistors RIX, RI3, RI2, and RI1 can be easily set. For example, resistors R1, R2,
R3, Rx and resistors RIX, RI3, RI2, RI1
The following values of give a relatively constant input impedance.

[0084]

[Table 1]

Of course, it is anticipated that one skilled in the art will be able to similarly implement a combination of a programmable amplifier 54C and an impedance matching circuit 56 with different resistances, depending on the particular implementation.

Because of the implementation of the impedance matching circuit 56, the gain of the programmable gain amplifier 54C is now in communication with the central office DSL modem 8 in which the analog pre-function 12 according to the preferred embodiment of the present invention is implemented. Can be programmably selected based on the characteristics of the current subscriber loop. This selection can be made without changing the input impedance that occurs to the line driver 14 and the rest of the system. Therefore, the response of the analog pre-function 12 to the received signal is greatly improved by the implementation of the impedance matching circuit 56.

Referring back to FIG. 4, the output of programmable gain amplifier 54C is an analog low-pass filter 5C.
8C to which a programmable gain amplifier 60 is connected.
Amplification by C and AD conversion by the AD converter 62C follow. In this system, an analog low-pass filter 58C is provided on the receiving side of the analog pre-function 12, mainly to avoid folding collapse of the low-frequency signal band (from DC to 138 kHz). As described above with respect to analog low-pass filter 50C, analog low-pass filter 58C includes a third-order Chebyshev filter implemented in a conventional manner as an active RC network.
It may be implemented as a relatively simple analog filter, such as a filter, with a 6.0 dB passband gain and about 1 unit.
It has a break frequency of 55 kHz. If the analog pre-function 12 is integrated into a single integrated circuit, the polysilicon resistors and polysilicon-polysilicon capacitors may be used in analog low-pass filters regardless of the sensitivity of these components to process variations. Used in 58C. Manufacturing trimming of the analog pre-function 12 may also be used to adjust the analog low-pass filter 58C. However, if a digital filter 64C is present downstream of the analog low-pass filter 58C, as described below, such trimming only to an accuracy of ± 13% variation in the break frequency would be necessary. Not just. According to a preferred embodiment of the present invention, such trimming is enabled, for example, by a number of parallel capacitors in the feedback loop of the operational amplifier, and these capacitors are selectively circuitized as is known in the art. Switched in or out of the circuit, control of such switching is implemented with logic functions controlled by the state of the fuse on the input of such a switch.

In this exemplary implementation, the source of the signal that may be folded back into the received signal at these frequencies is the source generated by the transmitter of analog pre-function 12 itself. As described above, the transmission side of the analog prefix function 12 spans the band from 25 kHz to 1,104 kHz, and depends on the hybrid performance.
It generates a signal having a power spectral density that varies between sBm / Hz. Return loss through hybrid 16 in central office DSL modem 8
Worst case situation occurs when the loop attenuation is high, so that the echo power from the transmitter side of the analog pre-function 12 is relative to the received signal power from the remote DSL modem 15 over the twisted pair facility TWP. Get higher. In this situation, the analog prefix function 12 is preferably controlled as follows. That is, (the line driver 1
The gain of the programmable gain amplifier 54C (combined with the coarse programmable gain amplifier in Figure 4) is set to produce a signal power at the input to the analog low-pass filter 58C in the range of -2.44 dBm to -1.44 dBm. Is done. Assuming that the backflow loss through the hybrid 16 is frequency dependent, this gain is -61.7 in the transmitted signal band from 30 kHz to 1,104 kHz.
It corresponds to 5 dBm / Hz, and after 1,104 kHz, it shifts by -24 dB / octave (roll-off).
As described below, since the AD converter 62C samples at a rate of 4,416 kHz in this embodiment, the low end of the folding bandwidth in the AD converter 62C is 2,
208 kHz. The above gain combination is
At 2,208 kHz, a power spectral density of -85.75 dBm / Hz is produced. The analog low-pass filter 58C according to the preferred embodiment of the present invention
The attenuation done in Hz is at least -65 dB and is provided by the programmable gain amplifier 60C.
Even considering the 5 dB gain, the power spectral density above 2,208 kHz at the input of the A / D converter 62C is at most -145.25 dBm / Hz, which is the level of the A / D converter according to this embodiment of the invention. Since it is at least -9 dB below the quantization noise of 62C, aliasing is substantially eliminated. The group delay created by the analog low-pass filter 58C according to this embodiment of the invention is from 2.3 μs to 5.25 μ over its passband.
s, resulting in a total distortion of about 3 μs.

The gain required to bring the signal level to -144 dBm in this worst case where the received upstream signal is much smaller than the echo from hybrid 16 is that the signal is entirely within the pass bandwidth of filter 58C. , If a significant upstream signal is present due to the short loop, or if the echo power is reduced due to backflow loss through the hybrid 16,
It is expected to be large enough to saturate the analog low pass filter 58C (eg, of the order of 9 dB). The programmable gain amplifier 54C will have its gain adjusted down in this situation.

As described above, the output of analog low-pass filter 58C is connected to second programmable gain amplifier 60C.
C, amplifier 60C provides a gain that increases or decreases in this example in the range of about 2.5 dB to about 5.5 dB in 1 dB steps, and provides an output voltage that swings about 4 V peak-to-peak. Second programmable gain amplifier 60
The output of C is supplied to the AD converter 62C.

AD converter 62C of this embodiment of the present invention
Is a fixed sampling rate of 4,416 kHz, 1
With a 4-bit resolution, the received analog signal is converted to a digital word. A conventional A / D converter implementation may be used for A / D converter 62C according to this embodiment of the present invention. Linearity is preferably achieved by trimming during manufacturing.
Maximized. The reference voltage circuit 68C preferably converts a stable reference voltage, such as a bandgap voltage, into an A / D converter 6.
2C to perform high-accuracy conversion regardless of temperature changes.

The output of the AD converter 62C is supplied to a digital filter 64C. FIG. 9 shows the signal flow through the digital filter 64C combined with the oversampling register 44C. This will be described. As shown in FIG. 9, in order to reduce the sampling rate and hence the complexity of the downstream finite impulse response digital low pass filter 94, first a decimation filter filter is used.
Process 92 is applied to the digital output from AD converter 62C. In this embodiment of the invention, as described above, the sampling rate of AD converter 62C is:
4,416 kHz. Decimation filter
Process 92 implements a 4-tap finite impulse response with all four taps having the same value of 0.25.
The modulation of the result of the decimation filter process 92 is as follows.

[0093]

(Equation 7)

Decimation filter process 92
The sampling rate reduction performed by
The portion of the output spectrum of the AD converter 62C above 04 kHz is folded back into the band from DC to 1,104 kHz. The reduced sampling rate digital stream is then provided to a digital low pass filter 94.

In this embodiment of the invention, the digital low pass filter 94 is a finite impulse response digital filter.
A filter having a sampling rate that is twice the output spectrum of the decimation filter process 92, ie, 2,208 kHz in this example.
Operates at z. Decimation filter process 9
2 reduces the complexity of the digital low-pass filter 94, rather than a 25 tap filter with 53 non-zero tap weighted bits.
Allows the implementation of the filter 94 as a 13-tap finite impulse response filter with symmetric tap weights, thus greatly reducing the complexity of the filter 94 and
Considering the chip area required for the decimation filter process 92 also facilitates the implementation of the filter 94 in the integrated circuit of the analog pre-function 12.

The transfer function implemented by the digital low-pass filter 94 is preferably determined as a trade-off between pass-band ripple and stop-band rejection while still maintaining low complexity. In this regard, the processing performed at the receiving side by the digital transceiver function 10, as discussed above, decimates the signal sampling rate to the order of 276 kHz and at least 41
Eliminate echo components up to 4 kHz, which sets the frequency filtered by the digital low-pass filter to start at about 414 kHz. In accordance with a preferred embodiment of the present invention, a digital low pass filter 94
Has a breakpoint frequency of about 414 kHz and a -32 dB
Is performed in the stop band. Of course, if the echo power spectral density is lower than the worst case, or the signal power spectral density is higher than the worst case, or
If the echo cancellation performed by digital transceiver function 10 extends to higher frequencies, the stopband rejection requirements for digital low pass filter 94 are relaxed.

In accordance with the preferred embodiment of the present invention, digital low pass filter 94 implements a 13 tap finite impulse response filter, which selects tap weighting factors with a small number of non-zero bits. Therefore, it can also be easily implemented as a group of registers and adders (ie, without a dedicated multiplier). The complexity of the digital low pass filter 94 is instead determined by the number of non-zero bits in its tap weighting factor, which in the exemplary embodiment is selected by selecting tap weighting factors such that If it is done, it is only 27.

[0098]

(Equation 8)

In accordance with a preferred embodiment of the present invention, these tap weighting factors are determined by a particular standard (eg, T1E1.
413) can be hard-wired in the digital filter 64C. Alternatively, digital filter 64C may be implemented in such a way that the number of taps and their tap weight factors can be programmably selected, especially if the DSL standard is estimated to be fluid. However, the circuit complexity required for such programmability necessarily increases.

The output of the finite impulse response digital low pass filter process 94 is supplied to an interpolation filter process 96 or, as shown in FIG.
5, the operation is bypassed through the operation of S6. In this embodiment of the invention, interpolation filter process 96 is implemented by oversampling register 44C, which is twice the frequency at which low-pass filter process 94 loads it (eg, 2,208 kHz). The output of the interpolation filter process 96 is sampled at a frequency (e.g., 4,416 kHz). Interpolation filter
The use of process 96 depends on the desired input sampling rate of digital transceiver function 10.

In accordance with a preferred embodiment of the present invention, the analog pre-function 12 in the central office DSL modem 8 is implemented in a single integrated circuit due to the reduced complexity of the analog filters 50C, 58C. And the reduced complexity can be realized by digital filters 46C, 6C.
Enabled by having 4C. Still further
In accordance with a preferred embodiment of the present invention, the analog prefix function 1
Digital filter 46 in the digital domain within 2
The digital filter operation performed by C, 64C uses tap weighting factors with relatively few non-zero bits to facilitate implementing analog pre-function 12 on a single integrated circuit. , A finite impulse response filter. The ability to integrate these functions significantly reduces the component trimming required during manufacturing, greatly reduces the cost of analog pre-functions in DSL modems, and improves overall system performance.

FIG. 10 shows the structure and operation of the analog prefix function 11 in the remote DSL modem 15. This will be described in detail. As was the case with the analog prefix function 12 in the central office DSL modem 8, the analog prefix function 11 is limited to that function alone, or alternatively, the digital transceiver function 13, line Driver 1
It can also be integrated into a single integrated circuit, either integrated with certain other functions such as 7 or the like. As will be apparent from the following description, analog pre-function 11 and analog pre-function 12 may both be implemented on a common integrated circuit. However, to the extent that for a given integrated circuit it uses metallization selection or fuse programming to determine whether it will act as a remote analog prefix 11 or as a central office analog prefix 12. , Analog prefix function 11 is very similar to analog prefix function 12 described above.

As in the case of the analog pre-function 12, the analog pre-function 11 according to an embodiment of the present invention comprises a high-pass filter, a transmitter power splitter, a 4-wire to 2-wire hybrid and a receiver coarse programmable. It is intended to feed all loop interface components that are not exposed to high voltages, such as gain amplifiers. Such elements are external to the analog pre-function 11 (e.g., implemented within the line driver 17 and hybrid 19).

As in the case of the analog prefix function 12, the analog prefix function 11 includes a transmitting side and a receiving side.
Further, an echo canceling transmitting side 53 as a second transmitting side is provided in the analog prefix function 11, and this transmitting side is equivalent to the signal transmitting side shown in FIG. I have. In this connection, the echo cancellation transmitting side 53 uses the analog prefix function 11 to transmit the lines TXP, TXP.
The lines ECP and ECM are driven by an analog signal corresponding to the signal generated on the XM. Track ECP, ECM
Arrives at a line receiver external to the analog prefix 11 (eg, at the line driver 17) and provides a scaled copy of the low frequency upstream transmit signal, which copy is transmitted by the analog prefix 11 It can be used to cancel any echo signals generated by the side.

In this embodiment of the present invention, the transmitting side (both the main transmitting side and the echo canceling transmitting side 53) and the receiving side share the interface and the control function 42R, through which the analog prefix function 11 can be used as a digital signal. -Communicate with the transceiver function 13. As before, the interface and control function 42R includes a parallel digital interface, over which digital words transmitted by the remote DSL modem 15 are received by the analog prefix function 11, via which Data received by the twisted pair facility TWP and processed by the analog prefix function 11 is communicated to the digital transceiver function 13 as a digital word. According to this embodiment of the invention, the parallel interface is a 16-bit parallel interface,
Each has an edge-triggered read strobe input and a write strobe input to control reading of data from and writing of data to it. Furthermore,
The interface and control function 42R includes various programmable gain amplifier gain values (as described below),
Switch control to bypass or enable various filter blocks and functions, and, in the case of analog pre-function 11, for setting the gain of the receive equalizer function (as described further below). It includes a number of control registers that store control words that set the state of various functions within analog pre-function 11, such as switch control.

The interface and control function 42R also includes a suitable signal interface for receiving and supplying control information to and from the digital transceiver function 13. In this embodiment of the invention, the serial port PS
Is provided for receiving control information such as used to set the frequency of the clock signal, as described below. Conventional scanning tests, such as the JTAG standard, also preferably provide interface and control functions 42
Implemented via R.

Clock circuit 66R has analog pre-function 1
1 and supplies a corresponding clock signal for the synchronous operation of these functions.
In accordance with a preferred embodiment of the present invention, clock circuit 66R
Generates an internal (and external, if desired) clock based on an external voltage controlled crystal oscillator (VCXO) 65X. As discussed above in connection with analog prefix function 12, a 12-bit serial D / A converter 63R within analog prefix function 11 generates an analog voltage signal, which is
In response to a control signal received by the interface and control function 42R (particularly via an update signal provided to the serial port SP within this function), it is provided to an external voltage controlled crystal oscillator 65X.

A reference voltage 68R, preferably a stable reference voltage such as a bandgap reference voltage, is also shared by the transmitting and receiving sides of the analog prefix function 11. Other circuits used within the analog prefix function 11, such as power distribution and regulation, general port communication, etc., may of course be included in this analog prefix function, but for the purpose of simplicity of this description. Not shown. As shown in FIG.
The analog pre-function 11 also includes an oversampling register 44R, which may include one or more over-sampling registers 44R, such as those used in the analog pre-function 11 in implementing the digital filtering operation described further below. Includes register stage.

Referring to the signal transmitting side of the analog pre-function 11, the digital filter 46R receives digital data words from the oversampling register 44R and performs digital filtering on these digital data words prior to DA conversion. carry out. FIG. 11 shows the data flow through a digital filter 46R combined with an oversampling register 44R for an exemplary implementation of the preferred embodiment of the present invention. This will be described in detail.

As shown in FIG. 11, the digital filter operation process performed by the analog pre-function 11 includes a number of options, including digital options.
The digital signal supplied by the transceiver function 13
It can be selected by switches S7 to S10 depending on the frequency and characteristics of the data. As in analog pre-function 12, interpolation filter 94 only doubles the sampling rate (e.g., by loading one of oversampling registers 44R at twice the rate at which its output is sampled (e.g., 2,2
(From 08 kHz to 4,416 kHz). As described above, this operation implements a filter with a transfer function of 1 + Z ⁻¹ and involves zero group delay distortion. Due to the relatively low frequency of these signals (the highest signal frequency is 138 kHz), the modulation resulting from this filter is insignificant.

Next, a digital high pass filter process 96 is performed by the analog pre-function 11 as part of the digital filter 46R of FIG. As in the case of the analog pre-function 12, the digital high-pass filter process 96 is preferably a first-order high-pass filter, for example, a conventional infinite impulse response (IIR) digital filter design technique. With a -3 dB breakpoint frequency of 10.7 kHz implemented via The characteristics of the digital high pass filter process 96 in the analog prefix function 11 are preferably similar to those described above for the digital high pass filter 72 in the analog prefix function 12.

A digital low-pass filter process 98 then filters the digital signal (filter processes 94 and 96) to band limit the digital data so as to reduce the complexity of the downstream analog filter operation. (To the extent filtered by). The analog filtering operation of the upstream DSL communication is performed by the digital low-pass filter process 9.
According to the present invention, it can be reduced from a fourth order analog filter to a second order analog filter through use of
Has been observed. The contribution of the downstream analog filter operation to noise is also sufficiently suppressed. In accordance with a preferred embodiment of the present invention, digital low pass filter process 98 is implemented through an infinite impulse response (IIR) implementation having a knee frequency at about 138 kHz. A particularly advantageous realization of the digital low pass filter process 98 is a minimum (± 0.5d
B) Third order infinite impulse response approximating an elliptical response with passband ripple. The preferred exemplary realization utilizes a time domain filter equation as follows.

[0113]

(Equation 9)

Here, the coefficient is defined as follows.

[0115]

(Equation 10)

This particular implementation is an ideal digital elliptic filter to reduce circuit complexity by maintaining coefficients that have a relatively small number of non-zero bits and therefore can also be implemented without multipliers. Deviates only slightly. This deviation only causes a 0.25 droop in the knee frequency, which is acceptable for this application. Even considering the infinite impulse response implementation of the digital low pass filter process 98 in this embodiment of the invention, the group delay varies from only about 2.21 μs (at 25 kHz) to 3.76 μs (at 138 kHz).

According to a preferred embodiment of the invention, in particular T
These tap weighting factors are preferably hard-wired into the analog pre-function 11 to implement a known standard such as the 1E1.413 standard. Alternatively, analog pre-function 11 may include registers or other addressable locations, particularly in view of the speed at which telecommunications standards may change over time, including the number of taps and their The tap weighting factors for the taps may be programmable. Then, the result of the digital low-pass filter process 98, as shown in FIG.
8R. According to a preferred embodiment of the present invention,
The structure of the DA converter 48R is the same as that of the DA converter 4 shown in FIG.
Note that this figure is substantially similar to that described above for 8C.

As shown in FIG. 10, the DA converter 48R
Is supplied to the analog low-pass filter 50R. Analog low-pass filter 50R according to a preferred embodiment of the present invention is a second-order Chebyshev continuous-time filter with a nominal 166 kHz passband implemented according to the prior art. The filter 46R in the filter processes 96, 98 discussed above is enabled to the extent of the digital filter operation previously performed. Regardless of the break frequency variation that may occur, it is preferred that the analog low-pass filter 50R is not trimmed because of the integration of the analog pre-function 11. Assuming typical process variations in modern manufacturing technology, this would result in a 40% variation of the passband break frequency around a nominal break frequency of 166 kHz, which is 138 kHz in the worst case
It is expected to meet ripple specifications over the signal band.

Further, it has been observed that at a breakpoint frequency 40% below nominal, the worst case group delay caused by analog low pass filter 50R varies with frequency from about 1.14 μs to about 1.82 μs. This small group delay is due to the digital filter 46 discussed above.
The direct implementation of the low complexity of the analog low-pass filter 50R enabled by the implementation of R is suitable for DSL communication.

[0120] The output of the analog low pass filter 50R is provided to a programmable attenuator 52R, which is constructed by conventional techniques. Analog prefix function 12
As described above, the programmable attenuator 52R provides a selectable 0 dB to −24 dB attenuation in 1 dB steps via a control word written to the analog prefix function 11. As before, the noise during the input provided to the programmable attenuator 52R is reduced by the DA converter 4
It is preferably of the order of -138 dBm / Hz so as not to degrade the signal-to-noise ratio of the output signal from the 8R. The output of programmable attenuator 52R is provided on lines TXP, TXM to line driver 17 and corresponds to an analog signal corresponding to data transmitted and encoded in a manner implemented by digital transceiver function 13. And has frequency characteristics specified by applicable standards, such as T1E1.413.

Referring to the receiving side of FIG.
The lines RXP, RXM driven by the line driver 17 in response to the communication signal received through the twisted pair facility TWP from the L modem 8 reach the equalizer 57. According to a preferred embodiment of the present invention, equalizer 57 comprises:
It is provided to compensate for attenuation across the twisted pair facility TWP, especially at high frequencies where downstream data is communicated using ADSL technology.

In particular, as described above, the bandwidth for implementing the downstream communication with the ADSL technology is as follows.
It is between 25 kHz and 1.104 MHz. When signals spanning this bandwidth are fed over a conventional twisted pair telephone line, such as a twisted pair line facility TWP, significant attenuation can often occur. This attenuation becomes worse as the line number decreases, as the line length increases, and as the signal frequency increases. FIG. 12 plots the decay for various line lengths and numbers, as shown by curve 100,
Indicated by 102, 104, 106, 108. Curve 1
00, 102, and 106 show the line attenuation for 305 m, 2743 m, and 5486 m of the 24th AWG twisted pair line, and the curves 104 and 108 show the line attenuation for 2743 m and 5486 m of the 26th AWG twisted pair line. As is apparent from FIG. 12, line attenuation can be quite severe in some cases. For example, 1MHz
The signal will be attenuated to the order of -100 dB when fed to a 5486 m 24th AWG twisted pair. However, at the receiving end of such signals, conventional A / D converters have a substantially flat quantization noise floor over frequency. As a result, high frequency signals communicated over conventional twisted pair facilities may be attenuated by the transmission line to the point that they fall below the quantization noise floor of the receiving A / D converter, in which case the high frequency portion of the bandwidth is reduced. Is lost.

FIG. 12 shows that line attenuation can be approximated by two complex poles. According to a preferred embodiment of the present invention, a frequency domain equalizer 57 is provided in the analog pre-function 11 to boost the signal at high frequencies according to a characteristic having two dominant zeros. The noise conditions on the receiving side of the analog prefix 11 are very strict according to the current ADSL standard (for example 5 nV / (Hz)
^In particular, the frequency characteristics of the equalizer 57 are preferably controllable to compensate for wide variations in line conditions, loop length and quality. Although the use of switched capacitor stages has been considered for such equalization in accordance with a preferred embodiment of the present invention, to achieve this in accordance with modern technology, excessive capacitors and unrealistically low noise and high It was observed to involve a settling speed operational amplifier. Therefore, given the low distortion level requirements of ADSL communication, the preferred RC (compared to gm-C and MOSFET-C implementations)
It is preferred in the context of the present invention that the equalizer 57 is preferably implemented for a continuous time, with the aid of an operational amplifier.
It's been found. Further, the compensation of such line attenuation by the equalizer 57 is performed by the AD converter 62R.
It is particularly necessary to include it in the analog domain prior to conversion.

FIG. 13 shows the structure of the equalizer 57 according to the first embodiment of the present invention, in which two operational amplifier stages 110 and 112 are connected in cascade. Step 11
0, 112 respectively include operational amplifiers 111, 113, each of which has an input RC network and a feedback R
It has a C network. For example, stage 110 includes a variable resistor R
An input RC network consisting of a parallel RC network of s1 and a capacitor Cs1 and a resistor Ri1 in series with this, and a feedback parallel RC network consisting of a variable resistor Rf1 and a capacitor Cf1.
And a network. Step 112 has a similar configuration. As a result, the frequency response of equalizer 57 is expressed as:

[0125]

[Equation 11]

Here, G ₁₁₁ and G ₁₁₃ are amplifiers 11 determined by the ratio of the feedback resistance to the input resistance, respectively.
The gain is 1,113. For example, the gain G ₁₁₁ is determined by the ratio R
f1 / (Ri1 + Rs1). The characteristic transfer function frequencies ω _111x and ω _112x of the stages 110 and 112 are defined as follows (for example, for the stage 110).

[0127]

(Equation 12)

This transfer function therefore produces two zeros, one from each stage, each of which can be easily controlled for a particular stage by the product Rs.Cs.
The two poles of this transfer function can be taken at appropriate frequencies to attenuate the band response.

The equalizer 57 in this embodiment of the present invention
Includes two stages, but it is also possible to more precisely control the transfer function through the use of more than two stages. In such a case,
The number of product terms in the transfer function, of course, corresponds to the number of stages used in equalizer 57.

As mentioned above, the location of the zeros of the equalizer 57 is preferably optimized to compensate for line attenuation over the expected range of loop conditions by selecting the gain level with respect to frequency. You. For example, 5dB
It is expected that one can select a boost slope that varies with frequency (ie, boosts more and more at higher frequencies), increasing in increments from 5 dB to 25 dB. Thus, referring to FIG. 13, each of the variable resistors Rs1, Rf1, Rs2, Rf2 is implemented via a set of parallel resistors and the resistance of each of these resistors is set to set the gain for each of the stages 110, 112. It is preferable that each can be operated or prohibited by opening and closing a switch. Alternatively, of course, those zeros may be set by fixed resistance values according to the design. Further, instead of these, referring to FIG.
A switch (not shown) may be inserted in the analog pre-function 11 so that the lines RXP, RXM bypass the equalizer 57 and reach the analog low-pass filter 58R directly. In a preferred embodiment of the present invention, exemplary RC values for the various settings of the above example are listed in the following table.

[0131]

[Table 2]

In this example, the resistors Ri1 and Ri2 are 500
Assume Ω. FIG. 14 shows the frequency response over the frequency of the equalizer 57 for the above setting. As can be seen, the high frequency boost provided by the equalizer 57 compensates for line attenuation across the twisted pair facility TWP. According to a preferred embodiment of the present invention, the equalizer 5
7 is relatively simple to implement and involves minimal group delay distortion (eg, on the order of 1.96 μs).

Referring back to FIG. 10, the output of the equalizer 57 is supplied to an analog low-pass filter 58R.
The analog low pass filter 58R according to this embodiment of the invention is a fourth order elliptic continuous time filter with a nominal 1.325 MHz pass band. As described above, the analog low-pass filter 58R need not be trimmed, regardless of the effect on the break frequency due to process variations. The worst case group delay through analog low pass filter 58R is expected to be about 2.1 μs. Alternatively, improved process control can be provided by trimming either the resistors or the capacitors at the amplification stages 110, 112.

According to an alternative embodiment of the present invention, analog low-pass filter 58R is implemented by a ladder filter, which has a number of operational amplifier stages, the first of which is a plurality of stages. Is also an equalizer 57
Serves as the second stage of the. FIG. 15 shows such a configuration. This will be described in more detail below.

As shown in FIG. 15, the stages 110 ', 11
Analog low-pass filter 5 as well as each of 2 '
8R are realized in differential form, and the lines RXP,
Receive RXM. Resistors Rs and Rf associated with each of the inverting and non-inverting inputs are connected to stages 110 ', 11
A variable resistor within both 2 ', providing a selectable equalizer gain as described above. However, for the purpose of stability of the analog low-pass filter 58R, stage 1
Preferably, the values of the 12 'resistors Rs and Rf are not adjusted, so that the characteristics of the filter do not vary with the selection of the gain of the equalizer 57.
Referring to the above table, a wide range of gain can be obtained without changing the resistance in the second stage 112 '. As can be seen from FIG. 15, analog low pass filter 58R is implemented in the conventional manner for an active filter, with the negative feedback from each operational amplifier stage in filter 58R being provided to each of the preceding stages, including stage 112 '. You.

According to an alternative embodiment of the present invention, step 11
2 'also serves as both the second stage in equalizer 57 and the first stage in analog low pass filter 58R. Because of the need for stage 112 'to be in analog low-pass filter 58R in order to obtain the proper order filter, equalizer 57 operates by simply adding a single operational amplifier stage 110' from this duplication. It is possible. as a result,
This embodiment of the present invention provides the additional advantage of implementing analog pre-function 11 more efficiently on an integrated circuit. The overall noise and distortion of the channel is also minimized by the addition of a single stage, which further improves the performance of the analog pre-function 11.

Referring back to FIG. 10, the output of the analog low-pass filter 58R is provided to a programmable gain amplifier 60R, which in this example is a 25k
Hz over a signal bandwidth of 1,104 kHz.
About 2.5dB to about 11.5dB in 25dB steps
, And a maximum output signal voltage swing of about 4 V peak-to-peak. The output of the second programmable gain amplifier 60R is the A / D converter 62R.
Supplied to

The AD converter 62R in this embodiment of the present invention converts the received analog signal into a digital word with a fixed sampling rate of 4,416 kHz and a resolution of 14 bits. A conventional A / D converter implementation may be used for A / D converter 62R according to this embodiment of the present invention. Linearity is preferably maximized by trimming during manufacturing. For highly accurate conversion regardless of temperature, the reference voltage circuit 68R preferably supplies a stable reference voltage, such as a bandgap voltage, to the AD converter 62R.

The output of the AD converter 62R is supplied to a digital filter 64R. FIG. 16 shows the signal flow through the digital filter 64R combined with the oversampling register 44R. This will be described in detail. As shown in FIG. 16, the digital low-pass filter process begins with the output sampling rate of the A / D converter 62R, which in this example is 4,416 kHz.
Is a 2-pole, 2-zero biquadratic s
Section) Perform sampling. Digital low-pass filter 120 is provided primarily to attenuate noise above 1,104 kHz generated by equalizer 57 and analog low-pass filter 58R, so that aliasing from these frequencies is performed by sampling Nothing happens when the rate is decimated to 2,208 kHz. The transfer function of the digital low-pass filter 120 according to the preferred embodiment of the present invention is as follows.

[0140]

(Equation 13)

According to the exemplary implementation of digital low pass filter 120, the 1,312 kHz
The stopband rejection above z is about 8.8 dB.

Next, if desired (eg, enabled by switches S11 and S12), a decimation filter process 122 is applied to the filtered data from digital low pass filter 120. A decimation filter process 122 is provided to reduce the sampling rate, if desired by the digital transceiver function 13. In this example, the decimation filter process 122 is simply a two sample moving average circuit,
It has the following transfer function:

[0143]

[Equation 14]

[0144] In this case, f _c is the input sampling rate of 4,416kHz. The decimation filter process 122 causes a slight droop in its passband, but such droop is acceptable or digital
It can also be compensated by the FFT process 22R in the transceiver function 13.

The total group delay on the receiving side of the analog pre-function 11 varies in the range from about 0.92 μs to about 2.28 μs depending on the setting selected for the equalizer 57. Presumed. This group delay is small enough so that there is minimal distortion in the received signal.

The analog pre-function 11 according to the present invention is similar to the analog pre-function 12 described above, and is therefore implemented in a single integrated circuit and with reduced complexity analog filters 50R, 58R. This provides significant advantages for the implementation of high performance modems of the DSL type. This reduction in complexity is
This is made possible by the provision of the filters 46R, 64R. Still further, in accordance with a preferred embodiment of the present invention, analog pre-function 11 provides the ability to selectively compensate for a wide range of line attenuation conditions through the use of equalizer 57. As described above, in accordance with certain embodiments of the present invention, the equalizer can be implemented with only a single operational amplifier stage, thus reducing chip area costs and additional noise due to additional processing. As mentioned above, the ability to so integrate these functions is enabled by the present invention, along with a considerable reduction in component trimming required during manufacturing, as well as the analog pre-functions in DSL modems. Extremely low cost and improved overall system performance.

Although the present invention has been described in accordance with its preferred embodiments, modifications and alternatives to these embodiments will take advantage of the advantages and benefits of this invention and should not be construed as limiting such modifications. Embodiments and alternative embodiments are, of course, expected to be apparent to those skilled in the art from reference to the specification and the accompanying drawings. Such modifications and alternative embodiments are expected to be within the scope of the invention, as set forth in the following claims.

With respect to the above description, the following section is further disclosed.

(1) An analog pre-circuit for a modem integrated on a single integrated circuit, comprising: a digital interface for communicating digital signals; and the digital interface coupled to the digital interface. A digital filter function for applying a digital filter function to a digital signal received from the digital filter, and a digital / digital converter coupled to the digital filter for converting the filtered digital signal into an analog signal.
An analog converter, a transmit analog filter for filtering the analog signal into a first transmit frequency band, and a receive analog filter for filtering an analog signal received by the analog pre-circuit, wherein the analog signal A received analog filter, wherein the analog / digital converter is coupled to the received analog filter for converting the filtered analog signal to a digital signal; and wherein the analog / digital converter is coupled to the received analog filter. Applying a digital filter function to the converted digital signal, coupled to a converter;
A receive digital filter having an output coupled to the digital interface.

(2) The transmission digital filter is:
A first filter comprising: an interpolation filter for increasing a sampling rate of the digital signal; and a digital low-pass filter coupled to the interpolation filter for filtering the increased sampling rate digital signal.
Analog pre-circuit as described in the item.

(3) The transmission digital filter is:
3. The analog pre-circuit of claim 2, further comprising a digital high pass filter coupled between said interpolation filter and said digital low pass filter.

(4) The analog pre-circuit of claim 3, further comprising a bypass switch for routing and transferring said digital signal to bypass said interpolation filter and said digital high-pass filter.

(5) The analog pre-circuit according to claim 2, wherein said digital low-pass filter is realized as a finite impulse response filter.

(6) The analog front-end circuit according to claim 1, wherein the transmission analog low-pass filter has an order of three or less.

(7) The function of the receiving digital filter includes a decimation filter for lowering the sampling rate of the digital signal at the output of the analog / digital converter, and a function of the analog / digital converter and the digital interface. A digital low-pass filter connected in series with said decimation filter between the analog pre-circuit and the decimation filter.

(8) The analog pre-circuit according to claim 7, wherein the digital low-pass filter is a finite impulse response filter.

(9) The analog front-end circuit according to claim 1, wherein the received analog low-pass filter has an order of three or less.

(10) Receiving an analog signal in the first reception frequency band, amplifying the reception analog signal according to a frequency response, and supplying the amplified reception analog signal to the analog low-pass filter. 2. The analog pre-circuit of claim 1, further comprising an equalizer.

(11) The analog front-end circuit according to claim 10, wherein the first reception frequency band includes a frequency higher than a frequency in the first transmission frequency band.

(12) The analog front-end circuit according to (1), wherein the first reception frequency band includes a frequency higher than a frequency in the first transmission frequency band.

(13) The analog pre-circuit according to claim 1, wherein the first transmission frequency band includes a frequency higher than a frequency in the first reception frequency band.

(14) Integrated into a single integrated circuit, a host interface, a digital transceiver function coupled to the host interface, an analog line driver for driving and receiving analog signals through the telephone facility. An analog pre-circuit, the analog pre-circuit comprising a digital interface for communication of digital signals with the digital transceiver function, and a digital interface coupled to the digital interface. A transmitting digital filter for applying a digital filter function to a received digital signal, a digital / analog converter coupled to the transmitting digital filter for converting the filtered digital signal into an analog signal, and the analog line Supply to the driver A transmit analog filter for filtering the analog signal into a first transmit frequency band, and a receive analog filter for filtering an analog signal received by the analog pre-circuit from the analog line driver. The analog signal is the first
A receiving analog filter in the receiving frequency band of
An analog-to-digital converter coupled to the receive analog filter for converting the filtered analog signal to a digital signal; and a digital filter coupled to the analog-to-digital converter for converting the converted digital signal. A receive digital filter having an output coupled to said digital interface, said function applying a function.

(15) The modem of claim 14, wherein said digital transceiver function comprises a programmable digital signal processor.

(16) The transmitting digital filter is an interpolation filter for increasing a sampling rate of the digital signal, and a digital low-pass filter coupled to the interpolation filter for filtering the enhanced sampling rate digital signal. And a pass filter.
The modem according to claim 14.

(17) a digital high-pass filter coupled between the interpolation filter and the digital low-pass filter;
A bypass switch for routing and transferring the digital signal to bypass the interpolation filter and the digital high-pass filter.
The modem according to claim 6.

(18) The modem according to (16), wherein the digital low-pass filter is realized as a finite impulse response filter.

(19) The modem according to (14), wherein the transmitting analog low-pass filter has an order of three or less.

(20) The function of the reception digital filter includes a decimation filter for lowering a sampling rate of the digital signal at an output of the analog / digital converter, a function of the analog / digital converter and the digital interface, A digital low-pass filter connected in series with said decimation filter between the two.

(21) The modem according to the item 20, wherein the digital low-pass filter is a finite impulse response filter.

(22) The modem according to (14), wherein the reception analog low-pass filter has an order of three or less.

(23) The analog pre-circuit receives an analog signal in the first reception frequency band from the line driver, amplifies the reception analog signal according to a frequency response, and amplifies the amplified reception analog signal. The modem of claim 14, further comprising a receive equalizer that provides a signal to the analog low pass filter.

(24) The modem according to item 23, wherein the first reception frequency band includes a frequency higher than a frequency in the first transmission frequency band.

(25) The modem according to (14), wherein the first reception frequency band includes a frequency higher than a frequency in the first transmission frequency band.

(26) The modem according to (14), wherein the first transmission frequency band includes a frequency higher than a frequency in the first reception frequency band.

(27) Asynchronous digital subscriber line (AD
Digital Subscriber Line (DSL) used for SL) communications
Modems 8, 15 are disclosed. Each modem includes a digital transceiver function 10,13 and an analog prefix function 12,11 where the analog prefix function 12,13.
11 is integrated into a single integrated circuit. According to the disclosed embodiment, the analog prefix functions 12, 11 each include a transmitter and a receiver. The transmitting side is oversampling
Registers 44C and 44R and digital filter 46
C, 46R, which serve to increase the sampling rate of the transmitted digital data. As a result, the analog / digital converters 48C, 48R operate in an oversampled manner, resulting in the downstream analog low-pass filters 50C, 50R being implemented with relatively simple low order filters. On the receiving side,
In order to reduce the complexity of the receiving analog filters 58C, 58R, digital filter functions 64C, 64
R is included downstream of the analog / digital converters 62C and 62R. The remote DSL modem 15 also includes an equalizer function 57 that boosts signal amplitude at higher frequencies to overcome the effect of line attenuation on high frequency downstream transmission.

[Brief description of the drawings]

FIG. 1 is a block diagram of a DSL modem system showing the location of a DSL modem at a remote user location in a telephone system and at a central office.

FIG. 2 is a block diagram illustrating the signal flow of a digital transceiver function in the remote DSL modem of the telephone system of FIG. 1 according to a preferred embodiment of the present invention.

FIG. 3 is a block diagram of a digital transceiver function in a central office DSL modem of the telephone system of FIG. 1 according to a preferred embodiment of the present invention.

FIG. 4 is a block diagram of an analog prefix function in the central office DSL modem of the telephone system of FIG. 1 according to a preferred embodiment of the present invention.

FIG. 5 is a system diagram illustrating a digital filter operation performed by a transmitter of the analog pre-function of FIG. 4 according to a preferred embodiment of the present invention;

FIG. 6 is a block diagram of a digital-to-analog converter in the transmitter of the analog pre-function of FIG. 4 according to a preferred embodiment of the present invention;

FIG. 7 is a block diagram of a conventional programmable gain amplifier.

FIG. 8 is a block diagram of a programmable gain amplifier combined with an impedance matching circuit used on the receiving side of the analog pre-function of FIG. 4 according to a preferred embodiment of the present invention.

FIG. 9 is a system diagram illustrating a digital filter operation performed by a receiver of the analog pre-function of FIG. 4 according to a preferred embodiment of the present invention;

FIG. 10 is a block diagram of an analog prefix function in a remote DSL modem of the telephone system of FIG. 1 according to a preferred embodiment of the present invention.

FIG. 11 illustrates a digital signal performed by the transmitter of the analog prefix function of FIG. 10 in accordance with a preferred embodiment of the present invention.
It is a system diagram which shows a filter operation.

FIG. 12 is a line attenuation curve plotted against frequency for various folding line numbers and lengths.

FIG. 13 according to a first preferred embodiment of the present invention;
FIG. 3 is a schematic block circuit diagram of an equalizer used on the receiving side of the analog pre-function of FIG.

FIG. 14 is a transfer function curve plotted for the equalizer of FIG. 13 in various settings.

FIG. 15 according to a second preferred embodiment of the present invention;
FIG. 3 is a schematic block circuit diagram of an equalizer used on the receiving side of the analog pre-function of FIG.

FIG. 16 illustrates a digital signal performed by the receiver of the analog pre-function of FIG. 10 in accordance with a preferred embodiment of the present invention.
It is a system diagram which shows a filter operation.

[Description of Signs] 7,9 Host Interface 8 Central Office DSL Modem 10,13 Digital Transceiver Function 11,12 Analog Prefix Function 14,17 Line Driver 15 Remote DSL Modem 16,19 4-wire-2wire Hybrid circuit 20C, 20R Framing and coding process 22C, 22R IFFT process 26C, 26R, 30C, 30R Analog pre-function interface process 31C, 31R Time domain equalizer process 33C, 33R FFT process 35C, 35R Frequency domain equalization 40C, 40R Decoding and deframing process 42C, 42R Interface and control functions 44C, 44R Oversampling registers 46C, 46R, 64C, 64R Digital Filters 48C, 48R, 63C, 63R D / A converters 50C, 50R, 58C, 58R Analog low-pass filters 52C, 52R Programmable attenuators 53 Echo cancellation transmitters 54C, 60C, 60R Programmable gain amplifiers 56 Impedance matching circuits 62C, 62R AD converter 66C, 66R Clock circuit 68C, 68R Reference voltage circuit 70, 74, 94, 96 Interpolation filter process 71, 72 Digital high-pass filter 76 Digital low-pass process 78 MSB sub DA converter array 80 LSB sub D / A converter array 84 Calibration logic 85 Calibration circuit 85 Binary-thermometer decoder 86 Bias and reference current circuit 89 External high-pass coupling capacitor 92 Decimation filter process 94 Finite impulse response Digital low-pass filter process 96,98 Digital low-pass filter process 111,111 'First operational amplifier stage 112,112' Second operational amplifier stage 120 Digital low-pass filter 122 Decimation filter process BP Bonding pad R Remote system TWP Twisted pair line facility

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04M 11/00 302 H04L 13/00 309Z H04Q 3/42 104 27 / 00Z (72) Inventor Subhashish Mukherzhi India Countries Bangalore, Murguspariya, ES Layout, Laby Nest, Flat 308

Claims (1)

[Claims] An analog pre-circuit for a modem integrated in a single integrated circuit, comprising: a digital interface for communicating digital signals; and a digital interface coupled to the digital interface. A transmit digital circuit that applies a digital filter function to the received digital signal.
A filter coupled to the transmit digital filter for converting the filtered digital signal into an analog signal; and a transmit analog filter for filtering the analog signal into a first transmit frequency band. A receive analog filter for filtering an analog signal received by the analog pre-circuit, wherein the analog signal is within a first receive frequency band; and a receive analog filter coupled to the receive analog filter. An analog-to-digital converter for converting the filtered analog signal to a digital signal; and applying a digital filter function to the converted digital signal, the digital-to-analog converter being coupled to the analog / digital converter. .Output coupled to the interface Analog pre-end circuit comprising: a receiving digital filter, the having.