WO2005015653A1 - Transistor a effet de champ - Google Patents

Transistor a effet de champ Download PDF

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Publication number
WO2005015653A1
WO2005015653A1 PCT/GB2004/003428 GB2004003428W WO2005015653A1 WO 2005015653 A1 WO2005015653 A1 WO 2005015653A1 GB 2004003428 W GB2004003428 W GB 2004003428W WO 2005015653 A1 WO2005015653 A1 WO 2005015653A1
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WO
WIPO (PCT)
Prior art keywords
field effect
effect transistor
region
gate
transistor according
Prior art date
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PCT/GB2004/003428
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English (en)
Inventor
Raoul Schroder
Martin Grell
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The University Of Sheffield
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Priority claimed from GB0318522A external-priority patent/GB2404785A/en
Application filed by The University Of Sheffield filed Critical The University Of Sheffield
Publication of WO2005015653A1 publication Critical patent/WO2005015653A1/fr

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
    • G11C13/0016—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/17—Memory cell being a nanowire transistor

Definitions

  • the present invention relates to a field effect transistor and a method of fabricating the same, and more particularly but not exclusively, a field effect transistor (FET) for use in devices such as smart cards, liquid crystalline displays (LCDs) and organic light emitting displays (OLEDs).
  • FET field effect transistor
  • FETs organic active matrix drivers for displays
  • LCD and OLED organic active matrix drivers for displays
  • memories consisting of a conventional FET and a capacitor.
  • a significant drawback to such memory devices is that they require two components and the memory is volatile due to capacitor leakage.
  • the working principle of an FET is that the current between source and drain electrodes (which are separated by a semiconductor region) depends on the field present in the transistor, which is itself controlled by applying a voltage to a gate insulator region via a gate electrode.
  • the semiconductor body is separated from the gate electrode by the gate insulator region.
  • a sufficiently high voltage of a suitable polarity is applied to the gate electrode the associated electric field induces a charged accumulation layer in the semiconductor at the semiconductor-gate insulator interface of the device. Current will flow through the accumulation layer so as to put the device into an "on" state.
  • a conducting accumulation layer that is, channel is induced in the semiconductor body region adjacent to the gate insulator.
  • This current will flow from the drain to the source (following the convention on direction of current flow), a djacent to the b ody r egion, w ith e lectrons c omprising t he m ajority c harge carriers (i.e. the electrons will flow from the source to the drain).
  • a capacitor is connected between the gate and source electrodes of the FET.
  • the drain electrode is connected to one of the display electrodes.
  • a separate voltage charges the capacitor such that the voltage at the gate electrode is sustained. To maintain a current to the display electrode it is necessary to periodically refresh the charge on the capacitor to sustain the gate voltage.
  • Ferroelectric materials possess a crystalline structure and a thermodynamic phase wherein they display a characteristic hysteresis loop for the electric displacement with respect to the applied electric field while the temperature of the material remains below the Curie temperature of that particular material.
  • the electric field is increased in one direction the polarity of the material is aligned, and this alignment remains at least in part when the electric field is reduced back to zero.
  • the material retains a remanent polarisation. To reverse this polarisation it is necessary to apply an electric field across the material in the opposite direction.
  • the FET can then simply be poled by an initially applied voltage, with the insulator acting to keep the FET in the "on" state after the poling voltage is turned off (Tingkai Li et al, "Fabrication and characterization of a Pb 5 Ge 3 O n one-transistor-memory device", Appl. Phys. Lett. 79, p. 1661-1663 (2001); M. W. J. Prins et al, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett. 68, p. 3650-3652 (1996).).
  • Ferroelectric FETs typically employ an inorganic semiconductor layer in conjunction with an inorganic ferroelectric insulating layer. TTo address problems related to lattice mismatch between the inorganic insulator and semiconductor layers it is often necessary to provide an 'intermediate crystal structure mediating layer', which increases the cost and complexity of FETs incorporating such layers.
  • PVDF polyvinylidenefluoride
  • PVDF films comprise crystalline regions that are ferroelectric, and non-crystalline regions that are not ferroelectric.
  • ferroelectric heterogeneity is likely to result in unacceptable performance of a FET incorporating a PVDF film making the use of such films highly unattractive.
  • US-A-2003/0127676 discloses a non-volatile memory device with a ferroelectric gate insulator layer which has been deposited by spin-coating. PVDF and vinylidene fluoride-trifluor ethylene copolymers (P(VDF-TrFE)) are described as suitable materials ' for the gate insulator layer.
  • Murata et al. (Y. Murata et al, "Ferroelectric behaviour in polyamides of m-Xylylenediamine and dicarboxylic acids", Jpn. J. Appl. Phys. 34, p. 6458-6462 (1995)) describes the electric behaviour of a series of nylon-type polyamide films 8 to 45 ⁇ m thick formed by melt processing.
  • the films produced exhibited electric displacement/electric field hysteresis loops characteristic of ferroelectric materials, however, since the films exhibited this behaviour in the amorphous phase they are not strictly ferroelectric materials but should rather be considered as ferroelectric-like materials in line with the definition of this term set out above.
  • the thickness of Murata' s films alone makes them unsuitable for incorporation in to an OFET device.
  • An object of the present invention is to at least mitigate at least one or more of problems of the prior art.
  • a field effect transistor comprising source and drain electrodes separated by a semiconductor body region, and a gate electrode s eparated from s aid s emiconductor b ody r egion b y a g ate i nsulator region, wherein the gate insulator region comprises a non-crystalline, preferably solution-processed, organic ferroelectric-like material.
  • This aspect of embodiments of the present invention thus provides a field effect transistor comprising a non-crystalline, preferably solution-processed, organic insulator region, which exhibits ferroelectric-like behaviour rather than an inorganic insulator region, which exhibits ferroelectric behaviour.
  • the term 'ferroelectric-like' will be used herein to refer to non-crystalline (i.e. amorphous) materials that exhibit a similar electric displacement/electric field hysteresis (D-E), and thereby a similar remanent polarisation, to ferroelectric materials but do not possess a crystalline structure and do not necessarily possess the same thermodynamic properties, that is, a thermodynamic phase associated with ferroelectricity.
  • Ferroelectric materials according to embodiments of the present invention do not exhibit a Curie temperature. Instead, the D-E disappears above the glass transition temperature.
  • the polarisation according to embodiments of the present invention is not permanent, that is, it can be changed by application of an appropriate electric field. It is to be understood that the term 'ferroelectric-like' is not intended to encompass electret materials.
  • a transistor in accordance with an embodiment of the present invention can be used in memory devices to store one bit per one component and the memory is permanent but re- writeable. Poling the gate once into the "on” or "off bias state switches the transistor into the respective state. It will remain in that state as long as no new gate bias is applied. When a new gate bias is applied memory can be erased or reset at will.
  • embodiments of the present invention can provide significant advantages over flash memory in terms of the power required to write and delete memory, the speed of operation, and the complexity of construction of the device.
  • a transistor in accordance with an embodiment of the present invention will also be a good candidate for LCD and OLED driver electronics because its fabrication should be compatible with the LCD/OLED fabrication process. Furthermore such devices will no longer incorporate a capacitor. Therefore capacitor leakage will be eliminated and the fabrication of displays (e.g. active matrix displays) which require several thousand pixels will be simplified significantly. Removing the need to refresh the device through not incorporating capacitors which need to be repeatedly refreshed, will reduce the amount of energy drawn from the power supply. This will also improve the performance of smart cards which will not need to be permanently connected to a power supply to refresh memory and will only require power when the memory is altered.
  • the ferroelectric-like material comprises at least one type of polymer.
  • the ferroelectric-like material may be comprised substantially of one type of polymer or may comprise a blend of two or more different types of polymer.
  • the ferroelectric-like material may comprise hydrogen bond donor and hydrogen bond acceptor groups.
  • the ferroelectric-like material is preferably a polyamide and may be formed from the condensation of a diamine and a dicarboxylic acid. It is preferred that the diamine comprises an aromatic group, more preferably the diamine is xylenediamine and most preferably the diamine is m-xylenediamine.
  • the dicarboxylic acid preferably comprises an aliphatic hydrocarbon moiety linking the two carboxylic acid groups. The dicarboxylic acid may comprise up to 13 carbon atoms, 5 to 11 carbon atoms or 6 carbon atoms. It will be appreciated by those skilled in the art that MXD6 comprises a ferroelectric-like polarisation hysteresis in its amorphous state due to hydrogen bond alignment see, for example, Y.
  • the ferroelectric-like material comprises repeating unit having the formula:
  • n 4
  • the polymer is poly(m-xylylenediamine-alt-adipic acid).
  • the insulator region should be of sufficient thickness to ensure that it contains no pinholes. For many applications it will be desirable to make the insulator region as thin as practically possible. However, in certain circumstances (e.g. if a larger memory window was required) a slightly thicker insulator region would be desirable. The thickness of the insulator region influences the memory window of the device
  • the thickness of the insulator is influenced by the solution concentration, a fabrication spin speed and solution temperature. It is thought that the solution concentration has a strong effect on the crystallinity of the insulator. Therefore, various thickness can be achieved by varying the above.
  • the insulator region has a thickness in the range 50 to 400 nm. Such thicknesses provide a memory window of approximately 5 V to 40 V depending on the application.
  • the insulator region may have a thickness of up to approximately 350 nm. In further preferred embodiments of this aspect of the invention the insulator region has a thickness in the range 100 to 300 nm, more preferably in the range
  • the insulator region should have a surface roughness, which is as low as possible. Preferably the insulator region has a surface roughness equal to or less than 5 nm.
  • the semiconductor body region comprises an organic semiconductor material.
  • any known inorganic semiconductor may be used in the device according to the present invention.
  • the semiconductor body region m ay c omprise a p -type s emiconductor m aterial.
  • a transistor in accordance with an embodiment of the present invention may additionally comprise a substrate region, which may comprise glass or plastic.
  • the gate electrode preferably comprises indium tin oxide or a synthetic metal (e.g. poly(ethylene dioxythiophene)-poly(styrene sulfonic acid) (PEDOT/PSS)), although any suitable material may be used e.g. polyaniline (PAni) emeraldine salt or a metal as such aluminium or gold.
  • At least one of the source and drain electrodes comprises a material selected from the group consisting of PEDOT/PSS, polyaniline (PAni) emeraldine salt, gold, calcium, silver, magnesium, tin, aluminium, alloys comprising one or more of the aforementioned materials, or any other suitable material.
  • a second aspect o f e mbodiments o f the p resent invention there i s p rovided a m ethod o f fabricating a field effect transistor comprising the steps of: a) forming a gate electrode; b) forming a gate insulator region; c) forming a semiconductor body region separated from said gate electrode by said gate insulator region; and d) forming source and drain electrodes separated from each other by said semiconductor body region,
  • the gate insulator region comprises a solution processed non-crystalline organic ferroelectric- like material.
  • steps a)-d) may be carried out in any convenient order to produce the desired transistor structure.
  • the order of steps may be a), b), c), d), or a), b), d), c), or alternatively d), c), b), a).
  • the inventive method is compatible with the deposition of organic semiconductors on top of the ferroelectric-like non-crystalline gate insulator.
  • steps a) - d Further steps may be performed so as to modify the structure formed in steps a) - d), e.g. surface modification of the gate insulator, modification of the gate insulator bulk, modification of the electrode/semiconductor interface, modification of the semiconductors etc.
  • the gate insulator region may comprise a plurality of insulator materials.
  • Suitable ferroelectric-like materials for use in the second aspect of the invention are described above in relation to the first aspect of the invention.
  • step b) comprises solution phase deposition, and more preferably step b) comprises spin- casting, although it will be evident to the skilled person that any number of alternative techniques may be used to form the gate insulator region, such as inkjet printing, or dip coating.
  • the spin-casting may be carried out at a speed in the range 100 to 10000 rpm, at a speed in the range 3000 to 5000 rpm, or at a speed of approximately 4000 rpm. It is preferred that the spin-casting is carried out over a period of time in the range 20 seconds to 15 minutes, over a period of time in the range 5 to 11 minutes, or over a period of time of approximately 8 minutes.
  • the non-crystalline organic ferroelectric-like material is formed from a solution of a precursor of said ferroelectric-like material in a suitable solvent (e.g. hexafluoroisopropanol, formic acid, trifluoroacetic acid and sulfuric acid, phenol/ethanol (as a 4:1 by volume mixture)).
  • a suitable solvent e.g. hexafluoroisopropanol, formic acid, trifluoroacetic acid and sulfuric acid, phenol/ethanol (as a 4:1 by volume mixture).
  • suitable precursors to the ferroelectric-like material comprise the various embodiments of the ferroelectric-like materials set out above in respect of the first aspect of the present invention but which cannot be termed ferroelectric-like materials since they will not exhibit ferroelectric-like properties by virtue of being in a solution phase.
  • Suitable precursors thus include a polymer or a blend of the two or more different polymers, which may comprise hydrogen bond donor and acceptor groups.
  • a precursor is preferably a polyamide and may be formed by condensation of a diamine and dicarboxylic acid. It is preferred that the diamine comprises an aromatic group, more preferably the diamine is xylenediamine and most preferably the diamine is m- xylenediamine.
  • the dicarboxylic acid preferably comprises an aliphatic hydrocarbon moiety linking the two carboxylic acid groups. The dicarboxylic acid may comprise up to 13 carbon atoms, 5 to 11 carbon atoms or 6 carbon atoms.
  • n 4
  • the polymer is poly(m-xylylenediamine-alt-adipic acid).
  • the concentration of the precursor in said solution is preferably in the range 20 to 70 mg/ml. More preferably the concentration of the precursor in said solution is in the range 30 to 60 mg/ml, and most preferably the concentration of the precursor in said solution is approximately 35 mg/ml.
  • the solvent is preferably an organic acid, or an organic solvent.
  • the solvent may comprise an aromatic group and the solvent is preferably o-cresol or m-cresol. It is particularly preferred that the solvent is m- cresol.
  • the precursor may be dissolved in the solvent at room temperature (i.e. a temperature of approximately 20°C), given a sufficient period of time, it is preferable that the precursor is dissolved in the solvent at a temperature in the range 20 to 70 °C, more preferably at a temperature in the range 40 to 60 °C, and yet more preferably at a temperature of approximately 50 °C.
  • the solution of the precursor is filtered prior to formation of the gate insulator region.
  • the solution of the precursor may be filtered at a temperature in the range 50 to 100°C prior to formation of the gate insulator region.
  • the solution of the precursor may be filtered at a temperature in the range 70 to 80°C prior to formation of the gate insulator region.
  • the solution of the precursor may be filtered through any desirable number of suitable filters.
  • the solution of the precursor is filtered through a first syringe-mounted filter, which preferably has a pore diameter of approximately 5 ⁇ m.
  • the solution of the precursor which has been filtered through the first syringe-mounted filter is then filtered through a second syringe-mounted filter having a narrower pore diameter than the first filter.
  • the second syringe-mounted filter may have a pore diameter of approximately 0.45 ⁇ m.
  • the semiconductor body region may be formed in step c) by thermal evaporation or spin casting.
  • the gate electrode is formed at least in part on a substrate region. It is further preferred that the gate insulator region is formed at least in part on the gate electrode. The semiconductor body region may be formed at least in part on the gate insulator region.
  • figure 1 is a schematic representation of a transistor device in accordance with a first embodiment
  • figure 2 is a schematic representation of the device of figure 1 prepared in accordance with example 1 showing how to turn the device "on” by applying a gate voltage
  • figure 3 is a schematic representation of the device of figure 1 prepared in accordance with example 1 showing how the device remains in the "on” state when the gate voltage is zero
  • figure 4 is a schematic representation of the device of figure 1 prepared in accordance with example 1 showing how to turn the device "off
  • figure 5 is a schematic representation of the device of figure 1 prepared in accordance with example 1 showing how the device remains in the "off state when the gate voltage is zero
  • figure 6 is a circuit diagram representing the arrangement of apparatus used to test the device of figure 1 prepared in accordance with examples 1 and 2
  • figure 7 is a graphical representation of the transfer characteristics of the device of figure 1 prepared in accordance with
  • MXD6 spherulites in the unwanted crystalline phase spun from a 40 g/1 solution (a) 2D image shows spherulites and the grain boundaries in between, (b) 3D profile of the same image, visualizing the roughness of 18 nm root-mean-square, 150 nm base to peak; figure 11 shows AFM images of amorphous MXD6 layers according to embodiments; Figures 11(a) and 11(b).10 x 10 ⁇ m 2 AFM images of amorphous MXD6 layers, (a) Cast from a 50g/l solution, roughness:
  • a transistor 1 comprises a glass substrate 2 with an indium tin oxide gate electrode 3 formed thereon.
  • a thin layer of a non-crystalline gate insulator material 4, MXD-6, is supported on the substrate/gate electrode layer 2, 3.
  • a semiconductor layer 5 comprised of a p-type organic semiconductor, pentacene, is supported on the insulator layer 4, and gold source and drain electrodes 6, 7 are formed on the semiconductor layer 5. Details of two non-limiting examples of methods for fabricating the transistor 1 are set out below in examples 1 and 2.
  • Figure 2 shows the operation of switching the transistor 1 on when the transistor has been prepared in accordance with example 1.
  • the device as drawn is a p-channel FET, but it will be appreciated that this embodiment i s f or i llustration o nly a nd a transistor in a ccordance w ith an e mbodiment o f the present invention may also comprise an n-channel FET. If the voltage between the source 6 and the drain 7 is kept constant, a current may flow between the drain 7 and the source 6 if an accumulation layer is induced in the body region 5. -40V is applied between the gate region 3 and the body region 5 polarising the insulator layer 4.
  • the effect is to induce an accumulation layer in the body region 5 adjacent the insulator layer 4 between the drain 7 and the source 6.
  • Arrows 8 show the insulator layer 4 being polarised in a first direction creating an electric displacement in a first direction i.e. from the gate region 3 to the body region 5.
  • the arrows 8 point from positive to negative polarity.
  • the current flowing between the drain and the source increases.
  • poling the gate voltage to a negative voltage will polarise the ferroelectric-like material layer in a first direction, which induces holes in the semiconductor body region by driving out electrons allowing current to flow.
  • n-channel transistor in accordance with the present invention the polarity of the voltage that must be applied to the gate to create an accumulation layer will be reversed to that described above. Furthermore, for current to flow in an n-channel transistor in the "on" state the drain voltage must be reversed. Additionally for an n-channel transistor in accordance with an embodiment of the present invention the polarisation of the insulator that induces an accumulation layer in the semiconductor body region will be reversed.
  • Figure 3 shows that when the voltage applied to the gate region 3 is returned to ground the insulator layer 4 retains a remanent polarisation and the associated electric displacement in the body region 5 remains. The accumulation layer remains and current continues to flow between the drain 7 and the source 6. Arrows 9 show that the insulator layer 4 remains polarised in the first direction creating an electric displacement in the first direction, in the absence of an applied gate voltage corresponding to the remanent polarisation.
  • pentacene as the semiconductor the majority of charge carriers will be holes.
  • Figure 4 shows that when 40V is applied between the gate region 3 and the body region 5 of the transistor 1 prepared in accordance with Example 1 the polarity of the insulator layer 4 reverses. This has the effect of removing the accumulation layer in the body region 5 and reducing the current flowing from the drain 7 to the source 6.
  • Arrows 10 show the insulator layer 4 being polarised in a second direction, opposite to the first direction creating an electric displacement in the second direction. If the gate voltage is then poled to a positive voltage the electric displacement of the ferroelectric-like material layer is first zeroed when the applied positive voltage is large enough to reach the coercitive field of the ferroelectric-like material and then reversed when the positive voltage is increased beyond the voltage required to reach the coercitive field. The effect is that the accumulation layer is removed and therefore the current that can flow from the drain to the source is considerably reduced and the device 1 is in the "off state.
  • Figure 5 shows that when the voltage applied to the gate region 3 is returned to zero the insulator layer 4 retains its remanent polarisation while the accumulation layer is removed, inhibiting current flow between the drain 7 and the source 6 and therefore the device remains in the "off state.
  • Arrows 11 show that the insulator layer 4 remains polarised in the second direction creating an electric displacement in the second direction, in the absence of an applied gate voltage.
  • the inventive device may store a logical high or low condition depending on the direction in which the gate has most recently been poled.
  • a voltage is applied to the drain region with respect to the source region.
  • a current sensor senses whether the current flowing through the transistor is high or low and registers a logic high or logic low condition respectively.
  • a display pixel will light-up or not light-up. In essence, during use the device 1 would be cycled between the situations shown in Figures 3 and 5.
  • This approach has significant advantages over the traditional use of a conventional FET in conjunction with a storage capacitor for memory devices. It does not involve a capacitor to store the charge, which may discharge over time. As such a transistor in accordance with an embodiment of the present invention does not need to be periodically refreshed in order to store the logic state. The circuit will thus require no power other than during a read or write operation as in accordance with conventional ferroelectric gate insulator FETs.
  • Transistors 1 prepared in accordance with Examples 1 and 2 were tested using two Keithley 2400 (denoted 12 in figure 6) source and measure units, one for applying a gate voltage, and one for applying a drain voltage and simultaneously measuring the resulting drain current.
  • the ground of the two Keithley units 12 was linked and connected to the source contact.
  • the electronic symbol of a p-type, accumulation mode MESFET has been used to represent the inventive device 1 under test as we are currently unaware of a standardised symbol for a ferroelectric FET.
  • the memory effect of the transistor 1 was characterized by holding the drain voltage constant and varying the gate voltage while reading the current between source and drain.
  • the two memory hysteresis curves illustrated in the lower section of figure 8 are essentially the same which illustrates that the memory window of the device 1 in accordance with an embodiment of the present invention is due to a genuine remanent polarisation that does not depend on the write or read speeds.
  • Such high voltages were used when testing the device 1 prepared in accordance with example 1 due to the thickness of the insulator layer.
  • the thickness of the layer was chosen to ensure that it did not contain any pinholes.
  • the results presented in relation to the device 1 prepared in accordance with example 2 illustrate that the method forming the second aspect of the present invention is eminently suitable to be adapted to produce thinner insulator layers, which use smaller gate voltages and provide smaller memory windows.
  • FIG. 7 shows the associated transfer characteristic of the transistor 1 prepared in accordance with examples 1 and 2 respectively. Referring to figure 7, starting at point 13 this shows a device in the "off state with no voltage applied to the gate and minimal leakage current flowing from the drain to the source. When the voltage applied to the gate is ramped to -40V the drain to source current increases to point 14. As the gate voltage is returned to zero
  • the drain to source current reduces slightly as the electric displacement is lower resulting from the polarised insulator layer compared to that present when the gate voltage is at -40 V.
  • a s the gate voltage is ramped to +40V the drain / source current decreases to point 16, which is substantially the same current level as at point 13. As the positive gate voltage is removed the drain / source current remains low.
  • the key feature of the behaviour of the device 1 prepared according to Example 1 as depicted in figure 7 is that the current at point 15 (after negative pulsing of the gate voltage) is 5.5 times higher than at point 13 (after positive pulsing of the gate voltage) even though the gate voltage at points 13 and 15 is zero.
  • device 1 prepared according to Example 1 exhibits a 'memory ratio' of 5.5.
  • the term 'memory ratio' shall be used herein to refer to the ratio of the source-drain current at zero gate voltage after negative pulsing of the gate voltage compared to the source-drain current at zero gate voltage after positive pulsing of the gate voltage.
  • a memory ratio of 5.5 is a sufficient variation in current for a current sensor to register the difference between high and low current and thus record logic high and logic low respectively thus enabling the device 1 of Example 1 to perform a memory function.
  • the device 1 prepared according to Example 2 as depicted in the upper section of figure 8 exhibits a significantly increased memory ratio of 200, which represents a major improvement in performance and is comparable to conventional inorganic ferroelectric transistors.
  • the high remanent polarisation of 60 mC/cm 2 reported for MXD-6 (Y. Murata et al, Jpn. J. Appl. Phys.
  • Figures 1 - 5 show the transistor 1 constructed as a planar FET with the gate electrode lowermost on the substrate.
  • the insulator, semiconductor body and drain / source electrodes are shown as being placed on top of one another working upwards.
  • a transistor in accordance with an embodiment of the present invention may take any number of physical forms, in common with other forms of both ferroelectric transistors and traditional FETs.
  • the form of the device can be controlled by choosing a particular order for steps a) to d) as previously defined for fabricating the device.
  • a transistor in accordance with an embodiment of the present invention may include a planar layer o f s emiconductor m aterial d eposited on t op o f an i nsulator m aterial a s shown i n figures 1 1 o 5, however, planar structures with the gate uppermost may also be formed.
  • trench structures wherein the gate is formed in a trench etched into the body of the semiconductor through the source electrode and / or the drain electrode, and separated from these by an insulator layer lining the gate trench may be constructed.
  • Field effect transistor devices in accordance with embodiments of the present invention can be prepared according to the following non-limiting examples.
  • Step 1 Substrate And Gate Electrode
  • a glass substrate was purchased with indium-tin-oxide (ITO, a conductive, transparent metal oxide) sputtered upon it.
  • ITO indium-tin-oxide
  • the ITO was patterned using the following process.
  • the parts of the ITO electrode to be preserved were coated with a protective acid-resistant material in solution (which could subsequently be removed by acetone).
  • the protective layer was then dried and the substrate immersed in 30 % hydrochloric acid for 6 minutes to remove the non-protected ITO.
  • the protective layer was then removed by immersion in acetone.
  • the substrate was cleaned using the following procedure. Ultrasonic bath cleaning in acetone for 5 minutes followed by ultrasonic bath cleaning for 20 minutes in a 70 °C solution of deionised water with 3 % Helmanex cleaning agent. The substrate was then washed with de-ionised water and subjected to further ultrasonic bath cleaning in deionised water at 70 °C for 20 minutes. Finally, the substrate was washed with de-ionised water and then underwent ultrasonic bath cleaning in a 50 °C methanol bath for 15 minutes. Step 2 - Gate Insulating Layer
  • a polyamide polymer MXD-6 and m-Cresol were combined in a ratio of 50 mg of MXD-6 per 1 ml of m- Cresol and the m-Cresol heated to 50 °C and stirred to accelerate the dissolving process.
  • Complete dissolution of MXD-6 pellets yielded a very viscous solution of MXD-6. Dissolution takes between 8 and 12 hours depending on the exact temperature of the m-Cresol. If a different form of MXD-6 were used, such as powdered MXD-6 rather than pellets, the dissolution time would be significantly less than 8 hours.
  • the MXD-6 solution was then hot-filtered at 70 - 80 °C through a syringe with a fastened syringe filter of 5 ⁇ m pore diameter.
  • the MXD-6 solution was then spun cast onto the glass-ITO substrate, which had been preheated to the same temperature as that of the solution (i.e. approximately 70 °C), at 4000 rpm for 8 minutes.
  • the substrate with the gate insulator layer deposited thereon was placed in a vacuum oven at 1 Torr and 50 °C for 24 hours to let any remaining m-Cresol and humidity evaporate. This process provided a layer of MXD-6 of approximately 350 nm thickness with less than 5 nm surface roughness.
  • Pentacene was placed into a quartz basket, which in turn was placed into a compatibly shaped tungsten filament housed in an evaporation chamber.
  • the substrate with the gate insulator deposited thereon was placed into the chamber approximately 12 cm from the quartz basket with the gate insulator side facing the opening of the basket.
  • the chamber was then evacuated to a pressure of 2xl0 "6 Torr and pentacene thermally evaporated onto the gate insulator at a rate of 0.5 nm/s.
  • Step 4 Source And Drain Electrodes
  • the quartz basket and tungsten filament from step 3 were replaced with a molybdenum boat and 1 cm of 0.5 mm gold wire placed into the boat.
  • the substrate having insulator and semiconductor layers deposited thereon was placed 12 cm from the boat and a shadow mask positioned between the boat and the substrate so as to define electrode sizes of 2 mm x 2 mm (for both source and drain electrodes) and with channel lengths on one mask of 20, 40, 60, or 80 ⁇ m to provide four pairs of electrodes.
  • Gold was then evaporated at a pressure of 2xl0 "6 Torr and a rate of 0.1 nm/s to provide gold electrodes having a thickness of approximately 100 nm.
  • a glass substrate having an ITO gate electrode formed thereon was cleaned in accordance with the method described in Step 1 of Example 1.
  • Step 2 Gate Insulating Layer
  • a gate insulator layer was formed in accordance with Step 2 of Example 1 subject to the following two differences.
  • polyamide polymer MXD-6 and m-Cresol were combined in a ratio of 35 mg of MXD- 6 per 1 ml of m-Cresol.
  • the MXD-6 solution formed by dissolution of MXD-6 in m-Cresol was initially hot-filtered at 70 - 80 °C through a syringe with a fastened syringe filter of 5 ⁇ m pore diameter and subsequently hot-filtered through a syringe with a fastened syringe filter of 0.45 ⁇ m pore diameter. This process provided a layer of MXD-6 of approximately 210 nm thickness .
  • a semiconductor layer was formed as described in Step 3 of Example 1 subject to the following differences.
  • the evaporation chamber was evacuated to a pressure of 8x10 ⁇ 7 Torr and pentacene was thermally evaporated onto the gate insulator at a rate of 0.3 nm/s.
  • Step 4 Source And Drain Electrodes
  • Source and drain electrodes were formed as described in Step 4 of Example 1 save for the fact that gold was evaporated at a rate of 0.2 nm/s to provide the gold electrodes.
  • FET non-volatile memory field-effect transistor
  • the memory effect is provided by a polymer that exhibits ferroelectric-like characteristics in its amorphous phase - allowing the transistor to be built using techniques developed for organic transistors.
  • the memory exhibits channel resistance modulations and retention times close in performance to inorganic ferroelectric FETs (FEFETs), yet at a small fraction of the cost, suitable for low-cost circuitry.
  • ORGANIC (0PT0-)ELECTR0NICS have received substantial research and development attention from academia [1-3] and industry [4-6] during the last two decades.
  • organic FETs OFETs
  • current organic memory solution are unsuitable as they are either based on capacitors, thus volatile and power intensive, or necessitate very high voltages for the writing process, with retention times of less than three hours [10-11].
  • F erroelectric-like means t hat t he d isplacement v ersus e lectric f ield ( D-E) hysteresis exhibits the same shape as typical ferroelectric materials; yet the material does not exhibit a thermodynamic phase or crystallinity associated with ferroelectricity.
  • the ferroelectric-like property also does not show a Curie temperature; instead the D-E hysteresis disappears above the glass transition temperature.
  • the "FerrOFET" exhibited a memory ratio of 200 and a retention time of a few hours [19].
  • ITO Indium-tin-oxide
  • m-Cresol 99.3%, Aldrich
  • MXD6 films While solid MXD6 films stay amorphous below 150 C, films cast from solution can crystallize at room temperature, in the form of hexagonal spherulites (cf. [figure 10]), i.e. for concentrations at or below 40 g/1. The control of the solution concentration and deposition temperature is therefore imperative to prevent crystallization. The samples were then stored in vacuo for several hours to remove any remaining solvent.
  • the thickness of the MXD6 layer is influenced by the solution concentration,- which also has -a strong effect on the crystallinity of the film, the solution temperature, and the spin speed.
  • the substrates with the dried MXD6 films are then placed into a vacuum chamber, and pentacene (97%, Aldrich) is evaporated upon the samples at room temperature with a deposition rate of 1 A/s. ' The area onto which pentacene was evaporated was limited to 2x2 mm 2 with a shadow mask.
  • gold source and drain contacts were evaporated on top of the pentacene at 0.5 A/s.
  • the transistors were analyzed using two Keithley 2400 source-measure units to apply the drain voltage and gate voltage, and measure the drain current and the gate leakage current. These two Keithley have a constant offset current of -2 x 10 "10 A, which is therefore the smallest current measured reliably.
  • the drain current vs. gate voltage graphs, or transfer characteristics, of two "FerrOFETs" with different MXD6 gate insulator layers are shown in [figure 9].
  • Device 1 - shown as the main graph - is made of a layer of MXD6 spun from a 50 g/1 solution ( ⁇ 50C) filtered with an 0.2 ⁇ m syringe filter.
  • the gate insulator layer thus deposited is 350 nm thick, and is extremely uniform.
  • the root-mean-square (RMS) roughness is less than 0.8 nm, and the roughness base to peak is 2 nm (cf. [figure 11(a)]).
  • the scan voltage is -45 V to + 30 V, whereas the memory window, defined as the difference between the threshold voltage on the up sweep and down sweep, is 20 V.
  • the scan voltage was chosen as such that the "FerrOFET” reaches the point of polarization saturation.
  • the ratio between the scan voltage and the memory window is 0.27, a value comparable to inorganic FEFETs [15].
  • Leakage currents are very small as amorphous films usually have smaller leakage compared to crystalline films [21], and even thinner MXD6 films are possible.
  • the leakage currents in all "FerrOFETs” were below 10 "8 Acm "2 , and for more than 80% of the gate scan well below our detection limit of 10 "9 Acm "2 .
  • the “memory ratio" between the "on” current and the “off current at zero gate voltage, also called the channel resistance modulation, is 2.7 x 10 4 .
  • the memory ratio was measured at zero gate voltage, which is preferable over having to apply a sustain voltage, not uncommon in FEFETs [14-15].
  • the memory ratio of device 2 is, with a value of 500, two orders of magnitude smaller than for device 1.
  • it is the onset of crystallinity seen in [figure 11(b)] that reduced the memory ratio in device 2.
  • Murata et al. have shown that crystalline MXD6 shows a much smaller ferroelectric-like effect, likely due to a quenching of the alignment of the hydrogen bridge bonds in the crystal [22].
  • the pentacene morphology at the interface layer is less ordered in device 2 due to the rougher MXD6 surface. It is well known that the pentacene morphology strongly influences the mobility of the material, especially the morphology of the first few pentacene layers near the interface.
  • device 2 stays entirely off.
  • the increase in layer thickness from 50 nm (device l) to 150 nm brings forth a longer path from the injection electrode area to the accumulation layer. Therefore, a higher field is needed to start accumulating charges at the semiconductor/insulator interface, and this shifts the onset to more negative voltages.
  • the control of the pentacene layer thickness therefore allows the exact placement of the memory window.
  • the "FerrOFET” an MXD6/pentacene all 7 organic ferroelectric-like memory transistor, shows a very comparable performance with respect to the inorganic FEFETs researched in the last two years, at a very small fraction of the cost and production difficulty. This enables the "FerrOFET” to be the memory of choice for many organic electronics circuits.
  • a solution processable gate insulator that exhibits ferroelectric-like polarization in an amorphous phase will enable tight integration of the memory with OFETs in mobile, flexible, and cheap circuits.
  • embodiments of the present invention can be realised in the form of n or p type devices. Furthermore, embodiments can be realised in which the devices are enhancement mode or depletion mode devices.

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Abstract

L'invention concerne un transistor à effet de champ comprenant des électrodes de source et de drain séparées par une zone comprenant un corps semi-conducteur, et une électrode de grille séparée de ladite zone de corps semi-conducteur par une zone d'isolant de grille, cette zone d'isolant de grille comprenant un matériau organique non cristallin de type ferroélectrique, de préférence formé par un procédé à base de solutions (« solution processed »). L'invention concerne en outre un procédé permettant de fabriquer un transistor à effet de champ comprenant les étapes consistant à a) former une électrode de grille ; b) former une zone d'isolant de grille, c) former une zone comprenant un corps semi-conducteur séparée de ladite électrode de grille par ladite zone d'isolant de grille ; et d) former des électrodes de source et de drain séparées l'une de l'autre par ladite zone de corps semi-conducteur, de telle manière que la zone d'isolant de grille comprend un matériau organique non cristallin de type ferroélectrique formé à partir de solutions. Dans une forme de réalisation, ce transistor peut être utilisé dans des dispositifs à mémoire pour le stockage d'un bit par composant, cette mémoire étant permanente mais réinscriptible.
PCT/GB2004/003428 2003-08-07 2004-08-09 Transistor a effet de champ WO2005015653A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB0318522A GB2404785A (en) 2003-08-07 2003-08-07 Field effect transistor with organic ferroelectric gate insulator
GB0318522.0 2003-08-07
GB0406334.3 2004-03-22
GB0406334A GB2406437A (en) 2003-08-07 2004-03-22 Field effect transistor with organic ferroelectric gate insulator

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014199144A1 (fr) * 2013-06-10 2014-12-18 The University Of Sheffield Transistor à effet de champ magnéto-résistif
US9812449B2 (en) 2015-11-20 2017-11-07 Samsung Electronics Co., Ltd. Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance
US10679688B2 (en) 2018-04-16 2020-06-09 Samsung Electronics Co., Ltd. Ferroelectric-based memory cell usable in on-logic chip memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5060191A (en) * 1988-07-08 1991-10-22 Olympus Optical Co., Ltd. Ferroelectric memory
EP0460242A1 (fr) * 1989-12-27 1991-12-11 Nippon Petrochemicals Co., Ltd. Element electrique et procede de reglage de la conductivite
US20030127676A1 (en) * 2002-01-09 2003-07-10 Samsung Sdi Co., Ltd. Non-volatile memory device and matrix display panel using the same
US20030134487A1 (en) * 2002-01-15 2003-07-17 International Business Machines Corporation Method of forming a planar polymer transistor using substrate bonding techniques

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5060191A (en) * 1988-07-08 1991-10-22 Olympus Optical Co., Ltd. Ferroelectric memory
EP0460242A1 (fr) * 1989-12-27 1991-12-11 Nippon Petrochemicals Co., Ltd. Element electrique et procede de reglage de la conductivite
US20030127676A1 (en) * 2002-01-09 2003-07-10 Samsung Sdi Co., Ltd. Non-volatile memory device and matrix display panel using the same
US20030134487A1 (en) * 2002-01-15 2003-07-17 International Business Machines Corporation Method of forming a planar polymer transistor using substrate bonding techniques

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014199144A1 (fr) * 2013-06-10 2014-12-18 The University Of Sheffield Transistor à effet de champ magnéto-résistif
US9812449B2 (en) 2015-11-20 2017-11-07 Samsung Electronics Co., Ltd. Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance
US10679688B2 (en) 2018-04-16 2020-06-09 Samsung Electronics Co., Ltd. Ferroelectric-based memory cell usable in on-logic chip memory

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