WO2005015248A1 - Essai de signal de donnees numeriques au moyen d'un signal d'essai arbitraire - Google Patents

Essai de signal de donnees numeriques au moyen d'un signal d'essai arbitraire Download PDF

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Publication number
WO2005015248A1
WO2005015248A1 PCT/EP2003/050365 EP0350365W WO2005015248A1 WO 2005015248 A1 WO2005015248 A1 WO 2005015248A1 EP 0350365 W EP0350365 W EP 0350365W WO 2005015248 A1 WO2005015248 A1 WO 2005015248A1
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WO
WIPO (PCT)
Prior art keywords
signal
digital data
data signal
value
sampling
Prior art date
Application number
PCT/EP2003/050365
Other languages
English (en)
Inventor
Joachim Moll
Original Assignee
Agilent Technologies, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies, Inc. filed Critical Agilent Technologies, Inc.
Priority to JP2005507530A priority Critical patent/JP2007515816A/ja
Priority to PCT/EP2003/050365 priority patent/WO2005015248A1/fr
Priority to AU2003266412A priority patent/AU2003266412A1/en
Priority to EP03817954A priority patent/EP1654548A1/fr
Publication of WO2005015248A1 publication Critical patent/WO2005015248A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31708—Analysis of signal quality
    • G01R31/3171—BER [Bit Error Rate] test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/16—Spectrum analysis; Fourier analysis
    • G01R23/20—Measurement of non-linear distortion
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/26—Measuring noise figure; Measuring signal-to-noise ratio
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/203—Details of error rate determination, e.g. BER, FER or WER

Definitions

  • the present invention relates to digital data signal testing.
  • a standard characterization of digital circuits requires determining the so-called Bit Error Rate (BER), i.e. the ratio of erroneous digital signals (Bits) to the total number of regarded digital signals.
  • Bit Error Rate Testers such as the Agilent ® 81250 ParBERT Platform with Agilent ® E4875A User Software and Measurement Software both by the applicant Agilent Technologies, are provided to determine a so-called BER eye diagram as a two-dimensional graphical representation generated using a sweep over delay and threshold of an analyzer. The result is an eye pattern with a BER value dependent on the sampling point for a plurality of sampling points.
  • Each sampling point is determined by an absolute or relative time (e.g. with respect to corresponding transition of a clock signal - usually the system clock for generating the stimulus signals or a clock signal derived therefrom or from the response signal) and a threshold value for comparing the response signal with.
  • the BER eye diagram gives information which BER value can be expected depending on the position of the sampling point within the eye. Parameters like jitter, level noise, phase margin, and quality factor (Q-factor) can be calculated from the BER eye diagram.
  • the invention can be partly or entirely embodied or supported by one or more suitable software programs, which can be stored on or otherwise provided by any kind of data carrier, and which might be executed in or by any suitable data processing unit.
  • Software programs or routines are preferably applied to control the measurement sequence and to compute the eye diagram or certain parameters thereof, e.g. rise time, fall time, signal levels, jitter.
  • FIG. 1 shows a signal-analyzing unit for analyzing a digital test signal according to an example of the present invention.
  • Fig. 2 shows an example of ABER values determined for a plurality of sampling points.
  • Fig. 3A shows an example of the course of the determined ABER values at a fixed value tx of the relative time scale over the threshold values V.
  • Fig. 3B shows an example, wherein the course of the determined ABER values at the fixed value tx as in Fig. 3A is differentiated over the threshold values V.
  • FIG. 4 shows an example wherein multiple of diagrams as in Fig. 3B are depicted for different values of t.
  • a signal-analyzing unit 10 for analyzing a digital test signal 20 (as provided e.g. from a DUT) comprises a sampling path 30 receiving the test signal 20, and an analysis unit 80 adapted for receiving and jointly analyzing the output of the sampling 30.
  • the sampling path 30 comprises a comparator 50 for comparing the test signal 20 against a threshold value Vth and providing a comparison signal 50A as result of the comparison.
  • the comparator 50 provides as the comparison signal 50A a first value (preferably a HIGH signal) in case the test signal is greater than the threshold value and a second value (preferably a LOW signal) in case the test signal is smaller than the threshold value.
  • a sampling device 60 receives as input the comparison signal 50A together with a timing signal 70 comprising a plurality of successive timing marks.
  • the sampling device 60 is adapted to derive a value of the comparison signal for one or more (and preferably each) of the timing marks.
  • the sampling device 60 provides as an output a sampling signal 60A representing the derived value(s) of the comparison signal 50A over the respective timing mark(s).
  • the sampling signal 60A is then subject (directly or after further processing) to further analysis by an analysis unit 80 for comparing the sampling signal 60A with an arbitrary test signal, which might be stored in a memory 90. Further, the analysis unit 80 might store the sampling signal 60A (e.g. for later analysis) in a separate memory 95 (but maybe also in the memory 90).
  • a demultiplexer 65 and a divider 75 might be coupled before the inputs of the analysis unit 80 in order to decrease the data rate of the received signal.
  • the BER-logic is implemented in lower speed digital circuits, e.g. FPGAs, and thus the high-speed data stream is broken up into several lower speed signals. This procedure is called demultiplexing or deserializing and is done with the demultiplexer 65.
  • the divider 75 controls the demultiplexer 65 and delivers a lower speed clock to the analysis unit 80.
  • the timing signal 70 is derived from a clock signal CLK.
  • One or more appropriate timing units might be provided for generating the respective timing signal(s) comprising the timing marks from the clock signal CLK.
  • a timing unit 110 generates the timing signals from the clock signal CLK, which might be derived e.g. from internal clock signal, an external clock signal, from the test signal 20 (e.g. using clock data recovery schemes as well known in the art).
  • the timing unit 110 derives the timing marks from transitions in its received clock signal (preferably from either one of a rising or falling edges), and might further allow modifying the timing marks with respect to corresponding transitions in its received clock signal by controllably delaying the timing marks with respect to corresponding transitions.
  • the analysis unit 80 receives the sampling signal 60A as well as the timing signal 70.
  • the analysis unit 80 provides a joint analysis of the sampling signal 60A, thereby using knowledge about the timing signal 70 together with the threshold value Vth.
  • Varying the threshold value Vth allows the sampling device 60 to sample at each possible threshold value. Varying the relative (e.g. delay) time of the timing marks with respect to corresponding transitions of the clock signal CLK then allows to further analyze the test signal 20 along its time axes. Thus e.g. an eye diagram of the test signal 20 can be determined.
  • each value sampled corresponds with a sampling point represented by a threshold value Vth, and a timing point in the digital data signal 20.
  • the threshold value Vth is typically related with respect to a voltage level of the digital data signal 20.
  • the threshold value Vth may be related with respect to a difference signal as the difference between a normal signal of the digital data signal 20 and a complementary signal of the digital data signal 20, with the complementary signal being complementary to the normal signal. In that case, the comparator 50 compares the normal signal against the complementary signal of the digital data signal 20 received at its inputs.
  • the timing point can be a relative timing point and might be related a fixed value of a period, but is preferably related to a current value of the period in order to cover variations of the period of the digital data signal 20.
  • the embodiment of Fig. 1 substantially represents a standard Bit Error Rate Tester (BERT) as well known in art and disclosed in the aforementioned documents.
  • bit error rate BER
  • the analysis unit 80 compares the sampling signal 60A against an arbitrary test signal, and might determine therefrom a value of BER or derive further analysis therefrom. The analysis unit 80 interprets the comparison with the arbitrary test signal as an error in case the value of the sampling signal 60A does not substantially match with the corresponding value of the arbitrary test signal.
  • Such arbitrary test signal can be any kind of signal being independent of and/or non-correlated to the digital data signal 20, being unrelated to data content of the digital data signal 20, or having otherwise no deterministic relationship with the digital data signal 20.
  • the arbitrary test signal can be an arbitrary test value, e.g. a fixed logic value (such as a logic HIGH or LOW signal or any other logic level) in the simplest case.
  • the arbitrary test signal might also be a more complex signal such as a pseudo random binary sequence (PRBS), any kind of alternating signal such as a signal of alternating logic values (e.g. alternating between a logic HIGH and a logic LOW signal).
  • PRBS pseudo random binary sequence
  • the following description shall be based on a fixed logic value as the arbitrary test signal, so that the analysis unit 80 compares the sampling signal 60A against one logic value (HIGH or LOW).
  • the inventive comparing analysis can be provided as well with other and more complex arbitrary test signals.
  • the analysis can e.g. be executed individually for each value of the alternating logic values.
  • the arbitrary test signal shall be a fixed logic LOW, so that the sampling signal 60A always compares the sampling signal 60A against the logic LOW.
  • the analysis unit 80 thus interprets any deviation of the sampling signal 60A from the logic LOW as an error.
  • the analysis unit 80 can then determine a value of BER representing the ratio of errors detected by comparing against the arbitrary test signal per number of bits. It is noted that the thus determined BER value is different from different BER values determined by comparing against an expected error-free signal, since in latter case the content of the digital data signal 20 is considered into the analysis while in the former case (of the present invention) the arbitrary test signal is completely unrelated to the content of the digital data signal 20. For the sake of better distinguishing those BER values, the BER values determined by comparing against the arbitrary test signal shall be denoted in the following as Arbitrary Bit Error Rate (ABER).
  • ABER Arbitrary Bit Error Rate
  • the analysis unit 80 For determining the values of ABER, the analysis unit 80 counts in a sequence of the digital data signal 20 two of: the number of bits in the sequence, the number of errors detected in the sequence, and the number of error-free bits in the sequence as the bits where no error is detected.
  • the details of determining the values of ABER correspond to the determining of BER, which are well known in the art and need not be repeated herein.
  • Fig. 2 shows an example of ABER values determined for each one of a plurality of sampling points, each sampling point being determined by a respective value t of a relative time scale and a respective value V of a voltage scale.
  • the different values of ABER are represented using a gray scaling.
  • the inventive scheme for determining ABER is entirely different from the determining BER with conventional Bit Error Rate Testers, it will be appreciated that the representation as in Fig. 2 of the ABER eye-diagram resembles a conventional BER eye-diagram.
  • the analysis unit 80 can further analyze the determined ABER values in order to derive an indication of occurrences of the digital data signal 20 at a respective sampling point. Such analysis, however, might also be provided by a different (e.g. external unit) coupled to the analysis unit 80 The analysis is preferably done by differentiating a course of the determined ABER values e.g. over the threshold values. Such indication can be the number of occurrences, a distribution of occurrences, or a probability of occurrences.
  • Fig. 3A shows an example showing the course of the determined ABER values at a fixed value tx of the relative time scale over the threshold values V.
  • the fixed value tx shall be about in the middle of the time axis as in Fig. 2.
  • Fig. 3B shows an example, wherein the course of the determined ABER values at the fixed value tx as in Fig. 3A is differentiated over the threshold values V.
  • the y-axis depicts an indication of occurrences of the digital data signal 20 at a respective sampling point (each represented by the value tx and the respective threshold value V of the x-axis).
  • the indication of occurrences shall be the number of occurrences.
  • the analysis unit 80 might further process the received or determined information for graphically representing the derived indications of occurrences for different sampling points. Such processing, however, might also be provided by a different (e.g. external unit) coupled to the analysis unit 80.
  • the graphical representation can be, for example, an absolute or relative distribution of derived indications relative to the respective sampling points (e.g. timing points and threshold values or voltages of signal level), e.g. in an eye diagram. While the representation can show the respective values of the indications as determined, comprehension of the representation might be improved by dividing the values into ranges of values and assigning a specific type of representation (e.g. color and/or shading) to each range of values.
  • Fig. 4 shows an example wherein multiple diagrams as in Fig. 3B are depicted for different values of t, with the number of occurrences being represented by a gray scaling (here: from light gray to black with light gray representing the highest and black the lowest number of occurrences, background color is white representing areas where no occurrences are detected) applied for respective value ranges.
  • Fig. 4 thus represents the number of occurrences of the example curve of Fig. 2.
  • This representation substantially corresponds to representations available by use of an oscilloscope.
  • the ABER value in the middle of the eye is not always constant. This behaviour can also be seen by repeating a measurement at the same sampling point.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Dc Digital Transmission (AREA)

Abstract

Pour tester un signal de données numériques (20), une valeur (60A) dérivée du signal de données numériques (20) en un point d'échantillonnage est comparée dans une unité d'analyse (80) à une valeur correspondante d'un signal d'essai arbitraire. La comparaison est interprétée (80) comme une erreur lorsque la valeur dérivée ne correspond pas sensiblement à la valeur correspondante du signal d'essai arbitraire et le taux d'erreur sur les bits pour le signal de données numériques est déterminé.
PCT/EP2003/050365 2003-08-06 2003-08-06 Essai de signal de donnees numeriques au moyen d'un signal d'essai arbitraire WO2005015248A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2005507530A JP2007515816A (ja) 2003-08-06 2003-08-06 任意のテスト信号を使用するデジタルデータ信号のテスト
PCT/EP2003/050365 WO2005015248A1 (fr) 2003-08-06 2003-08-06 Essai de signal de donnees numeriques au moyen d'un signal d'essai arbitraire
AU2003266412A AU2003266412A1 (en) 2003-08-06 2003-08-06 Digital data signal testing using arbitrary test signal
EP03817954A EP1654548A1 (fr) 2003-08-06 2003-08-06 Essai de signal de donnees numeriques au moyen d'un signal d'essai arbitraire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2003/050365 WO2005015248A1 (fr) 2003-08-06 2003-08-06 Essai de signal de donnees numeriques au moyen d'un signal d'essai arbitraire

Publications (1)

Publication Number Publication Date
WO2005015248A1 true WO2005015248A1 (fr) 2005-02-17

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EP (1) EP1654548A1 (fr)
JP (1) JP2007515816A (fr)
AU (1) AU2003266412A1 (fr)
WO (1) WO2005015248A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1729448A2 (fr) * 2005-05-03 2006-12-06 Agere Systems, Inc. Procédé et appareil de génération de séquences de tests
US7447965B2 (en) 2005-05-03 2008-11-04 Agere Systems Inc. Offset test pattern apparatus and method
US10171127B2 (en) 2017-05-19 2019-01-01 Rohde & Schwarz Gmbh & Co. Kg Method, system and computer program for synchronizing pseudorandom binary sequence modules

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5166924B2 (ja) * 2008-03-11 2013-03-21 株式会社日立製作所 信号再生回路

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1241483A1 (fr) * 2001-03-16 2002-09-18 Agilent Technologies, Inc. (a Delaware corporation) Mesure du taux d'erreurs sur les bits
EP1298830A2 (fr) * 2001-09-28 2003-04-02 Agilent Technologies, Inc. Identifier et synchroniser des canaux permutés dans un testeur de taux d'erreur de bits de canaux parallèles

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1241483A1 (fr) * 2001-03-16 2002-09-18 Agilent Technologies, Inc. (a Delaware corporation) Mesure du taux d'erreurs sur les bits
EP1298830A2 (fr) * 2001-09-28 2003-04-02 Agilent Technologies, Inc. Identifier et synchroniser des canaux permutés dans un testeur de taux d'erreur de bits de canaux parallèles

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1729448A2 (fr) * 2005-05-03 2006-12-06 Agere Systems, Inc. Procédé et appareil de génération de séquences de tests
EP1729448A3 (fr) * 2005-05-03 2007-03-21 Agere Systems, Inc. Procédé et appareil de génération de séquences de tests
US7272756B2 (en) 2005-05-03 2007-09-18 Agere Systems Inc. Exploitive test pattern apparatus and method
US7447965B2 (en) 2005-05-03 2008-11-04 Agere Systems Inc. Offset test pattern apparatus and method
US10171127B2 (en) 2017-05-19 2019-01-01 Rohde & Schwarz Gmbh & Co. Kg Method, system and computer program for synchronizing pseudorandom binary sequence modules

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Publication number Publication date
EP1654548A1 (fr) 2006-05-10
JP2007515816A (ja) 2007-06-14
AU2003266412A1 (en) 2005-02-25

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