WO2005003962A2 - Verfahren zur umschaltung zwischen wenigstens zwei betriebsmodi einer prozessoreinheit sowie entsprechende prozessoreinheit - Google Patents
Verfahren zur umschaltung zwischen wenigstens zwei betriebsmodi einer prozessoreinheit sowie entsprechende prozessoreinheit Download PDFInfo
- Publication number
- WO2005003962A2 WO2005003962A2 PCT/DE2004/001299 DE2004001299W WO2005003962A2 WO 2005003962 A2 WO2005003962 A2 WO 2005003962A2 DE 2004001299 W DE2004001299 W DE 2004001299W WO 2005003962 A2 WO2005003962 A2 WO 2005003962A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- operating mode
- processor unit
- execution units
- memory area
- programs
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000015654 memory Effects 0.000 claims abstract description 97
- 230000001960 triggered effect Effects 0.000 claims abstract description 11
- 238000012544 monitoring process Methods 0.000 claims description 9
- 230000008859 change Effects 0.000 claims description 8
- 238000011156 evaluation Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 5
- 230000006870 function Effects 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 238000012937 correction Methods 0.000 description 3
- 101100325756 Arabidopsis thaliana BAM5 gene Proteins 0.000 description 2
- 102100031584 Cell division cycle-associated 7-like protein Human genes 0.000 description 2
- 101000777638 Homo sapiens Cell division cycle-associated 7-like protein Proteins 0.000 description 2
- 101150046378 RAM1 gene Proteins 0.000 description 2
- 101100476489 Rattus norvegicus Slc20a2 gene Proteins 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000003936 working memory Effects 0.000 description 2
- 101001106432 Homo sapiens Rod outer segment membrane protein 1 Proteins 0.000 description 1
- 101150065817 ROM2 gene Proteins 0.000 description 1
- 102100021424 Rod outer segment membrane protein 1 Human genes 0.000 description 1
- 101100524639 Toxoplasma gondii ROM3 gene Proteins 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/165—Error detection by comparing the output of redundant processing systems with continued operation after detection of the error
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/845—Systems in which the redundancy can be transformed in increased performance
Definitions
- control applications in particular in the field of motor vehicle control, such as engine control, brake control or steering and transmission, etc., but also in industrial applications such as automation or in
- the non-safety-critical programs or tasks are processed.
- Various non-safety-critical programs run on both execution units, that is to say CPUs 1 and 2 (101, 102). This includes, for example, the operating system itself for the second operating mode, i.e. the OSEK subsystem.
- the two execution units or CPUs thus share a non-volatile second memory area which, as described above, can be designed.
- each CPU has its own volatile memory area RAM1 and RAM2, 110, respectively
- an incorrect access is detected in the second operating mode, a corresponding error reaction can also be initiated here.
- an error response corresponding to the first operating mode is conceivable and can be predetermined. This is particularly useful because, in the event of incorrect access, security-critical memory areas may be accessed. On the one hand, this can be realized in that a connection to the second memory area is only established in the second operating mode and the connection to the first memory areas is capped in this operating mode or access to the first memory area is prevented in some other way and only allowed in the second memory area.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Quality & Reliability (AREA)
- Hardware Redundancy (AREA)
- Storage Device Security (AREA)
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
- Debugging And Monitoring (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
BRPI0411824-3A BRPI0411824A (pt) | 2003-06-24 | 2004-06-22 | processo para a comutação entre, pelo menos, dois modos de operação de uma unidade de processamento, bem como, unidade de processamento correspondente |
US10/560,962 US20070277023A1 (en) | 2003-06-24 | 2004-06-22 | Method For Switching Over Between At Least Two Operating Modes Of A Processor Unit, As Well Corresponding Processor Unit |
JP2006515276A JP4232987B2 (ja) | 2003-06-24 | 2004-06-22 | プロセッサユニットの少なくとも2つの動作モードを切替る方法および対応するプロセッサユニット |
EP04738748A EP1639454A2 (de) | 2003-06-24 | 2004-06-22 | Verfahren zur umschaltung zwischen wenigstens zwei betriebsmodi einer prozessoreinheit sowie entsprechende prozessoreinheit |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10328208.4 | 2003-06-24 | ||
DE10328208 | 2003-06-24 | ||
DE10332700.2 | 2003-07-18 | ||
DE10332700A DE10332700A1 (de) | 2003-06-24 | 2003-07-18 | Verfahren zur Umschaltung zwischen wenigstens zwei Betriebsmodi einer Prozessoreinheit sowie entsprechende Prozessoreinheit |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005003962A2 true WO2005003962A2 (de) | 2005-01-13 |
WO2005003962A3 WO2005003962A3 (de) | 2006-01-26 |
Family
ID=33566007
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2004/001299 WO2005003962A2 (de) | 2003-06-24 | 2004-06-22 | Verfahren zur umschaltung zwischen wenigstens zwei betriebsmodi einer prozessoreinheit sowie entsprechende prozessoreinheit |
Country Status (7)
Country | Link |
---|---|
US (1) | US20070277023A1 (de) |
EP (1) | EP1639454A2 (de) |
JP (1) | JP4232987B2 (de) |
KR (1) | KR20060026884A (de) |
BR (1) | BRPI0411824A (de) |
RU (1) | RU2006101719A (de) |
WO (1) | WO2005003962A2 (de) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006045800A1 (de) * | 2004-10-25 | 2006-05-04 | Robert Bosch Gmbh | Verfahren und vorrichtung zur synchronisierung in einem mehrprozessorsystem |
WO2006045775A1 (de) * | 2004-10-25 | 2006-05-04 | Robert Bosch Gmbh | Verfahren und vorrichtung zur umschaltung bei einem rechnersystem mit wenigstens zwei ausführungseinheiten |
WO2006135937A2 (en) * | 2005-06-13 | 2006-12-21 | Intel Corporation | Selective activation of error mitigation based on bit level error count |
WO2007017395A2 (de) * | 2005-08-08 | 2007-02-15 | Robert Bosch Gmbh | Verfahren und vorrichtung zum vergleich von daten bei einem rechnersystem mit wenigstens zwei ausführungseinheiten |
WO2008043652A2 (de) * | 2006-10-10 | 2008-04-17 | Robert Bosch Gmbh | Elektronisches system |
EP1914414A2 (de) | 2006-10-10 | 2008-04-23 | Robert Bosch Gmbh | Einspritzsystem und Verfahren zum Betreiben eines Einspritzsystems |
JP2009505181A (ja) * | 2005-08-08 | 2009-02-05 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | 少なくとも2つの処理ユニットと、データおよび/または指令のための少なくとも1つの第1のメモリもしくはメモリ領域とを有する計算機システム内で指令および/またはデータを記憶するための方法および装置 |
JP2009505179A (ja) * | 2005-08-08 | 2009-02-05 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | 少なくとも2つの実行ユニットを有する計算機システムにおいてレジスタのマーキングによってスタート状態を定める方法および装置 |
JP2009505182A (ja) * | 2005-08-08 | 2009-02-05 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | データ処理方法および装置 |
JP2009508188A (ja) * | 2005-08-08 | 2009-02-26 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | 少なくとも2つの実行ユニットを有する計算機システムにおけるメモリアクセスを制御する方法および装置 |
JP2009541887A (ja) * | 2006-10-10 | 2009-11-26 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | 複数の実行ユニットを有するシステムを切り替える方法 |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10349581A1 (de) * | 2003-10-24 | 2005-05-25 | Robert Bosch Gmbh | Verfahren und Vorrichtung zur Umschaltung zwischen wenigstens zwei Betriebsmodi einer Prozessoreinheit |
DE102005037213A1 (de) * | 2004-10-25 | 2007-02-15 | Robert Bosch Gmbh | Verfahren und Vorrichtung zur Umschaltung zwischen Betriebsmodi eines Multiprozessorsystems durch wenigstens ein externes Signal |
DE102005037230A1 (de) * | 2005-08-08 | 2007-02-15 | Robert Bosch Gmbh | Verfahren und Vorrichtung zur Überwachung von Funktionen eines Rechnersystems |
DE102005037244A1 (de) * | 2005-08-08 | 2007-02-15 | Robert Bosch Gmbh | Verfahren und Vorrichtung zur Steuerung eines Rechnersystems mit wenigstens zwei Ausführungseinheiten und mit wenigstens zwei Gruppen von internen Zuständen |
DE102005055067A1 (de) * | 2005-11-18 | 2007-05-24 | Robert Bosch Gmbh | Vorrichtung und Verfahren zum Beheben von Fehlern bei einem wenigstens zwei Ausführungseinheiten mit Registern aufweisenden System |
JP4784827B2 (ja) * | 2006-06-06 | 2011-10-05 | 学校法人早稲田大学 | ヘテロジニアスマルチプロセッサ向けグローバルコンパイラ |
US7941698B1 (en) * | 2008-04-30 | 2011-05-10 | Hewlett-Packard Development Company, L.P. | Selective availability in processor systems |
DE102008062594A1 (de) * | 2008-12-16 | 2010-07-01 | Diehl Aerospace Gmbh | Mehrkanal-Kontrollermodul |
US9081688B2 (en) * | 2008-12-30 | 2015-07-14 | Intel Corporation | Obtaining data for redundant multithreading (RMT) execution |
US9594648B2 (en) * | 2008-12-30 | 2017-03-14 | Intel Corporation | Controlling non-redundant execution in a redundant multithreading (RMT) processor |
JP2010198131A (ja) * | 2009-02-23 | 2010-09-09 | Renesas Electronics Corp | プロセッサシステム、及びプロセッサシステムの動作モード切り替え方法 |
US8375250B2 (en) * | 2009-03-04 | 2013-02-12 | Infineon Technologies Ag | System and method for testing a module |
WO2011101707A1 (en) * | 2010-02-16 | 2011-08-25 | Freescale Semiconductor, Inc. | Data processing method, data processor and apparatus including a data processor |
US9405637B2 (en) | 2011-01-18 | 2016-08-02 | Texas Instruments Incorporated | Locking/unlocking CPUs to operate in safety mode or performance mode without rebooting |
US9367438B2 (en) | 2011-04-21 | 2016-06-14 | Renesas Electronics Corporation | Semiconductor integrated circuit and method for operating same |
WO2014080245A1 (en) | 2012-11-22 | 2014-05-30 | Freescale Semiconductor, Inc. | Data processing device, method of execution error detection and integrated circuit |
DE102013218814A1 (de) | 2013-09-19 | 2015-03-19 | Siemens Aktiengesellschaft | Verfahren zum Betreiben eines sicherheitskritischen Systems |
JP6090094B2 (ja) * | 2013-10-02 | 2017-03-08 | トヨタ自動車株式会社 | 情報処理装置 |
US9760446B2 (en) * | 2014-06-11 | 2017-09-12 | Micron Technology, Inc. | Conveying value of implementing an integrated data management and protection system |
US9823983B2 (en) | 2014-09-25 | 2017-11-21 | Nxp Usa, Inc. | Electronic fault detection unit |
US9658793B2 (en) * | 2015-02-20 | 2017-05-23 | Qualcomm Incorporated | Adaptive mode translation lookaside buffer search and access fault |
US9858201B2 (en) | 2015-02-20 | 2018-01-02 | Qualcomm Incorporated | Selective translation lookaside buffer search and page fault |
JP6378119B2 (ja) * | 2015-03-16 | 2018-08-22 | 日立建機株式会社 | 制御コントローラ、ステアバイワイヤシステムおよび機械 |
US10063569B2 (en) * | 2015-03-24 | 2018-08-28 | Intel Corporation | Custom protection against side channel attacks |
US10002056B2 (en) | 2015-09-15 | 2018-06-19 | Texas Instruments Incorporated | Integrated circuit chip with cores asymmetrically oriented with respect to each other |
US9734006B2 (en) * | 2015-09-18 | 2017-08-15 | Nxp Usa, Inc. | System and method for error detection in a critical system |
RU2623883C1 (ru) * | 2016-02-18 | 2017-06-29 | Акционерное общество "Лаборатория Касперского" | Способ выполнения инструкций в системной памяти |
RU2634172C1 (ru) * | 2016-06-02 | 2017-10-24 | Акционерное общество "Лаборатория Касперского" | Способ передачи управления между адресными пространствами |
JP6356736B2 (ja) * | 2016-06-29 | 2018-07-11 | ファナック株式会社 | コントローラシステムおよび制御方法 |
US11535266B2 (en) * | 2017-07-13 | 2022-12-27 | Danfoss Power Solutions Ii Technology A/S | Electromechanical controller for vehicles having a main processing module and a safety processing module |
GB2579590B (en) | 2018-12-04 | 2021-10-13 | Imagination Tech Ltd | Workload repetition redundancy |
GB2579591B (en) | 2018-12-04 | 2022-10-26 | Imagination Tech Ltd | Buffer checker |
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WO2003010638A1 (de) * | 2001-07-26 | 2003-02-06 | Infineon Technologies Ag | Prozessor mit mehreren rechenwerken |
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2004
- 2004-06-22 EP EP04738748A patent/EP1639454A2/de not_active Ceased
- 2004-06-22 KR KR1020057024653A patent/KR20060026884A/ko not_active Application Discontinuation
- 2004-06-22 WO PCT/DE2004/001299 patent/WO2005003962A2/de active Application Filing
- 2004-06-22 JP JP2006515276A patent/JP4232987B2/ja not_active Expired - Fee Related
- 2004-06-22 RU RU2006101719/09A patent/RU2006101719A/ru not_active Application Discontinuation
- 2004-06-22 US US10/560,962 patent/US20070277023A1/en not_active Abandoned
- 2004-06-22 BR BRPI0411824-3A patent/BRPI0411824A/pt not_active IP Right Cessation
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WO2003010638A1 (de) * | 2001-07-26 | 2003-02-06 | Infineon Technologies Ag | Prozessor mit mehreren rechenwerken |
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Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006045800A1 (de) * | 2004-10-25 | 2006-05-04 | Robert Bosch Gmbh | Verfahren und vorrichtung zur synchronisierung in einem mehrprozessorsystem |
WO2006045775A1 (de) * | 2004-10-25 | 2006-05-04 | Robert Bosch Gmbh | Verfahren und vorrichtung zur umschaltung bei einem rechnersystem mit wenigstens zwei ausführungseinheiten |
US8090983B2 (en) | 2004-10-25 | 2012-01-03 | Robert Bosch Gmbh | Method and device for performing switchover operations in a computer system having at least two execution units |
WO2006135937A2 (en) * | 2005-06-13 | 2006-12-21 | Intel Corporation | Selective activation of error mitigation based on bit level error count |
WO2006135937A3 (en) * | 2005-06-13 | 2007-02-15 | Intel Corp | Selective activation of error mitigation based on bit level error count |
JP2009505182A (ja) * | 2005-08-08 | 2009-02-05 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | データ処理方法および装置 |
WO2007017395A3 (de) * | 2005-08-08 | 2007-07-26 | Bosch Gmbh Robert | Verfahren und vorrichtung zum vergleich von daten bei einem rechnersystem mit wenigstens zwei ausführungseinheiten |
US8196027B2 (en) | 2005-08-08 | 2012-06-05 | Robert Bosch Gmbh | Method and device for comparing data in a computer system having at least two execution units |
WO2007017395A2 (de) * | 2005-08-08 | 2007-02-15 | Robert Bosch Gmbh | Verfahren und vorrichtung zum vergleich von daten bei einem rechnersystem mit wenigstens zwei ausführungseinheiten |
JP2009505185A (ja) * | 2005-08-08 | 2009-02-05 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | 少なくとも2つの実行ユニットを有するコンピュータシステムにおいてデータを比較する方法およびデバイス |
JP2009505181A (ja) * | 2005-08-08 | 2009-02-05 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | 少なくとも2つの処理ユニットと、データおよび/または指令のための少なくとも1つの第1のメモリもしくはメモリ領域とを有する計算機システム内で指令および/またはデータを記憶するための方法および装置 |
JP2009505179A (ja) * | 2005-08-08 | 2009-02-05 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | 少なくとも2つの実行ユニットを有する計算機システムにおいてレジスタのマーキングによってスタート状態を定める方法および装置 |
JP2009508188A (ja) * | 2005-08-08 | 2009-02-26 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | 少なくとも2つの実行ユニットを有する計算機システムにおけるメモリアクセスを制御する方法および装置 |
WO2008043652A2 (de) * | 2006-10-10 | 2008-04-17 | Robert Bosch Gmbh | Elektronisches system |
JP2009541887A (ja) * | 2006-10-10 | 2009-11-26 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | 複数の実行ユニットを有するシステムを切り替える方法 |
WO2008043652A3 (de) * | 2006-10-10 | 2008-06-05 | Bosch Gmbh Robert | Elektronisches system |
JP4908587B2 (ja) * | 2006-10-10 | 2012-04-04 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | 複数の実行ユニットを有するシステムを切り替える方法 |
EP1914414A2 (de) | 2006-10-10 | 2008-04-23 | Robert Bosch Gmbh | Einspritzsystem und Verfahren zum Betreiben eines Einspritzsystems |
EP1914414A3 (de) * | 2006-10-10 | 2013-08-14 | Robert Bosch Gmbh | Einspritzsystem und Verfahren zum Betreiben eines Einspritzsystems |
Also Published As
Publication number | Publication date |
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BRPI0411824A (pt) | 2006-08-08 |
WO2005003962A3 (de) | 2006-01-26 |
US20070277023A1 (en) | 2007-11-29 |
RU2006101719A (ru) | 2007-07-27 |
KR20060026884A (ko) | 2006-03-24 |
JP4232987B2 (ja) | 2009-03-04 |
JP2007507015A (ja) | 2007-03-22 |
EP1639454A2 (de) | 2006-03-29 |
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