WO2005003960A2 - Architecture de processeur pour identification exacte d'index - Google Patents

Architecture de processeur pour identification exacte d'index Download PDF

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Publication number
WO2005003960A2
WO2005003960A2 PCT/EP2004/007175 EP2004007175W WO2005003960A2 WO 2005003960 A2 WO2005003960 A2 WO 2005003960A2 EP 2004007175 W EP2004007175 W EP 2004007175W WO 2005003960 A2 WO2005003960 A2 WO 2005003960A2
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WO
WIPO (PCT)
Prior art keywords
pointer
objects
processor
processor architecture
data
Prior art date
Application number
PCT/EP2004/007175
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German (de)
English (en)
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WO2005003960A3 (fr
Inventor
Matthias Meyer
Original Assignee
Universität Stuttgart
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universität Stuttgart filed Critical Universität Stuttgart
Priority to AT04740540T priority Critical patent/ATE480824T1/de
Priority to JP2006516089A priority patent/JP4763598B2/ja
Priority to KR1020067000018A priority patent/KR101116989B1/ko
Priority to DE502004011642T priority patent/DE502004011642D1/de
Priority to EP04740540A priority patent/EP1639475B1/fr
Priority to US10/563,122 priority patent/US8473722B2/en
Publication of WO2005003960A2 publication Critical patent/WO2005003960A2/fr
Publication of WO2005003960A3 publication Critical patent/WO2005003960A3/fr
Priority to HK06112643.0A priority patent/HK1092236A1/xx

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/35—Indirect addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/17—Embedded application

Definitions

  • the present invention relates to a processor architecture in which memory is accessed via pointers which refer to objects.
  • Bit patterns that could represent a pointer must also be considered a pointer to avoid releasing memory that is still in use.
  • no compacting methods may be used that move objects and update pointers.
  • the memory is fragmented without a compacting method.
  • a great deal of effort is required in the search and identification of pointers.
  • pointers in objects can be identified using type descriptions (type descriptors) that are contained in each object.
  • type descriptors type descriptions
  • a capability is associated with the associated object through a two-stage mapping process. For each object there is a unique entry in an object table that corresponds to the Location that describes the size and state of the object. Each object consists of two areas: a data area and an area for capabilities. This enables exact capability identification. Due to the lack of a register set and the double indirect addressing of an object via The iAPX 432 is extremely inefficient in terms of capabilities and object descriptors, and it does not perform automatic garbage collection itself. Garbage collection must be done in software and is not real-time capable.
  • the object of the present invention is to provide a processor architecture for object-based and object-oriented programs which enables inexpensive, precise pointer identification and thus clears the way for efficient and real-time automatic garbage collection, which are implemented entirely or partially in hardware can. DESCRIPTION OF THE INVENTION The object is achieved with the processor architecture according to claim 1. Advantageous configurations of the processor architecture are the subject of the subclaims or can be found in the following description and the exemplary embodiments.
  • the term word is understood as a data unit that can be loaded from the memory or stored in the memory by means of a single processor instruction.
  • An object is understood to mean a coherent set of memory words in which each word belongs exclusively to a single object.
  • a pointer is a word that refers to an object. The term zero represents a fixed pointer value that is used to refer to no object.
  • the memory is accessed exclusively via pointers which point directly to objects.
  • An object is excluded in a contiguous memory area. stored, ie the memory areas occupied by two objects must not overlap.
  • pointers in a pointer area and data in a data area are stored separately.
  • information about the length of the pointer area and the length of the data area is stored in each object. This length information is referred to below as attributes. With the help of the attributes it is possible at any time to determine the size of an object and to clearly differentiate the pointers and data in an object.
  • the present processor architecture provides separate pointer register and data register sets. Pointer registers are only intended for operations with objects such as memory accesses and are not used for other tasks.
  • the processor preferably ensures that each word identified as a pointer is either the
  • the processor architecture thus adheres to the fixed rule (system invariant) that on the one hand each memory word or register can be identified as to whether it is a pointer or not, and on the other hand each pointer value is either zero or contains the address of an existing object ,
  • system invariant enables the exact identification of the pointers in the system at every cycle time.
  • New objects are preferably created using a special object creation command, to which the attributes of the object to be created are passed as parameters. This object creation command initializes all pointers of the pointer area with the zero value before the object can be accessed. In this way, the system invariant is not violated.
  • the object creation command is implemented interruptibly, whereby when an object creation command is canceled, incompletely initialized objects are generated in such a way that the interrupted object creation command can be continued at a later time and that incompletely initialized objects are clearly identified by the processor become.
  • the processor architecture preferably supports constant objects that already exist as part of a read-only memory area before the program starts. Pointers to constant objects are uniquely identified by the processor.
  • an area of the memory is preferably reserved for a program stack in a known manner.
  • the program stack is subdivided into a pointer stack area and a data stack area, with the first position not occupied by the stack in each case by a Batch index is specified, which is managed in a reserved data register.
  • the batch indices of the currently inactive batches are preferably stored as attributes in the associated batch objects.
  • the stack objects are stored as so-called static objects, preferably not in the heap, but in a static memory area managed by the operating system, and pointers to such objects (static pointers) are identified in a special way.
  • each pointer register is preferably accompanied by an attribute register in which the attributes of the object are stored which belong to the object referenced by the pointer in the pointer register.
  • an additional pipeline stage is provided for loading the attributes.
  • an attribute cache is preferably used in this pipeline stage to accelerate the accesses. All other pipeline stages and functional units required for program execution as well as the usual optimizations such as instruction and data caches or units for jump prediction can be implemented in an implementation of the present processor architecture in accordance with the prior art.
  • 1 schematically shows the register model of the present processor architecture
  • 2 schematically shows the object model of the present processor architecture
  • 3 schematically shows the implementation of the program stack as a stack object
  • 4 shows a table with a classification of the pointer-related commands
  • 5 shows an example of the implementation of the object layout for the present processor architecture
  • 6 schematically shows a pointer register with attributes
  • 7 shows an example of the implementation of a pipeline for the present processor architecture (simplified illustration)
  • 8 shows the decomposition of pointer-related instructions on the stages of a pipeline according to FIG. 7
  • Fig. 9 is a schematic illustration of an example of the present device.
  • each memory word or register can be identified as to whether it represents a pointer or not, and 2. each pointer value is either zero or is uniquely assigned to an existing object.
  • the present processor architecture provides separate data and pointer register sets, as is shown schematically in FIG. 1.
  • the data registers shown in the right part are used as general-purpose registers, while the pointer registers shown in the left part are used to access objects in memory.
  • N p indicates the number of pointer registers, N d the number of data registers.
  • N p indicates the number of pointer registers
  • N d the number of data registers.
  • the memory model of the present processor architecture is object-based. Each object consists of a data area and a pointer area, which are strictly separated from each other.
  • Figure 2 shows the schematic structure of such an object with the corresponding pointer words in the pointer area (left part of the figure) and the data words in the data area (right part of the figure) of the object.
  • the number of data words in the data area is described with the ⁇ attribute ( ⁇ ⁇ 0), the number of pointers in the pointer area with the ⁇ attribute ( ⁇ ⁇ 0).
  • the size of an object described by the attributes is determined when the object is created and cannot be changed later.
  • the attributes are part of the object and are stored in this in a separate attribute area.
  • the part of the instruction set specific to the present processor architecture only includes pointer-related instructions including load and store instructions.
  • the design of other commands, such as arithmetic commands or commands for program control, can be selected independently of the architecture described and is not part of the present invention.
  • the instruction set of the architecture described has a special object creation instruction which is used to create a new object and a pointer to this object.
  • Allocate Object receives the values of the ⁇ and ⁇ attribute for the object to be created as arguments and places the pointer on the newly created object in one Pointer register. Each pointer word in the pointer area of the created object is initialized to zero before the pointer to the object becomes visible to the program. There is no command to delete an object. Objects can only be automated
  • Load and save commands are used to access words within an object.
  • the processor architecture provides different load and save commands for access to pointer words and data words.
  • the "Load Date” and “Save Date” commands move data words exclusively between data areas of objects and data registers.
  • Pointer "instructions move pointers only between pointer areas of objects and pointer registers.
  • the load and store instructions identify the memory word to be accessed using a pointer register containing the pointer to the object and an integer positive index
  • various "indexing types" can be used to calculate the index values, which link data registers, constant offsets and scaling factors, for example.
  • the attributes of an object can be queried using two "read attribute" commands.
  • FIG. 4 shows a summary of the pointer-related instructions defined by the present processor architecture and categorizes them according to whether they read, write or dereference pointer registers. The register that is being read, written or dereferenced is printed in bold.
  • the program stack is viewed as a stack object, which - like every object - has one data area and one Has pointer area and can thus be viewed as two separate stacks.
  • a pointer register is reserved to hold the pointer to the stack object.
  • a stack index is used in each of the two stack areas in order to divide the corresponding area into the actual stack and a currently unoccupied area. In the present example, the stack index relates to the first unoccupied storage location.
  • a batch index of 0 represents an empty batch. The two batch indexes are called the data batch index (dsix) and the pointer batch index (psix).
  • Each of these indices is kept in a specially reserved data register. If the stack object is treated like a normal object, the system cannot distinguish whether a pointer belongs to the currently occupied pointer stack or to the unoccupied part of the pointer stack area. Since each word in the pointer stack area is identified as a pointer, the unused area of the pointer stack area can contain many pointers that point to objects that are no longer required. A garbage collector could not release these objects because there are still pointers to these objects.
  • One possible solution to this problem is to overwrite each pointer value with zero as soon as the corresponding pointer is removed from the stack.
  • a solution is therefore chosen that has the dynamic size of a stack is taken into account.
  • the stack object as illustrated in FIG. 3, is described by two pairs of attributes, one pair ( ⁇ , ⁇ ) of the current stack size and a second pair (II, ⁇ ) of the maximum stack size.
  • the ⁇ attribute corresponds to the value of the pointer stack index psix, the ⁇ attribute to the value of the data stack index dsix.
  • Batch attributes II and ⁇ are kept in system registers that are not visible to user programs.
  • pointers with indices smaller than ⁇ are regarded as pointers.
  • Memory words within the stack are addressed by ordinary load and save commands. Words can be removed from the stack by decreasing the value of the corresponding stack index using ordinary arithmetic instructions.
  • a special command is provided for storing a pointer on the pointer stack, which, in a non-interruptible manner, first places the pointer in the first unoccupied memory location of the pointer stack area and increases the pointer stack index. This is also the only command that can be used to increase the pointer stack index.
  • the memory can only be accessed via pointers, and the only way to create pointers is to create new objects using the object creation command.
  • constant data that, for example, already exists as part of the program code before the program starts.
  • Constant data are constant character strings or structures generated by the compiler such as branch tables or type descriptions.
  • the present example of an advantageous embodiment of the processor architecture therefore introduces constant objects.
  • a constant object is an unchangeable object that is stored as part of the program code or in a special area that is reserved for constant objects.
  • constant pointers use a special "create constant pointer" command. Memory accesses via constant pointers are restricted to read accesses, and the pointer area of a constant object may only contain constant pointers or null pointers. Constant objects become ordinary Differentiate objects by a ⁇ attribute, which is provided to distinguish between special types of objects.
  • each pointer in a newly created object must be initialized with the zero value before the associated object creation command can be completed. Therefore, the execution time for the object creation command is not limited by a small time constant. This is not acceptable for hard real-time applications. In order to make the object creation command interruptible, the described are advantageous
  • Uninitialized objects are created only if the assignment command is interrupted before an object is completed. Pointers to uninitialized objects are only visible in operating system mode and must never be dereferenced. Uninitialized objects - like static and constant objects - are identified by the ⁇ attribute.
  • the advantageous embodiment of the processor architecture described by way of example consequently supports four different types of objects: normal dynamic objects, uninitialized dynamic objects, constant objects and static objects.
  • the ⁇ attribute is used to distinguish between the types of objects and can be one of the four values (norm, uini, const, stat). to take.
  • the ⁇ attribute can be stored in the pointer to an object and / or in the object itself.
  • Normal dynamic objects and uninitialized dynamic objects are located in the heap memory area, static objects in the static memory area and constant objects in the memory area provided for the program code and / or constant data. Since static and uninitialized objects are limited to operating system mode, they are referred to as system objects.
  • the four object types can be characterized by how they are handled by a compacting garbage collector.
  • Ordinary dynamic objects have to be searched for pointers and moved when compacted.
  • Static objects must be searched for pointers, but must not be moved.
  • Uninitialized objects have to be moved during compaction, but must not be searched for pointers, since they can contain invalid pointers.
  • constant cleaners don't have to search or move pointers for pointers.
  • a possible implementation of the proposed processor architecture is explained below by way of example.
  • a word size of 32 bits is assumed for the implementation.
  • the memory can be addressed byte by byte to enable byte and halfword access within the data area. Words must be aligned to addresses that can be divided by four.
  • An exemplary layout of an object in the memory is shown in FIG. 5. Each object consists of a data area, a pointer area and an attribute area. For reasons of efficiency, the objects are aligned with addresses that can be divided by eight, which may make it necessary to fill a space between two objects.
  • the attribute area which is invisible to user programs, contains the ⁇ and ⁇ attributes of the object.
  • the present implementation changes the definition of ⁇ and ⁇ slightly since they now describe the number of bytes instead of the number of words in the corresponding area. Since ⁇ must be a multiple of four, two bits remain unoccupied in the memory word used for the ⁇ attribute. These can be used to store the ⁇ attribute (or parts thereof) and / or from a memory cleaner.
  • the pointers directly contain the physical memory address of the object. Since the objects are aligned according to double words, the object address only occupies 29 bits of a pointer word. The remaining three bits can be used to store the ⁇ attribute (or parts thereof) and / or from a memory cleaner.
  • the effort for dereferencing a pointer register is as low as the effort for address generation in conventional architectures.
  • the area check itself is not associated with any loss of performance, since it can be carried out in parallel with the address calculation.
  • the attribute registers come at a price: when a pointer is loaded from memory, the associated attributes must also be loaded into the attribute registers.
  • the location of the attributes in the memory is only known when the pointer has been loaded.
  • this problem can be solved efficiently by an additional pipeline stage according to the usual storage stage.
  • This additional level is called the attribute level and uses an attribute cache to perform attribute accesses in most cases without sacrificing performance.
  • the structure of the attribute cache is that of an ordinary one
  • the attribute cache is addressed by the upper 29 bits of a pointer and enables the ⁇ and ⁇ attributes to be read or written in one single step.
  • the main difference to a data cache is the size of the cache lines. While cache lines in data caches usually comprise 8 words, one line of the attribute cache has a width of 2 words and contains only the attributes of a single object.
  • FIG. 7 shows the basic structure of the implemented pipeline and FIG. 8 shows the decomposition of all pointer-related commands to the individual pipeline stages. The processing of the two most complex commands is described by way of example.
  • Address generation unit Address Generation Unit
  • AGU Address Generation Unit
  • the memory address of the pointer to be loaded and in parallel carries out the runtime tests prescribed by the architecture, such as area checks and zero pointer tests.
  • the calculated address is used to read the pointer from the object cache.
  • the loaded pointer then addresses the attribute cache to load the attributes from the object pointed to by the loaded pointer. Finally, the loaded pointer will be loaded with the
  • the size of the object to be generated is determined with the aid of two data operands, which are passed on from the decoding stage to the execution stage.
  • the pointer generation unit PGU: Pointer Generation Unit
  • the PGU can very easily determine the start address of the new object by adding the object size to the content of a system register that always points to the last occupied word in the area of the heap that is used for creating new objects .
  • the PGU is supported by the AGU, which generates the addresses required for pointer initialization. With an object cache with cache lines of 8 words, up to 8 pointer words can be initialized simultaneously in one clock cycle.
  • the create instruction passes through the execution stage without delay if the start address of the object can be calculated within a clock cycle and if all pointers in the object belong to the same cache line. If not, the pipeline is stopped until initialization is complete or an interrupt occurs. Finally, the attributes of the newly generated object are written to the attribute cache and the pointer together with its attributes are written to the register set. If an interrupted object creation command arrives at the end of the pipeline, the state of the interrupted object creation is written into a system register and the incompletely initialized object is identified with the ⁇ attribute for uninitialized objects. Initialization is resumed as soon as the execution context (command sequence counter, system register) of the interrupted program is restored.
  • the functionality of the proposed architecture was based on a working prototype demonstrated.
  • the memory cleaner is implemented as a micro-programmed coprocessor that works closely with the pipeline of the main processor.
  • the synchronization between processor and coprocessor is completely implemented in hardware.
  • the processor and the coprocessor for the garbage collection are described in VHDL and synthesized together for a more modern programmable logic device.
  • FIG. 9 shows a schematic illustration of an example of the present device.
  • the memory cleaner is formed by a micro-programmable coprocessor 2.
  • the processor architecture according to the invention is implemented in the main processor 1.
  • Processor 1 and coprocessor 2 establish the connection to the main memory.
  • the synchronization between the main and coprocessor takes place on different levels.
  • the garbage collector locks or clears lines of the data and attribute cache if necessary to ensure cache coherence.
  • a hardware read barrier built into the processor pipeline can trigger interrupts in the garbage collector.
  • the garbage collector can also stop the main processor 1 in order to protect critical areas in the microcode.

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Abstract

L'invention concerne une architecture de processeur basée sur un objet, permettant une identification exacte d'index, telle que l'index et les données soient complètement séparés les uns des autres dans la mémoire et dans les registres du processeur. L'accès à la mémoire est obtenue exclusivement au moyen d'index se référant à des objets. Un objet comprend des régions séparées pour les index et les données, et un champ d'attributs pour la description de la longueur des deux régions. Les index dans les registres d'index, ainsi que les index dans les régions d'index des objets, renferment directement les adresses des objets auxquels ces index se rapportent. L'architecture de processeur selon l'invention permet l'intégration d'un nettoyage automatique de la mémoire qui peut être totalement ou partiellement effectuée par implémentation matérielle. Un nettoyage de mémoire en temps réel peut être réalisé de manière particulièrement efficace par implémentation matérielle.
PCT/EP2004/007175 2003-07-01 2004-07-01 Architecture de processeur pour identification exacte d'index WO2005003960A2 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
AT04740540T ATE480824T1 (de) 2003-07-01 2004-07-01 Prozessorarchitektur für exakte zeigeridentifizierung
JP2006516089A JP4763598B2 (ja) 2003-07-01 2004-07-01 プロセッサおよびデバイス
KR1020067000018A KR101116989B1 (ko) 2003-07-01 2004-07-01 정확한 포인터 식별을 위한 프로세서 아키텍처
DE502004011642T DE502004011642D1 (de) 2003-07-01 2004-07-01 Prozessorarchitektur für exakte zeigeridentifizierung
EP04740540A EP1639475B1 (fr) 2003-07-01 2004-07-01 Architecture de processeur pour identification exacte d'index
US10/563,122 US8473722B2 (en) 2003-07-01 2004-07-01 Processor architecture for exact pointer identification
HK06112643.0A HK1092236A1 (en) 2003-07-01 2006-11-17 Processor for exact pointer identification

Applications Claiming Priority (2)

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DE10329680A DE10329680A1 (de) 2003-07-01 2003-07-01 Prozessorarchitektur für exakte Zeigeridentifizierung
DE10329680.8 2003-07-01

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WO2005003960A2 true WO2005003960A2 (fr) 2005-01-13
WO2005003960A3 WO2005003960A3 (fr) 2005-09-29

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EP (1) EP1639475B1 (fr)
JP (1) JP4763598B2 (fr)
KR (1) KR101116989B1 (fr)
CN (1) CN100517269C (fr)
AT (1) ATE480824T1 (fr)
DE (2) DE10329680A1 (fr)
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JP4763598B2 (ja) 2011-08-31
DE10329680A1 (de) 2005-02-10
KR101116989B1 (ko) 2012-03-14
CN100517269C (zh) 2009-07-22
JP2009514043A (ja) 2009-04-02
DE502004011642D1 (de) 2010-10-21
EP1639475A2 (fr) 2006-03-29
HK1092236A1 (en) 2007-02-02
WO2005003960A3 (fr) 2005-09-29
ATE480824T1 (de) 2010-09-15
US20080209149A1 (en) 2008-08-28
US8473722B2 (en) 2013-06-25
KR20060052771A (ko) 2006-05-19
EP1639475B1 (fr) 2010-09-08
CN1816802A (zh) 2006-08-09

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