WO2005003956A1 - Single memory with multiple shift register functionality - Google Patents
Single memory with multiple shift register functionality Download PDFInfo
- Publication number
- WO2005003956A1 WO2005003956A1 PCT/IB2004/051061 IB2004051061W WO2005003956A1 WO 2005003956 A1 WO2005003956 A1 WO 2005003956A1 IB 2004051061 W IB2004051061 W IB 2004051061W WO 2005003956 A1 WO2005003956 A1 WO 2005003956A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- access
- read
- accesses
- data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
Definitions
- the present invention relates to a memory device having a shift register functionality, such as a FIFO (First-In-First-Out) memory, which can be used for coupling one or more data sources to a plurality of data processing devices.
- a shift register functionality such as a FIFO (First-In-First-Out) memory
- FIFO First-In-First-Out
- PRML Partial-Response Maximum-Likelihood
- PRML-based receivers allow to significantly increase the system capacity and/or margins or, equivalently, decrease costs while keeping the capacity and/or margins unchanged.
- PRML-based detection in advanced optical disc systems, such as DVD+RW (Read and Writeable Digital Versatile Disc) and DVR (Blue-ray Disc) is shown to decrease system sensitivity to noise, defocus and disc tilt.
- the PRML- based detection allows to relax the requirements on the mechanical and optical system components and, as a result, to achieve higher system robustness and lower production costs.
- the so-called Viterbi algorithm is considered to be the most efficient practical implementation of the PRML detector. However, the speed of the Viterbi algorithm is intrinsically limited because of the data-dependent feedback loop it contains.
- Compare-Select (ACS) operation has to be executed every clock cycle, and the next cycle cannot be started before the result of the ACS operation is available.
- an alternative approach has been suggested to improve the throughput of a Viterbi detector. This alternative approach is based on the idea of splitting an incoming data stream into several sub-streams and processing them in parallel.
- a parallel implementation of the Viterbi decoder for data read at high speed from a digital storage or transmission system such as an optical disc, a hard disc or tape in particular, requires the use of expensive and power-consuming high clock rate digital hardware.
- Such high clock rate digital hardware results for example from the requirement of having the different parallel data streams buffered in FIFO memory blocks.
- one unified memory block of capacity Z x B is usually cheaper than Z memory blocks of capacity B, so that it would be preferable to use one memory of a bigger capacity than many small ones.
- single-port memories of the same capacity are cheaper than their multi-port counterparts. Consequently, it is preferable to use single-port memories instead of multi-port ones.
- This object is achieved by a memory device as claimed in claim 1.
- the proposed architecture in which shift register accesses to predetermine register memory blocks are mapped to subsequent addresses in the global address space of the memory, allows to combine a plurality of FIFOs or other kinds of shift register memories in one embedded memory, such as a RAM (Random Access Memory). This implementation is most favourable in view of power consumption and area.
- the favourable implementation allows to replace a multi-port RAM by a single- port RAM of the same capacity.
- Such an implementation is not only even more favourable in terms of area and power, but also has a reduced cycle and access time.
- the access control means may comprise at least one address counter or any kind of finite state machine which generates the required address sequence. Thereby, a simple implementation for address generation can be provided.
- the address ranges of the predetermined register memory sections may comprise overlapping regions of a predetermined size. This provides the advantage that the capacity of the embedded memory is less than the total number of memory locations of all replaced FIFO blocks.
- overlapping regions can be advantageously used as training regions for Viterbi detectors, where an incoming data stream is splitted between several detectors in such a way that the sub-streams overlap.
- one detector has the overlapping region at the end of its sub-stream and another detector has the same region at the beginning of its sub-stream.
- the latter detector may use the overlap region for training purposes since the bit decisions can be supplied by the former one.
- the proposed scheme needs no special markers in the data stream, and can be used in applications where the data stream is already standardised and there is no possibility to include markers in it.
- the at least one access port may provide access to a plurality of data sources for writing data to respective ones of the register memory blocks, and to a plurality of data processing devices for reading data from the register memory blocks.
- the access control means may be arranged to provide alternate access for the data sources and the data processing devices.
- the data source accesses may be controlled to cycle through the global address space, and the processing device accesses may be controlled to cycle through the address range of the respective register memory section.
- This cyclic read and write operations facilitate address translation required for the read-out accesses.
- a buffer memory may be connectable to the at least one access port and to the memory, wherein a line width of the buffer memory and the memory is selected to be greater or equal the data width of the at least one access port multiplied by the sum of read accesses and write accesses per cycle.
- a single-port architecture can be provided, where the embedded memory is replaced by a memory block of less memory lines and correspondingly more bits per line.
- the data source or data sources provide(s) the write data to the embedded memory via the buffer memory.
- an entire line can be written to the embedded memory at each write cycle to thereby reduce the access frequency.
- Multi-port RAM devices can thus be replaced by single-port RAM devices of the same capacity, while providing a reduced cycle and access time.
- the number of write ports of the at least one access port may now differ from the number of read ports.
- the number of data symbols accepted by the memory device may differ from the number of data symbols produced in every cycle.
- Fig. 1 shows schematic functional block diagrams indicating a transfer from individual FIFO memory devices to a memory device according to the first preferred embodiment with embedded FIFO blocks
- Fig. 2 shows functional block diagrams indicating a transfer from an embedded multi-port memory structure to a single-port memory device according to the second preferred embodiment with buffered access
- Fig. 3 shows a schematic block diagram of an address generation functionality used in the first and second preferred embodiments
- Fig. 4 shows a schematic block diagram of an address translation functionality used in the second preferred embodiment
- Fig. 5 shows a table indicating a memory access schedule according a first implementation example
- Fig. 6 shows a memory access schedule according a second implementation example.
- the Z FIFO blocks each have a memory capacity B, they can be combined into the embedded memory block EM having a capacity of ZxB, wherein the FIFO accesses can be mapped to subsequent addresses in the global address space of the embedded memory block EM.
- the capacities of the FIFO blocks not necessarily have to be the same.
- Each FIFO block may have an individual specific capacity, which has to be considered in the implementation of the individual addressing schemes.
- the read and/or write accesses can be controlled by an access control unit A which supplies corresponding control signals and addresses to the embedded memory block EM.
- data units to be written to or read from the embedded memory block EM can be supplied via respective access ports PI to PZ.
- a Viterbi-based bit detector organised in such a way is transparent to the rest of the system and can be easily integrated into the existing data flow within an integrated circuit.
- Each of the sequential Viterbi decoders may be operated at a speed lower than the bit rate. The slower the speed of the Viterbi detectors is, the more Viterbi detectors are needed to run in parallel.
- the number of Viterbi detectors grows at least almost linearly with the ratio between the bit rate and the speed of the detectors. For such detector applications or even for other kinds of applications, it can be useful to create overlapping regions between the different FIFO memory sections of the embedded memory block EM.
- FIG. 2 shows a schematic functional block diagram of a second preferred embodiment in which the multi-port embedded memory block EM is replaced by a single- port embedded memory block EM with an additional buffer memory B.
- a multi-port memory block EM of M lines with N bits per line as shown in the left portion of Fig. 2 has to handle X write accesses and Y read accesses in every cycle. Therefore, the access ports PI to PZ comprise X write ports and Y read ports. This implies that two or more write ports may be assigned to one FIFO memory section or that one read port may be assigned to more than one FIFO memory section.
- the width of the buffer memory B can be defined as one sample width smaller than the width of the embedded memory block EM, i.e. a buffer width of Nx(L-l), so that the last access (which would otherwise have filled the buffer memory B) is directly transferred to the embedded memory block EM in parallel with the buffer contents without being buffered.
- the line width between the buffer memory B and the embedded memory block EM remains LxN.
- the accesses have to be aligned in such a way that a block of LxN bit is read all the time.
- a corresponding memory address AEM of the embedded memory block EM is stored in the look-up table and supplied to the embedded memory block EM.
- the address translation functionality may as well be implemented as an FSM which produces the required address sequence. In the case of FIFO memory sections, this FSM may again consist of two simple cyclic counters. It is noted that the above first and second embodiments can be implemented in a fully independent manner and do not require any increase in the clock frequency. In the following, a first example of an implementation of the preferred embodiments is described with reference to Figs. 5 and 6. The implementation may be used in a multiplexing or demultiplexing functionality of a parallel PRML bit detector such as a Viterbi detector.
- each FIFO memory section has to be able to accept four samples and to produce five samples in every cycle.
- the required memory capacity depends on the specific application. It is assumed that each FIFO memory section has a memory capacity of 300 bytes. In the case of non-overlapping FIFO memory sections, a total capacity of the embedded memory block EM would be 1500 bytes.
- the line width of the buffer memory B and the embedded memory block EM not necessarily correspond to the sum of the number of write accesses and read accesses.
- the parameter L has to be at least this sum. However, a higher value can be chosen for the parameter L e.g. if this value better matches to a suitable memory size of the embedded memory block EM, for example 1200 bytes.
- written data becomes available only after 13 cycles. It has to be noted that in cycle No. 3 of Fig. 5, the read data does not correspond to the data written one cycle earlier. There is always a delay of at least 13 cycles. In addition, after power-on, some time is needed to write data into the embedded memory block EM before "useful" data can be read. In a practical implementation, the resulting embedded memory block EM of the second preferred embodiment, excluding any buffers and address generators, has an area of 0.15 mm and consumes 0.951 mW/Mhz in CMOS 18 process. A comparable dual-port memory which suits the requirements of the application, i.e.
- the first output processing device Ol uses lines L0 to L2
- the second output processing device O2 uses lines L3 to L5
- the third output processing device O3 uses lines L6 to L8. Every even cycle, a write access takes place, and every odd cycle, a read access.
- the output samples are not necessarily in the same order as the input samples.
- a reading scheme "read L0" ⁇ “read LI” ⁇ “read L2” is used for the first output processing device 01.
- a reading scheme "read L4" ⁇ “read L5" ⁇ “read L3” is used for the second output processing device O2, while the initially read lines L4 and L5 are discarded after initialisation.
- the reading scheme is "read L7” — > “read L8” ⁇ "read L6", while the initially read lines L7 and L8 are discarded.
- the discarding functionality may be implemented by inserting some dummy data which does not represent any meaningful data in the beginning of the stream.
- lines LO to L8 are successively written in every even cycle starting with the first cycle (cycle No. 0).
- cycle No. 1 line L0 is read and supplied to the first output processing device Ol.
- cycle No. 3 line L4 is read and supplied to the second output processing device O2, while the content is discarded during the initial first reading operation.
- line L7 is read and supplied to the third output processing device 03, while the content is again discarded during the initial first reading operation for this third output processing device 03.
- line LI is read and supplied to the first output processing device Ol .
- line L5 is read and supplied to the second output processing device 02.
- the present invention can be applied to any parallel shift register structure in optical disc systems, such as Portable Blue (PB) or Small Form Factor Optical (SFFO), DVD, DVD+RW, DVR, or any future optical disc system.
- PB Portable Blue
- SFFO Small Form Factor Optical
- the present invention can be applied to magneto-optical systems, hard disc systems, digital tape storage systems, satellite and mobile communication systems, image processing systems and the like.
- PRML or Viterbi processing systems the present invention can be applied in the demultiplexing or interleaving functionality at the input side or as well in the multiplexing or de- interleaving functionality at the output side.
- the preferred embodiments may thus vary within the scope of the attached claims.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Error Detection And Correction (AREA)
- Static Random-Access Memory (AREA)
- Information Transfer Systems (AREA)
- Shift Register Type Memory (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006518442A JP4900800B2 (en) | 2003-07-02 | 2004-06-30 | Single memory with multiple shift register functions |
US10/562,887 US7774573B2 (en) | 2003-07-02 | 2004-06-30 | Single memory with multiple shift register functionality |
EP04744431A EP1644820B1 (en) | 2003-07-02 | 2004-06-30 | Single memory with multiple shift register functionality |
DE602004013977T DE602004013977D1 (en) | 2003-07-02 | 2004-06-30 | SINGLE MEMORY WITH MULTIPLE SHIFT REGISTER FUNCTIONALITY |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03101980 | 2003-07-02 | ||
EP03101980.5 | 2003-07-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005003956A1 true WO2005003956A1 (en) | 2005-01-13 |
Family
ID=33560838
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2004/051061 WO2005003956A1 (en) | 2003-07-02 | 2004-06-30 | Single memory with multiple shift register functionality |
Country Status (8)
Country | Link |
---|---|
US (1) | US7774573B2 (en) |
EP (1) | EP1644820B1 (en) |
JP (1) | JP4900800B2 (en) |
KR (1) | KR20060028706A (en) |
CN (1) | CN100485601C (en) |
AT (1) | ATE396447T1 (en) |
DE (1) | DE602004013977D1 (en) |
WO (1) | WO2005003956A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100817204B1 (en) | 2006-12-22 | 2008-03-27 | 재단법인서울대학교산학협력재단 | Method and apparatus for mapping flash memory |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI382426B (en) * | 2007-10-04 | 2013-01-11 | Realtek Semiconductor Corp | System and method for predicting cache access |
WO2012101760A1 (en) * | 2011-01-25 | 2012-08-02 | 富士通株式会社 | Memory control method and system |
CN103594109B (en) * | 2012-08-15 | 2017-09-15 | 上海华虹集成电路有限责任公司 | A kind of memory construction for substituting dual-port RAM |
US9430394B2 (en) * | 2013-12-12 | 2016-08-30 | Mediatek Singapore Pte. Ltd. | Storage system having data storage lines with different data storage line sizes |
JP6632876B2 (en) * | 2015-12-04 | 2020-01-22 | シナプティクス・ジャパン合同会社 | Buffer memory device and display drive device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4750154A (en) * | 1984-07-10 | 1988-06-07 | Prime Computer, Inc. | Memory alignment system and method |
GB2214759A (en) * | 1988-01-18 | 1989-09-06 | Plessey Co Plc | High speed digital data link |
US4879720A (en) * | 1988-03-10 | 1989-11-07 | M/A-Com Government Systems, Inc. | Decoder ring system |
EP0498065A2 (en) * | 1991-02-04 | 1992-08-12 | International Business Machines Corporation | Variable data stripe system and method |
US6526495B1 (en) * | 2000-03-22 | 2003-02-25 | Cypress Semiconductor Corp. | Multiport FIFO with programmable width and depth |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3824562A (en) * | 1973-03-30 | 1974-07-16 | Us Navy | High speed random access memory shift register |
US4862419A (en) * | 1983-11-10 | 1989-08-29 | Advanced Micro Devices, Inc. | High speed pointer based first-in-first-out memory |
JPH01269150A (en) * | 1988-04-20 | 1989-10-26 | Nec Eng Ltd | Buffering device |
DE69031220T2 (en) * | 1990-12-20 | 1998-02-12 | Ibm | High speed multi-port FIFO buffer circuit |
JPH04221491A (en) * | 1990-12-21 | 1992-08-11 | Nippon Telegr & Teleph Corp <Ntt> | Fifo circuit for cell |
JPH05258555A (en) * | 1992-03-17 | 1993-10-08 | Nec Corp | Fifo semiconductor memory |
US5812820A (en) * | 1995-09-29 | 1998-09-22 | Pacific Commware, Inc. | Virtual UART |
US5809339A (en) * | 1995-12-06 | 1998-09-15 | Cypress Semiconductor Corp. | State machine design for generating half-full and half-empty flags in an asynchronous FIFO |
US5712992A (en) * | 1995-12-06 | 1998-01-27 | Cypress Semiconductor Corporation | State machine design for generating empty and full flags in an asynchronous FIFO |
US5828992A (en) * | 1995-12-11 | 1998-10-27 | Unova Ip Corp. | Automated control system with bilingual status display |
US5627797A (en) * | 1995-12-14 | 1997-05-06 | Cypress Semiconductor Corporation | Full and empty flag generator for synchronous FIFOS |
US5850568A (en) * | 1995-12-22 | 1998-12-15 | Cypress Semiconductor Corporation | Circuit having plurality of carry/sum adders having read count, write count, and offset inputs to generate an output flag in response to FIFO fullness |
US5852748A (en) * | 1995-12-29 | 1998-12-22 | Cypress Semiconductor Corp. | Programmable read-write word line equality signal generation for FIFOs |
US5682356A (en) * | 1996-01-11 | 1997-10-28 | Cypress Semiconductor Corp. | Multiple word width memory array clocking scheme for reading words from a memory array |
US5764967A (en) * | 1996-03-29 | 1998-06-09 | Cypress Semiconductor Corporation | Multiple frequency memory array clocking scheme for reading and writing multiple width digital words |
US5978868A (en) * | 1997-08-28 | 1999-11-02 | Cypress Semiconductor Corp. | System for generating buffer status flags by comparing read and write pointers and determining direction of progression of read pointer with respect to write pointer |
US5963499A (en) * | 1998-02-05 | 1999-10-05 | Cypress Semiconductor Corp. | Cascadable multi-channel network memory with dynamic allocation |
JP2000149436A (en) * | 1998-11-02 | 2000-05-30 | Sony Corp | Digital information reproducing device and reproducing method |
JP2001195877A (en) * | 2000-01-11 | 2001-07-19 | Seiko Epson Corp | Semiconductor integrated device |
-
2004
- 2004-06-30 DE DE602004013977T patent/DE602004013977D1/en active Active
- 2004-06-30 JP JP2006518442A patent/JP4900800B2/en not_active Expired - Fee Related
- 2004-06-30 KR KR1020057025390A patent/KR20060028706A/en not_active Application Discontinuation
- 2004-06-30 WO PCT/IB2004/051061 patent/WO2005003956A1/en active IP Right Grant
- 2004-06-30 CN CNB2004800186768A patent/CN100485601C/en not_active Expired - Fee Related
- 2004-06-30 EP EP04744431A patent/EP1644820B1/en not_active Not-in-force
- 2004-06-30 AT AT04744431T patent/ATE396447T1/en not_active IP Right Cessation
- 2004-06-30 US US10/562,887 patent/US7774573B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4750154A (en) * | 1984-07-10 | 1988-06-07 | Prime Computer, Inc. | Memory alignment system and method |
GB2214759A (en) * | 1988-01-18 | 1989-09-06 | Plessey Co Plc | High speed digital data link |
US4879720A (en) * | 1988-03-10 | 1989-11-07 | M/A-Com Government Systems, Inc. | Decoder ring system |
EP0498065A2 (en) * | 1991-02-04 | 1992-08-12 | International Business Machines Corporation | Variable data stripe system and method |
US6526495B1 (en) * | 2000-03-22 | 2003-02-25 | Cypress Semiconductor Corp. | Multiport FIFO with programmable width and depth |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100817204B1 (en) | 2006-12-22 | 2008-03-27 | 재단법인서울대학교산학협력재단 | Method and apparatus for mapping flash memory |
Also Published As
Publication number | Publication date |
---|---|
JP2007527079A (en) | 2007-09-20 |
CN100485601C (en) | 2009-05-06 |
US20060155927A1 (en) | 2006-07-13 |
EP1644820A1 (en) | 2006-04-12 |
JP4900800B2 (en) | 2012-03-21 |
EP1644820B1 (en) | 2008-05-21 |
DE602004013977D1 (en) | 2008-07-03 |
US7774573B2 (en) | 2010-08-10 |
ATE396447T1 (en) | 2008-06-15 |
CN1816796A (en) | 2006-08-09 |
KR20060028706A (en) | 2006-03-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100240372B1 (en) | Data code and decode apparatus and method | |
US6067267A (en) | Four-way interleaved FIFO architecture with look ahead conditional decoder for PCI applications | |
US20080244237A1 (en) | Compute unit with an internal bit FIFO circuit | |
US7589648B1 (en) | Data decompression | |
EP1644820B1 (en) | Single memory with multiple shift register functionality | |
US7461186B2 (en) | Data handover unit for transferring data between different clock domains by parallelly reading out data bits from a plurality of storage elements | |
Chang | A low-cost dual-mode deinterleaver design | |
JP3796250B2 (en) | Deinterleaving apparatus for digital communication system and deinterleaving method thereof | |
US6848042B1 (en) | Integrated circuit and method of outputting data from a FIFO | |
US7093084B1 (en) | Memory implementations of shift registers | |
CA2212099C (en) | Apparatus and method for removing error data decoding delay in a dtv | |
US20070208980A1 (en) | Method of transmitting data between different clock domains | |
US7610453B1 (en) | Reordering each array in a sequence of arrays | |
US6442657B1 (en) | Flag generation scheme for FIFOs | |
JP2001332980A (en) | Device and method for interleave | |
US7372755B2 (en) | On-chip storage memory for storing variable data bits | |
KR100248395B1 (en) | Design method of channel encoder in digital communication | |
US8006066B2 (en) | Method and circuit configuration for transmitting data between a processor and a hardware arithmetic-logic unit | |
JPH10112735A (en) | Mapping circuit for dqpsk modulation | |
KR100459114B1 (en) | Deinterleaver device and method of digital broadcasting | |
KR100233843B1 (en) | Image data saver | |
JP3634498B2 (en) | Image encoding device | |
KR100449033B1 (en) | the apparatus and the method for symmetrical data relay using inbuilted memory in PLD | |
KR20040010954A (en) | Transport Demultiplexor | |
JP2003258649A (en) | Decoder and decoding method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2004744431 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2006518442 Country of ref document: JP |
|
ENP | Entry into the national phase |
Ref document number: 2006155927 Country of ref document: US Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10562887 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020057025390 Country of ref document: KR Ref document number: 20048186768 Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 1020057025390 Country of ref document: KR |
|
WWP | Wipo information: published in national office |
Ref document number: 2004744431 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 10562887 Country of ref document: US |
|
WWG | Wipo information: grant in national office |
Ref document number: 2004744431 Country of ref document: EP |