KR100449033B1 - the apparatus and the method for symmetrical data relay using inbuilted memory in PLD - Google Patents

Abstract

A symmetrical data relay device in a PLD using an internal memory according to the present invention uses a DPRAM embedded in a PLD, a read relay FIFO and a write relay FIFO connected to the DPRAM to relay external PLD function blocks and data. By enabling data read and write relay interface with specific function modules, data reliability from the device is not only guaranteed reliability and performance, but also unnecessary circuit elements compared to conventional data relaying through logic cells. It is effective to achieve PLD optimization design environment.

Description

The apparatus and the method for symmetrical data relay using inbuilt memory in PLD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a symmetrical data relay device in a programmable logc device (PLD) using a built-in memory and a relay method thereof. Specifically, data provided from a user is read from a user using a memory bank built in the PLD. And a symmetrical data relay device in a PLD using an internal memory for enabling a write relay interface and a relay method thereof.

With integrated circuit technology, chipsets in various fields have been systematically integrated and integrated, and the hardware structure in the unit has also been simplified. In addition, to reduce the unit cost, implement specific functions not commercialized, commercial PLDs are frequently used to implement general functions such as the CPU bus interface.

In general, the PLD includes memory and interface elements for inputting and outputting data from a user or connected to a specific function module of the PLD according to a user control signal transmitted from an external MCU unit.

1 is a block diagram of a conventional device for performing data relay in a PLD. Referring to FIG. 1, a conventional apparatus for performing data relay in a PLD includes a logic memory 1 for largely forming memory cells and storing data, and data stored in the logic memory 1. The decoder / MUX (2) for addressing to transfer the data to a specific address area, and the data stored in the logic memory 1 by the decoder / MUX (2) by latching the data to a specific function module outside the PLD. And an external data latch and insertion section 3 for extracting data from a specific function module external to the PLD and writing it to the logic memory 1.

The logic memory 1 is connected to an external user interface bus on one side and receives a user control signal transmitted from the outside, and reads data from a specific area and transmits the data to an external user side according to the control signal, or the user side. It serves to receive data from. On the other hand, the inside of the PLD performs a function of storing data of a specific region or transferring stored data to a specific region according to a user control signal transmitted from the outside.

Therefore, when the memory area of the logic memory 1 is based on the inside of the PLD, the memory area of the logic memory 1 is written through the external data latch and extractor 4 and the write area and the external data latch and inserter 3. In order to transfer data to the outside, it may be configured as a lead region to which data is read.

The decoder / MUX 2 is a decoder and a MUX for decoding respective addresses to be stored when storing the data stored in the logic memory 1 to the external data latch and inserting section 3. The decoder and the MUX are required corresponding to the number of memory cells included in each logic memory 1.

The external data latch and inserter 3 receives the data stored in the logic memory through the decoder / MUX 2 and delivers the data to the functional block of the PLD that needs the data.

The external data latch and extractor 4 is used for latching and extracting data transmitted to the user interface bus through the logic memory 1 or data to be stored in the logic memory 1 from the outside for performing the function of the PLD. Perform the interface function.

As such, in the related art, memory cells are formed using limited logic cells and gates in a PLD, and address decoding is required to designate each cell position thereof. Thus, when a large data relay function is required, a large MUX is required. And a large amount of flip-flop (FF) is bound to be covered.

Therefore, if a memory cell is configured through logic without using a memory block embedded in the PLD to implement a large-scale data relay function, huge muxes are required as well as a waste of logic elements allowed in the PLD. There is a problem in that a waste of gates and excessive routing are accompanied by a vicious cycle in which performance is degraded.

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and uses a built-in memory bank to enable data read from a user to read data and a write relay interface with a specific function module. It is an object of the present invention to provide a symmetric data relay device and a method thereof.

1 is a configuration block diagram of a data relay device conventionally implemented in a PLD.

2 is a block diagram of a symmetrical data relay device in a PLD using an internal memory according to the present invention;

3 is a conceptual diagram illustrating a data storage form between a DPRAM and a relay FIFO shown in FIG. 2.

4 is a block diagram illustrating a configuration of a write relay FIFO and a latch unit shown in FIG. 2.

5 is a detailed block diagram of the write relay FIFO and latch unit shown in FIG. 4;

FIG. 6 is a detailed block diagram of the address generation and control unit shown in FIG. 2; FIG.

7 is a conceptual diagram illustrating the operation of a symmetrical data relay device in a PLD according to the present invention.

8 is a timing diagram for explaining an operation during a read relay cycle during operation of a data relay device using an internal memory according to the present invention;

9 is a timing diagram for explaining an operation during a write relay cycle during operation of a data relay device using an internal memory according to the present invention;

* Description of the symbols for the main parts of the drawings *

10: DPRAM 11: lead area

12: write area 20: address generation and memory control unit

30: reed relay FIFO 40: light relay FIFO

50: data selection section 60: external data latch and insertion section

70: external data latch and extract section

According to one aspect of the symmetrical data relay device in the PLD using the built-in memory according to the present invention for achieving this object, in the data relay device in the PLD, an internal memory embedded in the PLD by allocating a lead area and a write area, A first storage unit having the same memory size as the write area, latching and storing data from the outside, and sequentially shifting the stored data, and having the same memory size as the read area, and data input from the lead area of the internal memory. Selects a second storage unit for shifting and storing the data, latching the stored data, and data input to the first storage unit to latch external data to the first storage unit or to shift the latched data. A data selection section for reproducing the internal memory during a read relay cycle. Reads the data stored in the area, generates an address for storing in the second storage, generates a control signal for latching external data in the first storage, and b) stores in the first storage during the write relay cycle. And an address generation and a memory controller for generating an address for sequentially writing and storing data in the write area of the internal memory and generating a control signal for latching data stored in the second storage to the outside. .

On the other hand, according to one aspect of the symmetrical data relay method in the PLD using the built-in memory according to the present invention, in the data relay method in the PLD, the read cycle operation using the read area and the write area allocated to the built-in memory built in the PLD In the read cycle operation mode, the external data is latched and stored in a first storage unit having a memory having the same size as that of the write area, and in the read area of the internal memory. Reading stored data and storing the shifted data in a second storage unit having a memory size identical to that of the read area through a shift operation; in a write cycle operation mode, latching data stored in the second storage unit to the outside; Write data by shifting the data stored in the storage to the light area of the internal memory Performs steps.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

To make the description of the present invention more clear, the following several items will be defined.

First of all, inserting user data of main memory into a specific timeslot position on an ATM cell or SDH frame is referred to as reading data, and supplying data to main memory to supply data extracted from a frame to a user or main memory. Let's say it's a light.

In addition, the direction in which the user data is supplied to or from the data relay on the basis of the main memory is referred to as the read direction and the write direction, respectively, and the buffer capacity in the two directions is the same, and the generated address and the speed are the same. Let's define the structure that is called symmetrical.

In addition, in the user interface of the DPRAM, data generated from an external data extractor or data for supply to the inserter must exist in respective regions of the DPRAM, and input / output of such data is provided through a user side port of the DPRAM. Since the functions and methods for this are general memory interfaces, they will be omitted.

With this definition, let's look at a symmetric data relay device in a PLD using an internal memory according to the present invention.

2 is a block diagram illustrating a configuration of a symmetrical data relay device in a PLD using an internal memory according to the present invention. 2, a DPRAM 10, an address generation and memory control unit 20, a read relay FIFO 30, a write relay FIFO 40, a data selector 50, an external data latch, And an extracting unit 60 and an external data latch and inserting unit 70.

The DPRAM 10 is a memory embedded in the PLD, and its size can be adjusted by a combination of configured memory banks. In addition, in the use area division of the DPRAM 10, the lead area and the write area may be divided for convenience of reference on the user interface side. If the address generation rule on the data relay side is different, the memory area may be configured in various forms desired by the designer.

The address generation and memory control unit 20 controls the read relay FIFO 30, the write relay FIFO 40 and the MUX 50, as well as the data read from the DPRAM 10 to the outside or the DPRAM 10 from the outside. A memory control function is performed by generating various control signals and addresses so that data can be written.

For this purpose, the address, chip select, read / write, data enable, drive clock, unit bus cycle, and cycle progress are required to automatically perform data read and write operations with the memory. Generate control signals such as signals.

The read relay FIFO 30 reads data in the read area 11 of the DPRAM 10 to interface with the external data latch and insertion unit 70. That is, data is read from the read area 11 of the DPRAM 10 by the address generation and the control signal of the memory control unit 20, and shifts by a serial shift during a read cycle. 10, when the lead region 11 is filled with the same size, the data is supplied to the corresponding latch of the data latch and the inserting portion 70 by the drive clock during the write cycle.

The write relay FIFO 40 performs a function of interfacing to write data stored in the external data latch and extracting unit 60 in the write area 12 of the DPRAM 10.

The data selector 50 is composed of a 2: 1 mux, and includes a shift output of the light relay FIFO 40 and data extracted from the outside through the external data latch and extractor 60 to the light direction interface side of the data relay. Select latch output.

The external data latch and extractor 60 must satisfy the condition that the number of latches constituting the internal data is the same as the number of basic cells of the write relay FIFO 40. This is because the base cells of each FIFO in the data progress direction must correspond to the base cells of the write relay FIFO 40 in order to transfer data to the write relay FIFO 40 having the corresponding address in the memory.

The external data latch and insertion unit 70 must satisfy the condition that the latches provided therein are identical to the size of the read relay FIFO 30. The reason is that in order to receive the data filled in the read relay FIFO 30 in the data progress direction, the base cells of the read relay FIFO 30 must correspond to each other.

Referring to the data relay operation performed in the symmetrical data relay device in the PLD using the built-in memory according to the present invention configured as described above, when the read cycle starts, the data read operation according to the shift operation of the read relay FIFO 30, and write The external data load operation of the relay FIFO 40 is performed. When all data of the read area in the memory is read into the read relay FIFO 30, the read relay cycle ends, and at this time, the shift operation of the read relay FIFO 30 and the external data load operation of the write relay FIFO 40 are also terminated. Subsequently, when the write relay cycle starts with the address increase, the write relay FIFO 40 starts to write data to the write area 12 of the DRAM 10 while shifting its data in units of bus cycles, and at the same time, the read relay FIFO Data in 11 begins to be transferred to the outside through an external data latch and insert 70.

3 is a conceptual diagram illustrating a data storage type between a DPRAM and a relay FIFO shown in FIG. 2. The configuration of the DPRAM 10 will be described in more detail with reference to FIG. 3.

The DPRAM 10 must satisfy the condition that the memory sizes of the read and write regions 11 and 12 are the same as the sizes of the corresponding read relay FIFO 30 and the write relay FIFO 40, respectively. The reason is that when the data is filled in its own FIFO, the read relay and the write relay, which are opposite to each other in the data progress direction, are stored in a certain position in the memory or vice versa. This is because the base cells of each FIFO must correspond to the base cells having the corresponding address in memory or the latches in the external data insert to be delivered.

Therefore, all items such as the data, the size of the memory area, the generated address signal and all cycle signals, the size of each FIFO, etc. should be considered at the same time when designing symmetrically so that the data can be delivered to a predetermined position. .

FIG. 4 is a block diagram illustrating a write relay FIFO and a latch unit illustrated in FIG. 2. Referring to FIG. 4, the write relay FIFO 40 receives data generated by the external data latch and extractor 60 from the latch during the read cycle and stores the data in the standby state. Then, once the write cycle proceeds, the mode is switched to the serial shift mode, and data is written to the write area 12 in the DPRAM 10 by the write cycle signal.

FIG. 5 is a detailed block diagram illustrating the write relay FIFO and the latch unit illustrated in FIG. 4. Referring to FIG. 5, the D-flop flops arranged in series and connected in series, the Q output of the front-side flip-flop as one input, and the outputs of the external data latch and extraction unit 60 as one input, It consists of a 2: 1 mux connected to select one input and output it to the D input of the next D flip-flop.

FIG. 6 is a detailed block diagram of an embodiment of the address generation and control unit illustrated in FIG. 2. A configuration of an address generation and a controller will be described with reference to FIG. 6. In the embodiment, a case of implementing a data relay having an area of 0xFF (256 bytes) will be described.

As shown, the address generation and control unit 20 receives a 3-bit output consisting of an 11-bit binary counter 21 and outputs of the 0-2 ports of the 11-bit binary counter 21 and performs a NAND operation to perform tc8. A 7-bit output consisting of a NAND operator 22 for outputting the output, an inverting operator 23 for inverting the tc8 output, and an output of the third to tenth ports of the counter 21 and being output as a tc4 control signal. A logical product operator 24 and a 2: 1 mux 25 using the tc4 signal as a control signal, the tc8 signal as one input, and the output as a wrb control signal.

The tc4 signal is used as an R / W relay cycle signal. That is, the data transfer between the respective latches present in the external data latch and insertion unit 70 and the external data latch and extraction unit 60, and the corresponding read relay FIFO 30 and the write relay FIFO 40 corresponding thereto is performed. It is necessary to wait until the data area is filled with the same number of data in the same FIFO, so a control signal is required.

This signal is shown as an R / W cycle end signal in FIG. This controls the point of data transfer from the read relay FIFO to the external latch or from the external latch to the write relay FIFO. In particular, it controls the external latch selection mode of the write relay FIFO 40 via 2: 1 MUX.

The data transfer clock with the external data latch and insertion unit 70 uses a system clock that is a reference clock for read data relay and a bus cycle signal for write data relay.

The 3-bit output, which consists of the outputs of the 0-2 ports of the 11-bit binary counter 21, is used as a 3-bit counter. For the unit bus cycle, use the inverted value of tc8. An eight-bit output consisting of the outputs of the fourth through 11th ports of the counter is used to count the addresses. The output signal bit of the second port is used as the shift clock rdck of the read relay FIFO 30. The wrb control signal is used as the R / W STROBE signal.

The address is incremented in bus cycles from the start to the end of the specified area, and other signals are repeated in a regular and synchronized state.

7 is a conceptual diagram illustrating an operation of a symmetrical data relay device in a PLD according to the present invention. Here, since n = m (n and m are the number of bytes of the read and write regions, respectively), t _{m = 2tn} . Referring to FIG. 7, a brief description will be given of a relay operation of data in a read relay cycle and a write relay cycle.

First, when operating in a read relay cycle (a), the read relay FIFO 30 performs a shift operation to read the corresponding data from the lead region 11 of the DRAM 10 (b). In addition, the write relay FIFO 40 operates in the external latch mode (c), and transmits data from the external data latch and extractor 60 to the write relay FIFO 40 (d). That is, when the read relay cycle starts, the data read according to the shift operation of the read relay FIFO 30 and the external data load operation of the write relay FIFO 40 are performed. When all data of the read area 11 of the DRAM 10 is read into the read relay FIFO 30, the read relay cycle ends, and at this time, a shift operation of the read relay FIFO 30 and external data of the write relay FIFO 40 are performed. The load operation is also terminated.

On the other hand, when operating in the write relay cycle (e) The write relay FIFO 40 writes the corresponding data in the write area 12 of the DRAM 10 (f). At this time, the write relay FIFO 40 operates in the shift mode (g), and transfers data from the read relay FIFO 30 to the external data latch and insertion unit 60 (h). That is, when the write relay cycle starts with the address increase, the write relay FIFO 40 starts to write data to the write area 12 of the DRAM 10 while shifting its data in units of bus cycles, and at the same time, the read relay Data in the FIFO 11 begins to be transferred to the outside through an external data latch and insert 70.

8 is a timing diagram illustrating an operation during a read relay cycle during operation of a data relay device using an internal memory according to the present invention. A read relay cycle operation of a data relay device using an internal memory according to the present invention will be described with reference to FIG. 8.

When the system clock (ck20) 110 is provided, the 11-bit binary counter 21 is operated, and R / W as a result of the logical product operation of the input from the fourth port to the eleventh port of the 11-bit binary counter 21. The relay cycle signal tc4 is output. When the tc4 signal is in a high state, it operates in a read relay cycle, and when the tc4 signal is in a low state, it operates in a write relay cycle. In the drawing, the operation is performed in a reed relay cycle starting from the time 121 rising from the low state to the high state to the time 122 falling from the high state to the low state.

The 3-bit output, which is the output from the first port to the third port of the 11-bit binary counter 21, acts as the 3-bit counter 130 to count the time of occurrence of the unit bus cycle 140 required to change the address. That is, the bit value of the 3-bit counter is generated in the unit bus cycle 140 each time one cycle is completed. The clock for changing the address is used not tc8 signal. Therefore, in the drawing, the low state is maintained at the time when the 3-bit counter counts 0, the cycle is completed, the high state is raised to the high state at the 7-bit time, and then low. The address counter 150 counts an address by changing an address value at a time when a unit bus cycle is clocked from the fourth port of the 11-bit binary counter 21 to the output bit value of the eleventh port. That is, the address address of 0x00 is counted at the first time point 141 of the unit bus cycle, the address address of 0x01 is counted at the second time point 142, and the address address of 0x80 is counted at the third time point 143. do. The address count at this time counts the address of the read relay FIFO. On the other hand, the R / W STROBE signal outputs a low state value when the tc4 signal is high and outputs a tc8 signal when the tc4 signal is low. Thus, the figure shows a low state.

On the other hand, the rdck signal, which is a read relay FIFO shift clock, is a third port output value of the 11-bit counter 21 and generates a clock with a period of 8 bits. At this point, when the rd_ck clock rises, the data stored in the read area 11 of the DPRAM 10 is sequentially shifted to the read relay FIFO 30.

On the other hand, since tc8 is used as the write relay FIFO latch clock 190, data is latched from the external data latch and extractor 70 to the write relay FIFO 40 at each of the rising points 191 and 192 of the write relay FIFO latch clock. Accordingly, the data upgrade of the write FIFO 40 is performed from the external data latch and extractor 70.

9 is a timing diagram illustrating an operation during a write relay cycle during operation of a data relay device using an internal memory according to the present invention. 9, a write relay cycle operation of a data relay device using an internal memory according to the present invention will be described.

When the system clock (ck20) 110 is provided, the 11-bit binary counter 21 is operated, and R / W as a result of the logical product operation of the input from the fourth port to the eleventh port of the 11-bit binary counter 21. The relay cycle signal tc4 is output. As the tc4 signal is low, it operates in a write relay cycle. In the drawing, the light relay cycle is operated from the time point 122 when the high state falls to the low state until the time point when the state rises from the low state to the high state.

The address counter clock 150 counts the address by changing the address value at the time when the clock of the unit bus cycle is generated from the fourth port to the eleventh port of the 11-bit binary counter 21. That is, the address address of 0x80 is counted at the first time point 144 of the unit bus cycle, the address address of 0x81 is counted at the second time point 145, and the address address of 0x00 is counted at the third time point 146. do. The address count at this time counts the addresses of the write relay FIFOs 40. Meanwhile, the R / W STROBE signal outputs the tc8 signal when the tc4 signal is in a low state, and thus the clock of the tc4 signal is shown in the drawing.

On the other hand, since the tc8 signal is used for the write relay FIFO shift clock 200, the data stored in the write relay FIFO 30 at the time of the rise of the tc8 201 and 202 are sequentially read out of the read area 11 of the DPRAM 10. Shifts to).

Meanwhile, as the system clock ck20 is used as the read relay FIFO latch clock 220, data stored at the corresponding address of the read relay FIFO 30 for each of the clocks 221 and 222 is external data latch and insertion unit 60. Is latched to supply the read relay FIFO data to the external data latch and the inserter 60 and the extractor 70.

As described above, the data relay operation between the internal memory and any other function module using the PLD has been described. The system clock used in the present invention is an important factor for measuring performance, but may be limited depending on the processing speed of the memory or the performance of the PLD. In this test, a clock of 20MHz is used, so assuming unit bus cycle of 200ns, it takes about 50ms to process 256 bytes of data.

If a memory cell is configured through logic without using the built-in memory block to implement a large data relay function, huge MUXs are required as well as a waste of logic elements allowed in the PLD. This can be accompanied by waste and excessive routing, resulting in a vicious cycle of performance degradation.

In the present invention, all data input and output to and from the internal memory, various FIFOs, and external data insertion and extraction units are performed through flip-flops in order to exclude such elements, thereby enabling synchronized operation and having great reliability.

This method uses built-in RAM, which not only guarantees the reliability and performance of the device but also saves unnecessary circuit elements, compared with logic cells, and is effective in achieving PLD-optimized design environment.

Claims (8)

In the data relay device in the PLD, Internal memory built into the PLD by allocating lead and write areas; A first storage unit having the same memory size as the write area, receiving and storing data from an external source, and sequentially shifting the stored data; A second storage unit having the same memory size as the lead region, shifting and storing data input from the lead region of the internal memory, and latching the stored data; A data selector for selecting data input to the first storage to cause the first storage to latch external data or to shift the latched data; a) generates an address for reading data stored in a read area of the internal memory during the read relay cycle and storing the data in the second storage unit; and generating a control signal for latching external data in the first storage unit; , b) generating an address for sequentially writing and storing data stored in the first storage unit in the write area of the internal memory during a write relay cycle, and externally latching data stored in the second storage unit. A symmetrical data relay device in a PLD using an internal memory including an address generator for generating a control signal and a memory controller. The symmetrical data relay device according to claim 1, wherein said internal memory is a dual port memory. delete The memory of claim 1, wherein the first storage unit and the second storage unit are first-in first-out output memory. Symmetrical data relay device in PLD using built-in memory. The symmetric data relay device of claim 1, wherein the data selector comprises a 2: 1 mux arranged in multiple stages. In the data relay method in the PLD, Relay the data by performing the read cycle operation mode and the write operation mode by using the read area and the write area allocated to the internal memory embedded in the PLD, In the read cycle operation mode, Latching and storing external data in a first storage unit having a memory having the same size as that of the write area; Reading data stored in a read area of the internal memory and storing the data in a second storage part having a same memory size as the read area by a shift operation; In the light cycle operation mode, Latching data stored in the second storage unit to the outside; And shifting the data stored in the first storage into the write area of the internal memory to write the data to the write area of the internal memory. The symmetric data relay method according to claim 6, wherein the internal memory is a dual port memory. 7. The first and second storage units of claim 6, wherein the first storage unit and the second storage unit are first-in first-out output memory. Symmetrical data relay method in PLD using internal memory.