WO2004105220A2 - Systeme de module de puissance - Google Patents

Systeme de module de puissance Download PDF

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Publication number
WO2004105220A2
WO2004105220A2 PCT/US2004/015259 US2004015259W WO2004105220A2 WO 2004105220 A2 WO2004105220 A2 WO 2004105220A2 US 2004015259 W US2004015259 W US 2004015259W WO 2004105220 A2 WO2004105220 A2 WO 2004105220A2
Authority
WO
WIPO (PCT)
Prior art keywords
power module
bus
power
housing
electrically coupled
Prior art date
Application number
PCT/US2004/015259
Other languages
English (en)
Other versions
WO2004105220A3 (fr
Inventor
Sayeed Ahmed
Fred Flett
Douglas K. Maly
Ajay V. Patwardhan
Original Assignee
Ballard Power Systems Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/642,424 external-priority patent/US6987670B2/en
Priority claimed from US10/642,391 external-priority patent/US6906404B2/en
Priority claimed from US10/658,804 external-priority patent/US7505294B2/en
Priority claimed from US10/664,808 external-priority patent/US7443692B2/en
Application filed by Ballard Power Systems Corporation filed Critical Ballard Power Systems Corporation
Publication of WO2004105220A2 publication Critical patent/WO2004105220A2/fr
Publication of WO2004105220A3 publication Critical patent/WO2004105220A3/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • This disclosure is generally related to electrical power systems, and more particularly to power module architectures suitable for rectifying, inverting and/or converting electrical power between power sources and loads.
  • Power modules are typically self-contained units that transform and/or condition power from one or more power sources for supplying power to one or more loads.
  • a power module commonly referred to as an inverter, transforms direct current (DC) to alternating current (AC), for use in supplying power to an AC load.
  • a power module commonly referred to as a rectifier, transforms AC to DC.
  • power modules commonly referred to as a DC/DC converter step up or step down a DC voltage.
  • An appropriately configured and operated power module may perform any one or more of these functions.
  • the term "converter” is commonly applied generically to all power modules whether inverters, rectifiers and/or DC/DC converters.
  • a DC power source such as a fuel cell system, battery and/or ultracapacitor may produce DC power, which must be inverted to supply power to an AC load such as a three-phase AC motor in an electric or hybrid vehicle.
  • a photo-voltaic array may produce DC power which must be inverted to supply or export AC power to a power grid of a utility.
  • An AC power source such as a power grid or micro-turbine may need to be rectified to supply power to a DC load such as a tool, machine or appliance.
  • a high voltage DC source may need to be stepped down to supply a low voltage load, or a low voltage DC source may need to be stepped up to supply a high voltage load.
  • Custom designing of power modules results in excessive costs related to the design process, as well as, duplicative costs related to the creation of custom tooling, the manufacture of custom parts, and maintenance of separate inventories. Custom designing also reduces time to market. It would be desirable to have a power module that allows the investment in design, tooling, manufacturing and inventorying to be shared across many application specific products, and may shorten time to market.
  • the disclosure is directed to an architecture for a power module, employing a high degree of modularity, that allows a base power module to be quickly, easily, and cost effectively configured to address a large variety of applications by simply interchanging components, electrical connections, and/or software.
  • Figure 1 is an isometric view of a power module comprising a housing, integrated cold plate, DC bus terminals, AC phase terminals, circuitry and a gate drive board.
  • Figure 2A is an isometric view of the power module of Figure 1 with a cover removed and some portions broken or remove to show the DC bus, the AC bus, and the circuitry carried by a number of tiles carried by a substrate.
  • Figure 2B is a top plan view of the power module of Figure 2A showing a representative sampling of wire bonds electrically connecting various circuit components, buses, and layers in the substrate as an inverter.
  • Figure 3 is a schematic cross sectional view of one embodiment of the DC bus comprising a pair of L-shaped DC bus bars spaced by an electrical insulation.
  • Figure 4 is a schematic cross sectional view of one embodiment of the DC bus comprising a pair of generally planar DC bus bars spaced by an electrical insulation.
  • Figure 5 is a schematic view of a single power module configured as a power inverter between a power source and a load, illustrating some aspects of the architecture of the power module and the topology of the substrate.
  • Figure 6 is a schematic view of a single power module configured as an AC/AC power converter between a power source and a load, illustrating some aspects of the architecture of the power module and the topology of the substrate.
  • Figure 7 is a schematic view of a single power module configured as a half bridge rectifier between a power source and a load, illustrating some aspects of the architecture of the power module and the topology of the substrate.
  • Figure 8 is a schematic view of a single power module configured as an H bridge rectifier between a power source and a load, illustrating some aspects of the architecture of the power module and the topology of the substrate.
  • Figure 9 is an isometric view of a pair of power modules in back- to-back configuration and an external connector electrically coupling the DC buses of the power modules.
  • Figure 10 is a schematic view of the pair of power modules in back-to-back configuration of Figure 9 configured as a high power inverter between a power source and a load, illustrating some aspects of the architecture of the power module and the topology of the substrate.
  • Figure 11 is a schematic view of pair of power modules in back-to- back configuration of Figure 9 configured as two three phase inverters between a power source and a pair of loads, illustrating some aspects of the architecture of the power module and the topology of the substrate.
  • Figure 12 is a schematic view of the pair of power modules in back-to-back configuration of Figure 9 configured as a single three phase power inverter between a power source and a load, illustrating some aspects of the architecture of the power module and the topology of the substrate.
  • Figure 13 is a schematic view of the pair of power modules in back-to-back configuration of Figure 9 configured as a half bridge rectifier between a power source and a load, illustrating some aspects of the architecture of the power module and the topology of the substrate.
  • Figure 14 is a schematic view of the pair of power modules in back-to-back configuration of Figure 9 configured as an H bridge rectifier between a power source and a load, illustrating some aspects of the architecture of the power module and the topology of the substrate.
  • Figure 15 is a topological view of a single power module configured as a tri-level inverter between a power source and a three-phase load, illustrating some aspects of the architecture of the power module and the topology of the substrate.
  • Figure 16 is an electrical schematic view of a single-phase tri-level inverter (or one phase of a three-phase tri-level inverter).
  • Figure 17 is a timing diagram illustrating example outputs produced by the tri-level inverter of Figure 16 in response to a particular series of control signals.
  • Figure 18 is a top view of a tri-level inverter implemented in the power module of Figure 1.
  • Figure 19 is an electrical schematic view of a three-phase tri-level inverter.
  • Figure 20 shows an isometric view of a power converter according to one embodiment, comprising a high frequency capacitor and bulk capacitor coupled across the DC bus of the base power converter, a second housing to receive the capacitors and first housing, and a gate driver.
  • Figure 21 is an exploded isometric view of the power converter of Figure 20.
  • Figure 22A is a partial isometric view of a portion of a low side of the power converter illustrating the surface mounting of snubber capacitors to a low side emitter area of the substrate.
  • Figure 22B is an isometric view of a portion of a high side of the substrate illustrating the surface mounting of the snubber capacitors to a high side collector area of the substrate.
  • Figure 23 is an electrical schematic of the switches, freewheeling diodes, and snubber capacitors according to an illustrated embodiment.
  • FIGS 1 , 2A, and 2B show a base power module 10, generally comprising: a lead frame or housing 12, an integrated cold plate 14 attached to the housing 12 via bushings 15, a DC bus 16, an AC bus 18; power semiconductor devices electrically coupled between the DC bus 16 and AC bus 18, forming a low side 20a and a high side 20b of the power module 10.
  • the base power module 10 may further include one or more gate driver boards 22 for driving some of the power semiconductors 20 (see, Figures 20 and 21).
  • the DC bus 16 includes two sets of DC bus terminals 24, 26 extend out of the housing 12.
  • one set of DC bus terminals 26 is electrically coupled to a positive voltage or high side 20b of a power source or load and the other set of DC bus terminals is 24 is electrically coupled to a negative voltage or low side 20a of the power source or load.
  • the DC bus terminals 24, 26 are electrically coupled to respective DC bus terminals 24, 26 on another power module.
  • a set of AC phase terminals comprises three pairs of AC bus phase terminals 28a, 28b, 30a, 30b, 32a, 32b, extending out of the housing 12.
  • one pair of AC phase terminals is coupled to a respective phase (A, B, C) of a three phase power source or load.
  • some of the AC phase terminals are interconnected across or between the pairs, and coupled to power sources or loads.
  • Figure 3 shows a schematic cross-sectional view of the power module 10 taken along section line 3-3 of Figure 2A.
  • Figure 3 is not an exact cross-sectional view, but has been modified to more accurately represent the electrical connections which would otherwise not be clearly represented in the Figure 3.
  • the integrated cold plate 14 comprises a metal base plate 39, a direct copper bonded (DCB) substrate 40 which attached to the metal base plate by a solder layer 41.
  • a cooling header 42 including a number of cooling structures such as fins 42a, one or more fluid channels 42b, a fluid inlet 42c and a fluid outlet 42d for providing fluid connection flow to and from the fluid channels 42b, respectively.
  • the DCB substrate 40 typically comprises a first copper layer 40a, a ceramic layer 40b and a second copper layer 40c which are fused together.
  • the second copper layer 40c may be etched or otherwise processed to form electrically isolated patterns or structures, as is commonly known in the art.
  • the second copper layer 40c may be etched to form regions of emitter plating 43a and collector plating 44a on a low side 20a of the power module 10 (i.e., side connected to DC bus bar 34).
  • the second copper layer 40c may be etched to form regions of emitter plating 43b and collector plating 44b on the high side 20b of the power module 10 (i.e., side connected to DC bus bar 36.
  • a conductive strip 45 or wire bonds may extend between the collector plating 44a of the low side 20a and the emitter plating 43b of the high side 20b, passing through respective passages 46 formed under the DC bus bars 34, 36. As illustrated, the conductive strip 45 has be exaggerated in length on the low side 20a of the power module 10 to better illustrate the electrical connection with the collector plating 44a.
  • Power semiconductor devices 20 are attached to the various structures formed in the second copper layer 40c via a solder 47.
  • the power semiconductor devices may include one or more switches for example, transistors 48 such as integrated bipolar gate transistors (IGBTs) or metal oxide semiconductor field effect transistors (MOSFETS) 48.
  • the power semiconductor devices may also include one or more diodes 50.
  • the power semiconductor devices may have one or more terminals directly electrically coupled by the solder 47 to the structure on which the specific circuit element is attached.
  • the collectors of IGBTs 48 may be electrically coupled directly to the collector plating 44a, 44b by solder 47.
  • the cathodes of diodes 50 may be electrically coupled directly to the collector plating 44a, 44b by solder 47.
  • the DC bus 16 comprises a pair of L-shaped DC bus bars 34a, 36a.
  • the upper legs of the L-shaped DC bus bars 34a, 36a are parallel and spaced from one another by the bus bar insulation 38.
  • the lower legs of the L- shaped DC bus bars 34, 36 are parallel with respect to the substrate 40 to permit wire bonding to appropriate portions of the substrate.
  • the negative DC bus bar 34a may be wire bonded to the emitter plating 43a of the low side 20a
  • the positive DC bus bar 36a by be wire bonded to the collector plating 44b of the high side 20b.
  • the emitters of the IGBTs 48 and anodes of the diodes 50 may be wire bonded to the respective emitter plating 43a, 43b.
  • FIG. 4 shows another embodiment of the DC bus 16 for use in the power module 10, the DC bus 16 comprising a pair of generally planar DC bus bars 34b, 36b parallel and spaced from one another by a bus bar insulation 38.
  • the DC bus bars 34b, 36b are horizontal with respect to a substrate 40 ( Figures 2A and 2B), with exposed portions to permit wire bonding to the various portions of the substrate 40.
  • the DC bus bars 34, 36 are parallel, counter flow of current is permitted, thereby canceling the magnetic fields and their associated inductances.
  • the parallel DC bus bars 34, 36 and bus bar insulation 38 construct a distributed capacitance.
  • capacitance dampens voltage overshoots that are caused by the switching process.
  • the DC bus bars 34, 36 of the embodiments of Figures 3 and 4 create a magnetic field cancellation as a result of the counter flow of current, and capacitance dampening as a result of also establishing a functional capacitance between them and the bus bar insulation 38.
  • the power semiconductor devices include a number of decoupling capacitors 55 electrically coupled between the DC bus bars 34, 36 and ground to reduce EMI.
  • the decoupling capacitors 55 are located on the substrate 40 inside the housing 12. For example, some of the decoupling capacitors 55 are electrically coupled directly to the emitter plating 43a on the low side 20a of the substrate 40 and some of the decoupling capacitors 55 are electrically coupled directly to the collector plating 44b on the high side 20b of the substrate 40.
  • the decoupling capacitors 55 can be soldered in the same operation as the soldering of the substrate 40 to the cold plate 14.
  • the DC bus bars 34, 36 each include three terminals 24, 26, spaced along the longitudinal axis, to make electrical connections, for example, to a DC power source. Without being restricted to theory, Applicants believe that the spacing of the terminals 24, 26 along the DC bus bars 34, 36 provides smoother current flow within the DC bus bars 34, 36 and lower inductance paths to the external DC voltage storage bank.
  • the DC bus bars 34, 36 are internal to the housing 12. This approach results in better utilization of the bus voltage, reducing inductance and consequently permitting higher bus voltages while maintaining the same margin between the bus voltage and the voltage rating of the various devices.
  • the lower inductance reduces voltage overshoot, and problems associated with voltage overshoot such as device reliability.
  • the increase in bus voltage permits lower currents, hence the use of less costly devices.
  • the bus bar insulation 38 between the DC bus bars 34, 36 may be integrally molded as part of the housing 12, to reduce cost and increase structural rigidity.
  • the DC bus bar 34, 36 may be integrally molded in the housing 12, or alternatively, the DC bus bar 34, 36 and bus bar insulation 38 may be integrally formed as a single unit and attached to the housing 12 after molding, for example, via post assembly.
  • the power semiconductor devices are directly mounted on the substrate 40 which is directly attached to the cold plate 14 via solder layer 41 , the resulting structure serving as a base plate.
  • the use of a large substrate 40 reduces or eliminates the need for jumpers, and consequently has the benefit of reducing inductance in the power module 10.
  • the use of a cold plate 14 as the base plate, and the direct mounting of the power semiconductor devices thereto, enhances the cooling for the power semiconductor devices over other designs, producing a number of benefits such as prolonging the life of capacitors 55.
  • the power semiconductor devices are operable to transform and/or condition electrical power.
  • the power semiconductor devices may include switches and/or diodes 50.
  • the power semiconductor devices may also include other electrical and electronic components, for example, capacitors 55 and inductors.
  • the power module 10 and power semiconductor devices may be configured and operated as an inverter (DC ⁇ 7 ⁇ C), rectifier (AC ⁇ DC), and/or converter (DC ⁇ DC; AC ⁇ AC).
  • the power module 10 and/or power semiconductor devices may be configured as full bridges, half bridges, and/or H-bridges, as suits the particular application.
  • FIG. 5 schematically illustrates the layout of the substrate 40, employing twelve distinct regions of collector plating 44a, 44b, denominated collectively below as tiles 44.
  • the tiles 44 are generally arranged in a low side 20a row of six areas of collector plating 44a and a high side 20b row of six areas of collector plating 44b.
  • Each tile 44 can carry a variety of switches such as IGBTs 48 and/or a variety of diodes 50.
  • the gate driver board(s) 22 ( Figure 1) are coupled to control the power semiconductor devices, particularly the switches 48, based on signals received from a controller 52 via a signal bus 54, which may also be integrated into the power module 10 or which may be provided separately therefrom.
  • a base or standard tile 44 typically carries two IGBTs 48 and four diodes 50.
  • the inclusion of specific component types (switches such as IGBTs 48 and/or diodes 50) and the number of each component on a tile 44 may depend on the specific application.
  • a tile 44 may carry up to four IGBTs 48, or alternatively, up to eight diodes 50.
  • a tile 44 may carry four diodes 50 and omit IGBTs 48, for example, where the power semiconductor devices on the tile 44 will act as a rectifier.
  • the ability to eliminate components where the specific application does not require these components provides significant cost savings. For example, eliminating IGBTs 48 can save many dollars per tile 44.
  • the power module 10 comprises three half bridges combined into a single three-phase switching module, or single half-bridge modules that may be linked together to form a three phase inverter.
  • the same DC to AC conversion may be accomplished using any number of half bridges, which correspond to a phase, and each switching pair may contain any number of switching devices.
  • many of the examples herein use a common three phase/three switching pair configuration, although this should not be considered limiting.
  • Current is then permitted to flow through one or more of the switching devices 48 and/or diodes 50 on the high side 20b to the emitter layer 43b.
  • the current passes the emitter layer 43a on the low side 20a via the conductive strip 45 passing under the DC bus bars 34, 36.
  • a phase terminal allows current to flow from the emitter layer 43a on the low side 20a to a load such as a three phase AC motor.
  • the negative DC bus bar 34 couples the load to the switching devices 48 and/or diodes 50 on the low side 20a via the emitter layer 43a.
  • the overall design of the standard power module 10, including the position and structure of the DC and AC buses 16, 18, topology of the substrate 40, modularity of the tiles 44, and the inclusion of six phase terminals 28a, 28b, 30a, 30b, 32a, 32b in the AC bus 16 provides great flexibility, allowing the standard power module 10 to be customized to a variety of applications with only minor changes and thus relatively small associated costs. A number of these applications are discussed below.
  • Figure 5 also shows the single power module 10 configured as a power inverter.
  • the power inverter may be suitable, for example, for providing 300A at 1200V.
  • a DC power supply 58 supplies power to the power module 10 via the terminals 24, 26 of the DC power bus 16.
  • the power module 10 supplies three phase AC power to a three phase AC load 60 via the AC power bus 18.
  • the phase terminals 28a, 28b, 30a, 30b, 32a, 32b are electrically coupled in pairs, each pair supplying a respective phase of the power.
  • Figure 6 shows a single power module 10 configured as an AC/AC power converter.
  • the power converter may be suitable, for example, for providing 300A at 1200V.
  • Three of the AC phase terminals 28a, 28b, 30a are electrically coupled to respective phases (A, B, C) of a three phase AC power source 58, while the other three AC phase terminals 30b, 32a, 32b are electrically coupled respective phases of a three phase AC load 60.
  • Single Power Module Half Bridge Rectifier Single Power Module Half Bridge Rectifier
  • Figure 7 shows a single power module 10 configured as a half bridge rectifier.
  • the half bridge rectifier may be suitable, for example, for providing 1800A at 1200V or 2400A at 600V.
  • a typically use would employ a dedicated half bridge for each phase of the power source.
  • All of the AC phase terminals 28a, 28b, 30a, 30b, 32a, 32b of the power module 10 are electrically coupled a phase (A, B, or C) of the three phase AC power source 62.
  • the DC terminals 24, 26 are electrically coupled respective poles of a DC load 64.
  • the power module 10 is configured with IGBTs 50 for activation rectification.
  • the power module 10 may employ passive rectification, omitting the IGBTs 48, and thereby reducing parts count and costs.
  • Figure 8 shows a single power module 10 configured as an H bridge rectifier.
  • the H bride rectifier may be suitable, for example, for providing 900A at 1200V, sufficient for home applications and furnaces such as induction heating.
  • Three of the AC phase terminals 28a, 28b, 30a are electrically coupled to one line of an AC power source 62, while the other AC phase terminals 30b, 32a, 32b are electrically coupled to the other line of the AC power source 62.
  • the DC terminals 24, 26 are electrically coupled to respective poles of a DC load 62.
  • the power module 10 is configured with IGBTs 50 for activation rectification.
  • the power module 10 may employ passive rectification, omitting the IGBTs 48, and thereby reducing parts count and costs.
  • Figure 9 shows a pair of power modules 10a, 10b physically coupled back-to-back with the cold plates 14 facing each other.
  • the power modules 10a, 10b may be physically coupled front-to-front, depending on orientation and specific topology.
  • a dielectric spacer 66 may positioned between the opposed faces (i.e., backs or fronts) of the first and second power modules 10a, 10b to form a capacitor 68. This takes advantage of the integrated cold plates 14 in the power modules 10a, 10b. Since the dielectric spacer 66 is adjacent the cold plates 14 cooling of the capacitor will be enhanced. Thus, the high power inverter may employ a smaller capacitor than would otherwise be necessary. This may allow the use of a film capacitor (i.e., one or more layers) rather than the typical electrolytic capacitor, further enhancing and contributing to the form function of the power module 10. Film capacitors are available commercially from a variety of sources, including EPCOS AG of Kunststoff, Germany.
  • An external connector 70 electrically couples the DC bus bars 34, 36 of the first power module 10a to respective ones of the of the DC bus bars 34, 36 of the second module 10b.
  • the external connector 70 may also function as a clamp, for biasing or holding the first and second power modules 10a, 10b together.
  • the external connector 70 may conform to the exterior of a portion of the power modules 10a, 10b, contributing to the small footprint of the device.
  • the external connector 70 may be approximately U-shaped, as illustrated, including a pair of arms that are sufficiently spaced apart to receive the power modules 10a, 10b therebetween.
  • the external connector 70 may be a laminate structure formed from at least two conductive layers and a number of insulating layers, at least one of the insulating layers spacing and electrically insulating the two conductive layers. Portions of the insulating layers are removed to expose portions of the conductive layers to allow the electrically connections to the respective DC bus bars 34, 36. Insulating layers may be formed from a variety of commercially available material, for example, NOMEX® available from E.I. du Pont de Nemours and Company, Advanced Fibers Systems, Richmond, Virginia. This modular approach takes advantage of the unique topology of the standard power module 10 to provide a simple, cost effective, form factor solution to meet a large variety of customer demands, as discussed in detail below.
  • Figure 10 shows a pair of power modules 10a, 10b physically coupled back-to-back similar to that of Figure 9, and electrically coupled to create a high power inverter (e.g., twice the power of an inverter based on a single power module).
  • the external connector 70 illustrated as separate DC+ and DC- connectors for clarity, electrically couples the DC bus bars 34, 36 of the first power module 10a to respective ones of the of the DC bus bars 34, 36 of the second module 10b.
  • the phase terminals of the first power module 10a are electrically coupled in pairs to respective phases of a three phase AC power source 62.
  • the phase terminals of the main inverter are electrically coupled in pairs to a three phase AC load 60.
  • the first power module 10a is operated as a starter inverter (i.e., rectifier) while a second power module 10b functions as a main inverter.
  • a starter inverter i.e., rectifier
  • a second power module 10b functions as a main inverter. Note that the IGBTs 48 have been removed from the tiles 44 of the first power module 10a, since the IGBTs are not necessary for the rectification, thus significantly reducing the cost of the inverter.
  • This modular approach takes advantage of the unique topology of the standard power module 10 to provide a simple, cost effective, form factor solution to customer demands for various levels of power.
  • Figure 11 shows a pair of power modules 10a, 10b physically coupled back-to-back similar to that of Figure 9, and electrically coupled as two three phase inverters.
  • the inverter may be suitable, for providing power to two three phase AC loads.
  • the inverter may be suitable, for example, for providing 1800A at 1200V or 2400A at 600V.
  • the external connector 70 (illustrated as separate DC+ and DC- connectors for clarity), electrically couples the DC bus bars 34, 36 of the first power module 10a to respective ones of the of the DC bus bars 34, 36 of the second module 10b.
  • the external connector 70 further couples the DC bus bars 34, 36 to a DC power source DC+, DC-.
  • Pairs of the AC phase terminals 28a, 28b, 30a, 30b, 32a, 32b of the first power module 10a are electrically coupled to provide respective phases (A, B, or C) to a first three phase AC power load 60. Pairs of the AC phase terminals 28a, 28b, 30a, 30b, 32a, 32b of the second power module 10b are electrically coupled to provide respective phases (A, B', or C) to a second three phase AC load 72.
  • Dual Power Module Single 3 Phase Inverter Figure 12 shows a pair of power modules 10a, 10b physically coupled back-to-back similar to that of Figure 9, and electrically coupled as a single three phase inverter.
  • the inverter may be suitable, for providing power to two three phase AC loads.
  • the inverter may be suitable, for example, for providing 1800A at 1200V or 2400A at 600V.
  • the external connector 70 (illustrated as separate DC+ and DC- connectors for clarity), electrically couples the DC bus bars 34, 36 of the first power module 10a to respective ones of the of the DC bus bars 34, 36 of the second module 10b.
  • the external connector 70 further couples the DC bus bars 34, 36 to a DC power source DC+, DC-.
  • a first pair of the AC phase terminals 28a, 28b of the first power module 10a are electrically coupled to a first pair 32a, 32b of the AC phase terminals of the second power module 10b, and to provide a first phase (A) to a three phase AC power load 60.
  • a second pair of the AC phase terminals 30a, 30b of the second power module 10b are electrically coupled to a second pair of AC phase terminals 30a, 30b of the second power module 10b and to provide a second phase (B) to the three phase AC load 60.
  • a third pair of the AC phase terminals 32a, 32b of the first power module 10a are electrically coupled to a third pair of the AC phase terminals 28a, 28b of the second power module 10b and to provide a third phase (C) to the three phase AC load 60.
  • Figure 13 shows a pair of power modules 10a, 10b physically coupled back-to-back similar to that of Figure 9, and electrically coupled as a half bridge.
  • the half bridge may be suitable, for example, for providing 1800A at 1200V, or 2400A at 600V. In typically use, a separate half bridge will be provided for each phase.
  • the external connector 70 (illustrated as separate DC+ and DC- connectors for clarity), electrically couples the DC bus bars 34, 36 of the first power module 10a to respective ones of the of the DC bus bars 34, 36 of the second module 10b.
  • the external connector 70 further couples the DC bus bars 34, 36 to a DC power source DC+, DC-.
  • All of the AC phase terminals 28a, 28b, 30a, 30b, 32a, 32b of the first power module 10a are electrically coupled to one line of an AC power source 62. All of the AC phase terminals 28a, 28b, 30a, 30b, 32a, 32b of the second power module 10b are electrically coupled to one line of an AC load 60 to provide one phase (A).
  • Figure 14 shows a pair of power modules 10a, 10b physically coupled back-to-back similar to that of Figure 9, and electrically coupled as an H bridge.
  • the H bride may be suitable, for example, for providing 900A at 1200V.
  • the external connector 70 (illustrated as separate DC+ and DC- connectors for clarity), electrically couples the DC bus bars 34, 36 of the first power module 10a to respective ones of the of the DC bus bars 34, 36 of the second module 10b.
  • the external connector 70 further couples the DC bus bars 34, 36 to a DC power source DC+, DC-.
  • Three of the AC phase terminals 28a, 28b, 30a of the first power module 10a are electrically coupled to one line of an AC power source 62, while the other three AC phase terminals 30b, 32a, 32b of the first power module 10a are electrically coupled to the other line of the AC power supply 62.
  • Three of the AC phase terminals 28a, 28b, 30a of the second power module 10b are electrically coupled to one line of an AC load 60, while the other AC phase terminals 30b, 32a, 32b of the second power module 10b are electrically coupled to the other line of the AC load 60.
  • FIGS 15-19 illustrate tri-level inverters that take advantage, inter alia, of the inclusion of two terminals per phase in the design of the base power module 10. This approach reduces the size and cost over prior tri-level inverters which employ two separate bi-level modules for each phase, requiring fairly complex external coupling schemes.
  • FIG. 15 shows an embodiment of a tri-level inverter 170 implemented with the base power module 10.
  • One phase terminal 28a, 30a, 32a in each pair of phase terminals is coupled to a neutral line in the housing 12 of the power module 10, to provide a reference to a respective phase 164a, 164b, 164c of a three-phase load 164, such as a motor.
  • the other terminal 28b, 30b, 32b of each pair of phase terminals is electrically coupled to provide the first, second, and third voltages V-i, V 2 , V 3 across the respective phase 164a, 164b, 164c of the three-phase load 164.
  • Figure 16 is an electrical schematic of a single-phase tri-level inverter 170, or one phase of a three-phase tri-level inverter.
  • the collector 172 of a first transistor Q1 is coupled to a positive DC supply line P.
  • the emitter 174 of the first transistor Q1 is connected to a first node 176.
  • a first anti- parallel diode D1 is connected between the collector 172 and the emitter 174 of the first transistor Q1.
  • the base 178 of the first transistor Q1 is coupled to a first control line G1.
  • the first node 176 is coupled to a first control reference line EK
  • the collector 182 of a second transistor Q2 is coupled to the first node 176.
  • the emitter 184 of the second transistor Q2 is connected to a second node 186.
  • a second anti-parallel diode D2 is connected between the collector 182 and the emitter 184 of the second transistor Q2.
  • the base 188 of the second transistor Q2 is coupled to a second control line G2.
  • the second node 186 is coupled to a second control reference line EK2.
  • the collector 192 of a third transistor Q3 is coupled to the second node 186.
  • the emitter 194 of the third transistor Q3 is connected to a third node 196.
  • a third anti-parallel diode D3 is connected between the collector 192 and the emitter 194 of the third transistor Q3.
  • the base 198 of the third transistor Q3 is coupled to a third control line G3.
  • the third node 196 is coupled to a third control reference line EK3.
  • the collector 102 of a fourth transistor Q4 is coupled to the third node 196.
  • the emitter 104 of the fourth transistor Q4 is connected to a fourth node 106.
  • a fourth anti-parallel diode D4 is connected between the collector 102 and the emitter 104 of the fourth transistor Q4.
  • the base 108 of the fourth transistor Q4 is coupled to a fourth control line G4.
  • the fourth node 106 is coupled to a fourth control reference line EK4 and to a negative DC supply line N.
  • a fifth diode D5 is coupled between the first node 176 and a fifth node 116.
  • a sixth diode D6 is coupled between the fifth node 116 and the third node 196.
  • the second node 186 provides a phase-output of the tri-level inverter 170 and the fifth node 116 provides a neutral line for the phase output.
  • parallel components may be used. For example, each transistor illustrated in Figure 16 may actually represent two or more parallel transistors.
  • Switched voltage states for the tri-level inverter 170 of Figure 16 can be realized as follows.
  • a first voltage state of zero volts across the second node 186 and the fifth node 116 can be achieved by (a) applying a low signal (for example, zero volts) to the first control line G1 with respect to the first control reference line EK1 ; (b) applying a high signal (for example, 15 volts DC) to the second control line G2 with respect to the second control reference line EK2; (c) applying a high signal (for example, 15 volts DC) to the third control line G3 with respect to the third control reference line EK3; and (d) applying a low signal (for example, zero volts) to the fourth control line G4 with respect to the fourth control reference line EK4.
  • a second output state of P volts (a positive voltage) across the second node 186 and the fifth node 116 can be achieved by (a) applying a high signal (for example, 15 volts DC) to the first control line G1 with respect to the first control reference line EK1 ; (b) applying a high signal (for example, 15 volts DC) to the second control line G2 with respect to the second control reference line EK2; (c) applying a low signal (for example, zero volts) to the third control line G3 with respect to the third control reference line EK3; and (d) applying a low signal (for example, zero volts) to the fourth control line G4 with respect to the fourth control reference line EK4.
  • a high signal for example, 15 volts DC
  • a third output voltage state of N volts (a negative output voltage) across the second node 186 and the fifth node 116 can be achieved by (a) applying a low signal (for example, zero volts) to the first control line G1 with respect to the first control reference line EK1 ; (b) applying a low signal (for example, zero volts) to the second control line G2 with respect to the second control reference line EK2; (c) applying a high signal (for example, 15 volts DC) to the third control line G3 with respect to the third control reference line EK3; and (d) applying a high signal (for example, 15 volts DC) to the fourth control line G4 with respect to the fourth control reference line EK4.
  • a low signal for example, zero volts
  • an output can deliver an alternating voltage with three values: P, zero and N.
  • the tri-level inverter 170 when connected to a typical load (see Figure 15), such as a motor (not shown), can be controlled so as to supply an approximately sinusoidal alternating current output for particular load conditions.
  • a typical load see Figure 15
  • This principle is illustrated in Figure 17, which is a timing diagram for the tri-level inverter 170 of Figure 16 illustrating an example output voltage between a time period to and a time period t
  • Voltage level U1 shows the voltage applied to the first control line G1 with respect to the first control reference line EK1.
  • Voltage level U2 shows the voltage applied to the second control line G2 with respect to the second control reference line EK2.
  • Voltage level U3 shows the voltage applied to the third control line G3 with respect to the third control reference line EK3.
  • Voltage level U4 shows the voltage applied to the fourth control line G4 with respect to the fourth control reference line EK4.
  • Figure 18 illustrates a top view of an embodiment of the single- phase tri-level inverter 170 of Figure 16 implemented in the base power module 10 of Figure 1.
  • the lead 30a of the base power module 10 is coupled to the fifth node 116 of the tri-level inverter 170 and the phase lead 30b of the base power module 10 is coupled to the second node 186 of the tri-level inverter 170.
  • Figure 19 is an electrical schematic of a three-phase, tri-level inverter 170. It comprises three phase circuits 170U, 170V, 170W, each of which is a single-phase tri-level inverter circuit as described in Figure 16. The three neutral lines neutral U, neutral V, neutral W may be coupled together to a single neutral bus (not shown).
  • multi-level inverters such as an inverter configured to operate in four, non-loaded voltage states, may be employed.
  • Figures 20 and 21 show an embodiment of the base power converter 10 configured with a high frequency capacitor 200 and a bulk capacitor 202, suitable for a variety of high power applications, for example, as a 600V, 800A inverter.
  • Figures 20 and 21 also illustrate a gate driver board 22 (not shown in Figures 1 and 2A so as to illustrate the structure under the gate driver board 22).
  • a second housing 216 receives the first housing 12, as well as both the high frequency capacitor 200 and the bulk capacitor 202.
  • the second housing 216 may provide an enclosure or channels to provide liquid cooling in the cold plate 14.
  • the high frequency capacitor 200 may be a film capacitor, rather than an electrolytic capacitor. This provides a tightly coupled, low impedance path for high frequency components of current.
  • the high frequency capacitor 200 may be physically coupled adjacent the gate driver board 22 via various clips, clamps, and/or fasteners 204, 206.
  • the high frequency capacitor 200 may overlay a portion of the first housing 12, and may be electrically coupled to the DC bus bars 34, 36 ( Figure 2A) via the terminals 24, 26, respectively.
  • the bulk capacitor 202 may be an electrolytic capacitor or a film capacitor such as a polymer film capacitor, and may be physically coupled adjacent the gate driver board 22 via various clips, clamps, and/or fasteners 208.
  • the bulk capacitor 202 may be electrically coupled to the DC bus bars 34, 36 via the terminals 24, 26, respectively.
  • the anode of the bulk capacitor 202 may be electrically coupled to the anode of the high frequency capacitor 200 and the cathode of the bulk capacitor 202 may be electrically coupled to the cathode of the high frequency capacitor 200 via DC interconnects.
  • the second housing 216 is provided to physically receive the high frequency capacitor 200, the bulk capacitor 202, the base power converter 10 and first housing 12.
  • the second housing 216 further accepts the cold plate 14, containing an inlet aperture 260 and outlet aperture 262 for liquid cooling of the cold plate 14.
  • the cold plate 14 may take the form of a pin finned aluminum silicone carbide (ALSIC) plate.
  • ALSIC pin finned aluminum silicone carbide
  • the use of ALSIC plate closely matches the thermal expansion properties of the substrate 40, thus reducing cracking and the void formation associated with thermal cycling.
  • This particular embodiment employs liquid cooling of the cold plate 14 via inlet 260 and outlet 262.
  • the high frequency capacitor 200 provides a very low impedance path for the high-frequency components of the switched current.
  • the prior art of high-frequency paths (sometimes called “decoupling” or “snubber” paths) placed a discrete package external to the module. Since this path included a significant stray inductance, the discrete package was large. For example, in one embodiment, the discrete capacitor is 1 uF.
  • the inclusion of the high frequency capacitor 200 serves the purpose better, but with only 50nF (5% of the capacitance). Further, this makes the capacitor so small it did not impact the size of the power module 10, thus completely eliminating the need for external hardware and volume requirements.
  • large capacitors are generally placed in a parallel arrangement between the positive and negative DC connections or from each DC connection to a ground or chassis. These large capacitors are commonly referred to as “X” or “Y” capacitors. Relatively large external capacitors of about around 100 micro Farads are needed.
  • external it is meant that the element referred to is located outside of a power module. High frequency noise, and voltage overshoots that are initiated in the module by the switching process travel away from the source of the noise and voltage overshoots. A low impedance network may be used to provide a return path for the high frequency energy associated with noise and voltage overshoots.
  • capacitors attached between the positive and negative DC connections or from the DC connections to ground must be relatively large to minimize the impact of noise, and voltage overshoots.
  • these external capacitors typically cause stray inductance, which renders the capacitor ineffective at frequencies higher than about 10 kHz.
  • the power semiconductor devices include a number of snubber capacitors 53 that are electrically coupled between the DC bus bars 34, 36 to clamp voltage overshoot.
  • some of the snubber capacitors 53 are electrically coupled directly (i.e., surface mounted) to the emitter plating 43a on the low side 20a of the power module 10 and are electrically coupled directly (i.e., surface mounted) to the collector plating 44b on the high side 20b of the power module 10.
  • the Figures show two snubber capacitors for each switching pair combination, the power module 10 may include fewer or a greater number of snubber capacitors as suits the particular application.
  • “Positive” elements are typically intended to be coupled to a positive terminal of a power source, while “negative” elements are intended to be coupled to a negative terminal or ground of the power source.
  • “positive” elements are located or coupled to the high side 20b of the power module 10 and “negative” elements are located or coupled to the low side 20a of the power module 10.
  • the power modules described above may employ various methods and regimes for operating the power modules 10 and for operating the switches (e.g., IGBTs 48).
  • the particular method or regime may be based on the particular application and/or configuration. Basic methods and regimes will be apparent to one skilled in the art, and do not form the basis of the inventions described herein so will not be discussed in detail for the sake of brevity and clarity.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Programmable Controllers (AREA)

Abstract

L'invention concerne une architecture destinée à un module de puissance, utilisant un degré élevé de modularité, qui permet à un module de puissance de base d'être configuré rapidement, facilement et à faible coût en vue d'adresser une grande variété d'applications simplement en échangeant des composants, des connexions électriques et/ou des logiciels.
PCT/US2004/015259 2003-05-16 2004-05-17 Systeme de module de puissance WO2004105220A2 (fr)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US47138703P 2003-05-16 2003-05-16
US60/471,387 2003-05-16
US10/642,424 US6987670B2 (en) 2003-05-16 2003-08-14 Dual power module power system architecture
US10/642,391 US6906404B2 (en) 2003-05-16 2003-08-14 Power module with voltage overshoot limiting
US10/642,424 2003-08-14
US10/642,391 2003-08-14
US10/658,804 2003-09-09
US10/658,804 US7505294B2 (en) 2003-05-16 2003-09-09 Tri-level inverter
US10/664,808 2003-09-17
US10/664,808 US7443692B2 (en) 2003-05-16 2003-09-17 Power converter architecture employing at least one capacitor across a DC bus

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WO2004105220A2 true WO2004105220A2 (fr) 2004-12-02
WO2004105220A3 WO2004105220A3 (fr) 2005-03-31

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US7456598B2 (en) 2004-12-03 2008-11-25 Continental Automotive Systems Us. Inc. Method, apparatus and article for load stabilization
CN105429438A (zh) * 2015-12-29 2016-03-23 湖北江汉建筑工程机械有限公司 一种施工升降机柜式变频器及施工升降机
EP3136580A4 (fr) * 2014-09-25 2018-01-24 Hitachi, Ltd. Unité de conversion de courant et dispositif de conversion de courant
WO2019081107A1 (fr) * 2017-10-23 2019-05-02 Danfoss Silicon Power Gmbh Module de puissance ayant des caractéristiques pour assemblage de module de puissance et de serrage
CN111628661A (zh) * 2019-02-28 2020-09-04 Abb瑞士股份有限公司 用于光伏电站的逆变器
DE102020207709A1 (de) 2020-06-22 2021-12-23 Zf Friedrichshafen Ag Steuergerät zum Betreiben eines Elektroantriebs für ein Fahrzeug und Verfahren zum Herstellen eines deratigen Steuergeräts
DE102008033473B4 (de) 2007-07-17 2023-03-09 GM Global Technology Operations LLC (n. d. Ges. d. Staates Delaware) Fahrzeugwechselrichteranordnung mit Kühlkanälen
USD983759S1 (en) * 2019-05-31 2023-04-18 Fuji Electric Co., Ltd. Semiconductor module

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7456598B2 (en) 2004-12-03 2008-11-25 Continental Automotive Systems Us. Inc. Method, apparatus and article for load stabilization
DE102008033473B4 (de) 2007-07-17 2023-03-09 GM Global Technology Operations LLC (n. d. Ges. d. Staates Delaware) Fahrzeugwechselrichteranordnung mit Kühlkanälen
EP3136580A4 (fr) * 2014-09-25 2018-01-24 Hitachi, Ltd. Unité de conversion de courant et dispositif de conversion de courant
US9906154B2 (en) 2014-09-25 2018-02-27 Hitachi, Ltd. Power conversion unit and power conversion device
CN105429438A (zh) * 2015-12-29 2016-03-23 湖北江汉建筑工程机械有限公司 一种施工升降机柜式变频器及施工升降机
CN105429438B (zh) * 2015-12-29 2018-08-14 湖北江汉建筑工程机械有限公司 一种施工升降机柜式变频器及施工升降机
WO2019081107A1 (fr) * 2017-10-23 2019-05-02 Danfoss Silicon Power Gmbh Module de puissance ayant des caractéristiques pour assemblage de module de puissance et de serrage
CN111628661A (zh) * 2019-02-28 2020-09-04 Abb瑞士股份有限公司 用于光伏电站的逆变器
USD983759S1 (en) * 2019-05-31 2023-04-18 Fuji Electric Co., Ltd. Semiconductor module
DE102020207709A1 (de) 2020-06-22 2021-12-23 Zf Friedrichshafen Ag Steuergerät zum Betreiben eines Elektroantriebs für ein Fahrzeug und Verfahren zum Herstellen eines deratigen Steuergeräts

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