WO2004105113A1

WO2004105113A1 - Polishing body for cmp polishing, cmp polishing apparatus, cmp polishing method, and method for manufacturing semiconductor device

Info

Publication number: WO2004105113A1
Application number: PCT/JP2004/006859
Authority: WO
Inventors: Susumu Hoshino; Norio Yoshida; Yuko Kitade; Osamu Shimoda; Takeya Yabuki
Original assignee: Nikon Corporation
Priority date: 2003-05-26
Filing date: 2004-05-14
Publication date: 2004-12-02
Also published as: JPWO2004105113A1; TW200513347A

Abstract

A polishing body for CMP polishing is disclosed which is preferably used in a CMP polishing method which enables to prevent excess polishing of the peripheral surface of a wafer. This polishing body for CMP polishing is composed of a polishing pad, a hard elastic member and a soft elastic member bonded together in this order, and the thickness of the soft elastic member is not more than a half of the thickness of the polishing pad.

Description

Specification

Polishing body for CMP polishing, CMP polishing apparatus, CMP polishing method, and semiconductor device manufacturing method.

The present invention relates to a polishing body for CMP polishing, a CMP polishing apparatus, a method of flattening a surface of Si ₂ formed on a surface of a Si substrate by polishing by CMP polishing, and a semiconductor device using the method. It relates to a manufacturing method of the. Background art

As semiconductor integrated circuits become more highly integrated and miniaturized, the number of semiconductor manufacturing process steps increases and becomes more complicated. As a result, the surface state of semiconductor devices is not necessarily flat. The presence of a step on the surface causes disconnection of the wiring, a local increase in the resistance value, etc., which leads to disconnection and a reduction in current capacity. In addition, the insulation film may lead to deterioration of withstand voltage and generation of leak.

On the other hand, the light source wavelength of optical lithography has become shorter with the increase in integration and miniaturization of semiconductor integrated circuits, and the numerical aperture, or NA, has become larger. I'm getting better. In order to cope with the shallow focal depth, flattening of the device surface is required more than ever.

Specifically, in the semiconductor manufacturing process, planarization technology as shown in Fig. 6 has become essential. FIG. 6 is a conceptual diagram of a planarization technique in a semiconductor manufacturing process, and is a cross-sectional view of a semiconductor device. Fig 6 , 11 is a silicon wafer, 12 is an interlayer insulating film made of SiO ₂ , 13 is a metal film made of A1, and 14 is a semiconductor device. FIG. 6 (a) shows an example of flattening the interlayer insulating film 12 on the surface of the semiconductor device. FIG. 6B shows an example in which a metal film 13 on the surface of a semiconductor device is polished to form a so-called damascene. As a method for planarizing the surface of such a semiconductor device, a chemical mechanical polishing (CMP) technique is widely used. At present, CMP technology is the only method that can planarize the entire surface of a silicon wafer.

CMP has been developed based on a mirror polishing method for silicon wafers, and is performed using a CMP apparatus as shown in FIG. Reference numeral 15 denotes a head for rotating the wafer 16 while holding the wafer 16 to be polished, and has a rotation drive mechanism 17. There is a rotary platen 19 having a polishing pad 18 attached thereto facing the head portion 15 and a rotary drive mechanism 20 thereof.These polishing pad 18, rotary platen 19, and rotary drive mechanism are provided. 20 is given swinging by the rotary actuator 21 and is driven up and down. In practice, the polishing pad 18 and other members may be combined and used in place of the polishing pad 18 shown in FIG. 7. Are referred to as "polishing bodies".

When performing polishing using such a CMP polishing apparatus, the wafer 16 and the polishing pad 18 are rotated at a high speed, and the rotary swing arm 21 is lowered by a vertical drive mechanism (not shown). Then, the wafer 16 is pressurized by the polishing pad 18. Then, a slurry as an abrasive is supplied between the polishing pad 18 and the wafer 16. Further, the rotary swing arm 21 is swung by a swing drive mechanism (not shown) as shown by a broken arrow. Then, the wafer 16 is polished by the relative rotation and swing of the polishing node 18 and the wafer 16. Is performed, and the surface is flattened. That is, good polishing is performed by the synergistic action of mechanical polishing by relative movement between the polishing pad 18 and the wafer 16 and chemical polishing by slurry.

By the way, unlike a wafer in a blank state, the surface of a wafer in which semiconductor integrated circuits are formed is not flat, and there is usually a step between the part where chips are formed and the part where chips are not formed. . Therefore, when such a wafer is polished, the wafer is polished uniformly along the irregularities (undulations), that is, along the irregularities (undulations) of a large cycle inevitably generated with the circuit formation. It is required to eliminate local irregularities (this is called “local pattern flatness”) while performing “wafer 'global' removal uniformity”.

A polishing pad that satisfies both “Ueno, 'global-removal uniformity” and “local' pattern flatness” is composed of a polishing pad, a hard elastic member, and a soft member stacked in this order. Is known (International Publication WO 03/0993362). In such a polished body, a hard elastic member is sandwiched between the polishing pad and the soft member. Pattern flatness "can be satisfied.

As described above, by using a polishing body having a three-layer structure in which a polishing pad, a hard elastic member, and a soft member are laminated in this order, an effective area of a wafer on which a circuit pattern is formed can be obtained. It can be polished flat. This effective area is defined as a part inside 3 mm from the outer periphery of the wafer. That is, no circuit pattern is formed in a portion within 3 mm from the outer periphery, and it is not necessary to polish this portion flat.

However, when a conventionally known polishing method is used, the polishing rate at the outer peripheral portion is higher than that at the inner portion, so that SiO 2 There is a problem that the _two parts are completely polished and lost, and the underlying Si is exposed. If the Si is exposed, dust and the like tend to adhere, and the attached dust and the like enter the polished surface and cause problems such as contaminating and damaging the polished surface.

For this reason, in the prior art, the retainer ring is arranged so as to surround the outer periphery of the wafer, and the outer peripheral surface of the wafer is protected by the retainer ring, thereby preventing the outer peripheral surface of the wafer from being excessively polished. However, such a retainer ring is a consumable item, so that not only does it cost much, but also it is difficult to adjust the height of the retainer ring. Disclosure of the invention

The present invention has been made in view of such circumstances, and a CMP polishing method capable of preventing the outer peripheral surface of a wafer from being excessively polished without using a special method such as using retaining ring. A first invention for achieving the above object is to provide a polishing body for CMP polishing suitable for use in a polishing method, a CMP polishing apparatus, and a method for manufacturing a semiconductor device using the CMP polishing method. The polishing pad is formed by laminating a polishing pad, a hard elastic member, and a soft elastic member in this order, and a thickness of the soft elastic member is 1 to 2 or less of a thickness of the polishing pad. This is a polishing body for CMP polishing.

A second invention for achieving the above object is the first invention, wherein the thickness of the soft elastic member is 0.2mni≤T≤0.5mm.

According to a third invention for achieving the above object, a polishing pad, a hard elastic member, and a soft elastic member are laminated in this order, and the soft elastic member has a thickness of 0.2111111≤0.1≤0.5111111. Characteristic polishing body for CMP polishing It is.

A fourth invention for achieving the above object is a CMP polishing apparatus for performing polishing by moving a substrate relative to a polishing body while making contact with the polishing body. A CMP polishing apparatus characterized by using any one of the polishing bodies for CMP polishing according to the third invention. Fifth invention for achieving the above object, the Si_〇 _second surface formed on the Si substrate surface, a method of planarizing by polishing by CMP polishing, third from the first aspect of the present invention _T is a CMP polishing method, characterized in that polishing is performed using the polishing body for CMP polishing according to any one of the inventions. T. The sixth invention for achieving the above object is the fifth invention. A method for manufacturing a semiconductor device, comprising a step of polishing a wafer by a CMP polishing method.

A seventh invention for achieving the above object, the surface of the Si O ₂ formed on the Si substrate surface, a method of planarizing by polishing by CMP polishing, polishing the polishing pressure as follows 1 psi And a CMP polishing method.

An eighth invention for achieving the above object is the seventh invention, wherein the polishing body used for the CMP polishing is formed by laminating a polishing pad, a hard elastic member, and a soft elastic member in this order. It has a three-layer structure.

A ninth invention for achieving the above object is a method of manufacturing a semiconductor device, comprising a step of polishing a wafer by the CMP polishing method of the seventh invention or the eighth invention.

BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a diagram showing an outline of a polishing body having a three-layer structure.

FIG. 2 is a diagram showing the polishing rate at each position on the wafer using the thickness (mm) of the foamed polyurethane as a parameter.

FIG. 3 is a diagram showing the polishing rate at each position on the wafer, based on the polishing pressure (pressure for pressing the polishing body against the wafer) as a parameter.

FIG. 4 is a diagram showing a relationship between a polishing pressure and a polishing rate in a steady portion. FIG. 5 is a flowchart showing a semiconductor device manufacturing process as an example of the embodiment of the present invention.

FIG. 6 is a conceptual diagram of a planarization technique in a semiconductor manufacturing process. FIG. 7 is a diagram showing an outline of a CMP apparatus used for CMP polishing. BEST MODE FOR CARRYING OUT THE INVENTION

'Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Example 1)

When polishing a SiO ₂ film formed on an 8-inch wafer using a Nikon Corporation CMP polishing machine (trade name: NPS 3301 (NPS is a registered trademark)), the edge of the wafer and its edge are removed. The extent to which the polishing rate in the inner part differs was investigated. As a polished body, as shown in Fig. 1, a 1.25 mm thick polishing pad IC1000 (trade name) manufactured by Rodel Co., Ltd. was stuck to a 0.2ιηηι SUS plate, and a 0.20 mm thick The SUS plate was made into a sandwich shape by bonding polyurethane foams of 0.5 mm and 1.25 mm in size. Note that this polishing body is a donut-shaped polishing body having an outer diameter of 170 mm and a hole having a diameter of 60 mm formed in the center.

The number of revolutions of the polishing body was set at 301 rpm, and the number of revolutions of the wafer was set at −10 rpm (reverse rotation with respect to the polishing body). The starting position of the polishing body is 22 mm from the center of rotation of the wafer, the moving stroke is 45 mm, and the swing speed is 40 min / sec. And The slurry was supplied at a ratio of 100 ml / rniri using SS25 (trade name) manufactured by Cabot Corporation. The polishing pressure (the pressure for pressing the polishing body against the wafer) was 2.0 psi.

Figure 2 shows the polishing rate at each position on the wafer, using the thickness of the foamed polyurethane as a parameter. 2, the horizontal axis represents a position on the wafer (the distance from the wafer center _[mm]), the vertical axis represents the Si_〇 ₂ in the polishing rate (A (Ogusu Toromu) / niin).

As can be seen from FIG. 2, when the thickness of the polyurethane foam is 1.25 mm, which is equal to the thickness of the polishing pad IC1000, the polishing rate at a position 3 mm from the outer periphery of the wafer sharply increases. As a result, as described above, the problem that SiO ₂ is completely lost and Si is exposed occurs.

However, when the thickness of the polyurethane foam becomes 0.5 mm, the polishing rate at a position from the outer periphery of the wafer to 3 mm begins to decrease, and when the thickness of the polyurethane foam becomes thinner than 0.2 mm, on the contrary, the wafer edge portion The polishing rate tends to be lower than that inside. Even if the polishing rate is lowered at the wafer edge, there is no problem because no pattern is formed at that portion.

From the tendency shown in Fig. 2, if the thickness of the foamed polyurethane, which is a soft elastic member, becomes 1 Z2 or less of the thickness of the polishing pad, the sharp polishing rate at a position up to 3 mm from the outer periphery of the wafer will increase. It can be estimated that the increase will no longer be seen.

Also, if the thickness of the foamed polyurethane, which is a soft elastic member, is 0.5 mm or less, it can be estimated that a sharp increase in the polishing rate at a position up to 3 mm from the outer periphery of the wafer will not be observed.

From the above, the surface of SiO ₂ formed on the surface of the Si substrate was A polishing body formed by laminating a polishing pad, a hard elastic member, and a soft elastic member in this order when flattening by polishing, wherein the thickness of the soft elastic member is If polishing is performed using a polished body with a thickness of 1/2 or less or a foamed polyurethane that is a soft elastic member with a thickness of 0.5 mm or less, polishing at the wafer edge will occur. It was found that the problem that Si was exposed due to the increase in the rate could be solved, and that the polishing rate in the wafer surface was not affected.

(Example 2)

When polishing a SiO ₂ film formed on a 12-inch wafer using Nikon Corporation's CMP polishing machine (trade name: NPS 3301 (NPS is a registered trademark)), the edge of the wafer is polished. We investigated how much the polishing rate differs between the part and the inner part. As a polishing body, a 1.25 mm thick polishing pad IC1000 (trade name) manufactured by Rodel Co., Ltd. is bonded to a 0.2 mm thick SUS plate, and a 1.25 mm thick foamed polyurethane is further bonded onto the SUS plate. The SUS plate was used in a sandwich shape. This abrasive body has an outer diameter of 266 mm, and is a donut-shaped abrasive body having a hole with a diameter of 84 mm formed in the center. Retainer rings were not used during polishing.

The rotation speed of the polishing body was set at 181 rpm, and the rotation speed of the wafer was set at 201 rpm (reverse rotation from the polishing body). The swinging start position of the polishing body was 27.5 mni from the center of rotation of the wafer, the rotating stroke was 85 mm, and the rotating speed was 40 mmZsec. The slurry was supplied at a flow rate of 150 ml / min using SS25 (trade name) manufactured by Cabot Corporation.

Figure 3 shows the polishing rate at each position on the wafer, using the polishing pressure (the pressure at which the polishing body is pressed against the wafer) as a parameter. In Figure 3, The horizontal axis is a position on a wafer (the distance from the wafer center [mm]), the vertical axis represents the Si_〇 _second polishing rate (A (Ogusu Toromu) / min).

As can be seen from FIG. 3, when the polishing pressure is 2 psi or 3 psi, the polishing rate increases rapidly up to 3 mm from the outer periphery of the wafer. As a result, as described above, the problem that Si 無く₂ is completely lost and Si is exposed occurs.

However, when the polishing pressure was reduced to 1 psi, there was no sharp increase in the polishing rate at the wafer edge, and when the polishing pressure was further reduced to 0.5 psi and 0.1 psi, the polishing rate at the wafer edge was conversely reduced. There is a tendency to decrease compared to the inside. Even if the polishing rate decreases at the wafer edge, there is no problem because no pattern is formed at that portion.

However, when the polishing pressure is reduced, the polishing rate in the steady part decreases, and there is a possibility that the polishing rate may not be practical. Therefore, the relationship between the polishing pressure and the polishing rate in the steady part was investigated under the same conditions as described above. Figure 4 shows the results. In FIG. 4, the horizontal axis is the polishing pressure (psi), and the vertical axis is the average polishing rate of SiO ₂ (A (ogstroms) / min). As shown in Fig. 2, between O.lpsi and 3.0 psi, the polishing rate decreases almost linearly, but the relationship between polishing rate and polishing pressure is proportional to what is generally known as Preston's equation. In contrast to this, it can be seen that even in the case of O. lpsi, it exceeds 1000 [AZ min] due to the high speed rotation of the wafer and the abrasive body (average relative speed 3.0 [m / sec]). This is a polishing rate sufficient for practical use.

From the above, when the surface of SiO ₂ formed on the surface of the Si substrate is planarized by polishing by CMP, the polishing pressure is set to 1 psi or less, and the polishing rate at the wafer edge is reduced. The problem of Si exposure due to the increase in Was found to be obtained. (Embodiment of the invention)

FIG. 5 is a flowchart illustrating a semiconductor device manufacturing process according to an embodiment of the present invention. When the semiconductor device manufacturing process is started, first in step S100, an appropriate processing step is selected from the following steps S101 to S104. According to the selection, the process proceeds to any of steps S101 to S104.

Step S101 is an oxidation step for oxidizing the surface of the silicon wafer. Step S102 is a CVD step of forming an insulating film on the surface of the silicon wafer by CVD or the like. Step S103 is an electrode forming step of forming electrodes on the silicon wafer by steps such as vapor deposition. Step 104 is an ion implantation step of implanting ions into the silicon wafer. 'After the CVD step or the electrode forming step, go to step S105. In step S105, it is determined whether or not to perform the CMP step, and if so, the process proceeds to step S106. If the CMP step is not performed, bypass S106. In the CMP step, the polishing apparatus according to the present invention performs planarization of the interlayer insulating film and formation of damascene S by polishing the metal film on the surface of the semiconductor device.

After the CMP process or the oxidation process, the process proceeds to Step S107. Step S107 is a photolithography process. In the photolithography process, a resist is applied to a silicon wafer, a circuit pattern is printed on the silicon wafer by exposure using an exposure apparatus, and the exposed silicon wafer is developed. Further, the next step S108 is an etching step in which portions other than the developed resist image are removed by etching, and thereafter, the resist is peeled off, and the unnecessary resist after etching is removed. Next, in step S109, it is determined whether or not all necessary processes have been completed. If not, the process returns to step S100, and the previous steps are repeated to form a circuit pattern on the silicon wafer. If it is determined in step S109 that all steps have been completed, the steps are terminated.

The CMP polisher according to the embodiment of the present invention is the same as the conventional CMP polisher shown in FIG. 7 except that the polishing body of the present invention is used, and therefore the description thereof is omitted.

Claims

Range of request

1. A polishing pad, a hard elastic member, and a soft elastic member are laminated in this order, and the thickness of the soft elastic member is 1 Z2 or less of the thickness of the polishing pad. Polishing body for CMP polishing.

2. The polishing body for CMP polishing according to claim 1, wherein the thickness of the soft elastic member is 0.2 mm≤T≤0.5 mm.

3. A polishing body for CMP polishing formed by laminating a polishing pad, a hard elastic member, and a soft elastic member in this order, wherein the thickness of the soft elastic member is 0.2 nmi T 0.5 mm.

4. A CMP polishing apparatus for performing polishing by relatively moving a substrate while contacting the polishing body, wherein the polishing body is any one of claims 1 to 3. A CMP polishing apparatus using a polishing body for CMP polishing.

5. A method of flattening a surface of SiO ₂ formed on a surface of a Si substrate by polishing by CMP polishing, wherein the CM according to any one of claims 1 to 3 is provided. A CMP polishing method, wherein polishing is performed using a polishing body for P polishing.

6. A method of manufacturing a semiconductor device, comprising a step of polishing a wafer by the CMP polishing method according to claim 5.

The 7. Si substrate surface formed Si_〇 _second surface, a method of planarizing by polishing by CMP polishing, CM P polishing and performing polishing a polishing pressure and a 1 psi or less Method.

8. The polishing body used in the CMP polishing has a three-layer structure in which a polishing pad, a hard elastic member, and a soft elastic member are stacked in this order. CMP polishing method.

9. A method for manufacturing a semiconductor device, comprising a step of polishing a wafer by the CMP polishing method according to claim 7 or 8.