WO2004099892A1 - Method of forming a reference voltage and structure therefor - Google Patents
Method of forming a reference voltage and structure therefor Download PDFInfo
- Publication number
- WO2004099892A1 WO2004099892A1 PCT/US2003/012082 US0312082W WO2004099892A1 WO 2004099892 A1 WO2004099892 A1 WO 2004099892A1 US 0312082 W US0312082 W US 0312082W WO 2004099892 A1 WO2004099892 A1 WO 2004099892A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- voltage
- bandgap
- circuit
- during
- duty cycle
- Prior art date
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Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
Definitions
- the present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
- bandgap regulators utilized various methods and structures to form bandgap regulators .
- these bandgap regulators utilized two dissimilar sized bipolar transistors as the basis of the bandgap regulator.
- a resistor was connected in series between the emitter of the larger transistor and the power source. The voltage developed across the resistor, and amplified by the ratio of the resistors, was utilized as a part of the stable bandgap reference voltage.
- the bandgap regulator was operated at low current levels, such as currents of less than two (2) micro-amps. At low current levels offset voltages developed at the input of the amplifier used to amplify the voltage across the resistor.
- FIG. 1 schematically illustrates an embodiment of a portion of a bandgap reference generator in accordance with the present invention
- FIG. 3 schematically illustrates a portion of another alternate embodiment of a portion of the bandgap reference generator of FIG. 1 in accordance with the present invention
- current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor
- a control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor
- FIG. 1 schematically illustrates a portion of an embodiment of a reference voltage generator 10 that has low power dissipation and produces an accurate reference voltage on a reference output 15.
- Generator 10 includes a selectable bandgap reference 11 that is operated by generator 10 at a duty cycle of less than one hundred percent (100%) .
- Generator 10 selectively enables and disables reference 11 with a duty cycle that is determined by a timing circuit 12 of generator 10.
- Reference 11 is formed to generate a bandgap output voltage on an output 21 when reference 11 is enabled.
- Reference 11 also includes an enable input 19, a reference cell 33, a selectable reference amplifier 36, a reference comparator 37, a disable transistor 39, an inverter 38, and a voltage valid output 22.
- Generator 10 also includes a storage element 13, a storage switch or transistor 14, and an amplifier 16.
- Storage transistor 14 is used to selectively couple output 21 to element 13 in order to store the value of the bandgap output voltage onto element 13 while reference 11 is enabled.
- the voltage stored on element 13 is utilized to maintain the reference voltage on output 15 when reference 11 is disabled.
- Amplifier 16 receives the voltage stored on element 13 and drives output 15 with the value of the reference voltage in order to generate the reference voltage value on output 15.
- Amplifier 16 preferably has a high input impedance in order to maintain the voltage stored on element 13.
- the input impedance generally is at least about one hundred (100) Giga-ohms.
- amplifier 16 is a voltage follower that is formed with MOS transistors and that has a gain of approximately one so that the value of the reference voltage on output 15 is substantially equal to the value of the voltage on element 13.
- reference cell 33 is formed to include a first reference transistor 32 and a second reference transistor 34.
- Transistor 32 is coupled to output 21 through series connected resistors 27 and 28.
- a node 29 is formed where resistors 27 and 28 are connected together.
- Transistor 34 is coupled to output 21 through a series connected resistor 31.
- a node 30 is formed at the connection between resistor 31 and transistor 34.
- transistors 32 and 34 are formed to have different sizes with transistor 32 being larger than transistor 34 as illustrated by the transistor symbols.
- cell 33 is a simplified representation of a bandgap cell and that cell 33 typically includes other well known elements of a bandgap reference .
- Timing circuit 12 is formed to generate the timing signal or enable signal that is applied to enable input 19.
- Timing circuit 12 typically forms the enable signal as a pulse with an asymmetrical waveform that is periodically generated.
- the duty cycle is less than one hundred percent (100%) and generally is less than fifty percent (50%) . In the preferred embodiment, the duty cycle is less than approximately three percent (3%).
- a voltage that is approximately equal to a difference in the base-emitter voltages of transistors 32 and 34 is formed across resistor 28.
- This voltage is commonly referred to as a delta Vbe voltage.
- Reference amplifier 36 equalizes the voltage of nodes 29 and 30, which allows amplifier 36 to amplify the delta Vbe voltage in order to form the bandgap output voltage on output 21.
- the voltage formed on node 30 is an internal voltage that is referred to as a Vbe voltage.
- Reference comparator 37 compares the value of the bandgap output voltage to the value of the Vbe voltage or internal voltage on node 30 in order to form a control signal or voltage valid signal on output 22.
- the voltage valid signal is representative of a difference between the output voltage and the internal voltage.
- the inverting input of comparator 37 is formed to have an offset voltage to facilitate proper operation when amplifier 36 is disabled.
- the value of the output voltage must be greater than the value of the internal voltage plus the offset voltage in order for the voltage valid signal to be high.
- the enable signal on input 19 is high, the value of the bandgap output voltage on output 21 is greater than the value of the internal voltage on node 30 plus the internal offset voltage of comparator 37, thus, comparator 37 drives the voltage valid signal high.
- the high voltage valid signal enables transistor 14 to couple the value of the bandgap output voltage to element 13 for storage.
- the offset voltage is approximately one hundred (100) millivolts.
- comparator 37 drives the voltage valid signal low indicating that the output voltage on output 21 is not valid and should not be used.
- the low voltage valid signal disables transistor 14 and element 13 is disconnected from output 21 thereby maintaining the value of the voltage stored on element 13. It should be noted that comparator 37 has to work when the input voltages received by comparator 37 are close to the value of return 18 as can be seen from the previous explanation. Designs to operate with such voltages are well known to those skilled in the art.
- the output of amplifier 36 is connected to a first terminal of resistor 27 and to a first terminal of resistor 31.
- a second terminal of resistor 27 is connected to node 29 and to a first terminal of resistor 28.
- An emitter of transistor 32 is connected to a second terminal of resistor 28.
- a collector and a base of transistor 32 are connected to voltage return 18.
- a second terminal of resistor 31 is connected to node 30 and to an emitter of transistor 34.
- a base and a collector of transistor 34 are connected to return 18.
- a non-inverting input of amplifier 36 is connected to node 30 and an inverting input is connected to node 29 while the output is connected to output 21 and to a non-inverting input of comparator 37.
- Enable input 35 of amplifier 36 is connected to input 19.
- An inverting input of comparator 37 is connected to node 30 while the output of comparator 37 connected to output 22.
- a source of transistor 39 is connected to return 18, a drain is connected to the non-inverting input of comparator 37, and a gate is connected to an output of inverter 38.
- An input of inverter 38 is connected to input 19.
- the drain of transistor 14 is connected to output 21 and the source is connected to a non-inverting input of amplifier 16 and to a first terminal of element 13.
- a gate of transistor 14 is connected to output 22 and to timing circuit 12.
- a second terminal of element 13 is connected to return 18.
- a non-inverting input of amplifier 16 connected to an output of amplifier 16 and to output 15.
- An output of timing circuit 12 is connected to input 19.
- amplifier 36, comparator 37, and inverter 38 are coupled to receive operational power from input 17 and return 18.
- the particular bandgap cell that is used within reference 11 may be any one of many different well know bandgap designs. Two such designs are illustrated in FIG. 2 and FIG. 3.
- FIG. 2 schematically illustrates a portion of a bandgap reference 80 that is an alternate embodiment of reference 11 that is explained in the description of FIG. 1.
- Reference 80 includes a bandgap cell 81 that is an alternate embodiment of cell 33 that is explained in the description of FIG. 1.
- a disable transistor 82 is used to connect the output of amplifier 36 to input 17 when amplifier 36 is disabled.
- Cell 81 and the operation thereof is well known to those skilled in the art.
- cell 81 may be used for cell 33 in generator 10 of FIG. 1.
- FIG. 3 schematically illustrates a portion of a bandgap reference 85 that is an alternate embodiment of reference 11 that is explained in the description of FIG. 1.
- Reference 85 includes a bandgap cell 86 that is an alternate embodiment of cell 33 that is explained in the description of FIG. 1.
- a disable transistor 87 is used to connect the output of amplifier 36 to input 17 when amplifier 36 is disabled.
- Cell 86 and the operation thereof is well known to those skilled in the art. In some embodiments, cell 86 may be used for cell 33 in generator 10 of FIG. 1.
- FIG. 4 schematically illustrates a portion of a timing circuit 70 that is a preferred embodiment of timing circuit 12 that is explained in the description of FIG. 1.
- Circuit 12 includes an analog relaxation oscillator 41, and an analog pulse shaper 42 that are utilized to form the low duty cycle enable signal that is applied to input 19.
- Circuit 70 is formed to provide low power dissipation and low current consumption in order to minimize the power dissipated by generator 10 (see FIG. 1) .
- Those skilled in the art will understand that a digital implementation or other implementations may be utilized as long as the enable signal provides a low duty cycle for generator 10.
- the analog implementation of circuit 70 provides a more controlled power dissipation than would a digital implementation because of the various frequency related power dissipation components of a digital implementation.
- a reference circuit 68 of circuit 70 provides threshold voltages that are used by oscillator 41 and shaper 42. Circuit 68 provides a first threshold voltage or low threshold voltage on an output 71 and a second threshold voltage or high threshold voltage on an output 72.
- Oscillator 41 includes a current source 48 and a current source 49 that are used to charge and discharge, respectively, a capacitor 51 at a very controlled rate to form the oscillation frequency of oscillator 41.
- Shaper 42 includes a capacitor 59 that is charged by the pulses of oscillator 41, a current source 58 that is used to charge capacitor 59 at a very controlled rate, and switch transistors 61 and 62 that are used to charge and discharge, respectively, capacitor 59.
- oscillator 41 runs at a predetermined frequency and generates a narrow pulse during each cycle of the oscillation. Each pulse increases the charge on a capacitor 59 of shaper 42.
- shaper 42 When the voltage stored on capacitor 59 reaches a certain voltage, shaper 42 generates a pulse that is used to form the enable signal that is applied to input 19. Assume that an RS flip-flop 47 is set and a transistor 53 is disabled. Current source 48 is utilized to charge capacitor 51 at a very controlled rate. When the voltage on capacitor 51 reaches the high threshold value, the output of comparator 52 goes high driving node 50 high. The high on node 50 enables transistor 61 to begin charging capacitor 59. Note that node 64 is low and the output of an inverter 66 is high, thus, the high from node 50 is applied to flop 47.
- the high on node 50 also resets flop 47 through gates 44 and 46, driving the Q bar output of flop 47 goes high enabling transistor 53 to begin discharging capacitor 51.
- node 50 goes low and disables transistor 61 to stop the charging of capacitor 59.
- the delay from node 50 through gates 44 and 46 and through flop 47 and through comparator 52 sets the amount of time that transistor 61 is enabled to charge capacitor 59. This delay is generally very small compared to the period of oscillator 41, thus, a very small charge is applied to capacitor 59 during each pulse of oscillator 41.
- the oscillations of oscillator 41 continue until capacitor 59 is charged to a voltage value that is at least equal to the high threshold value on output 72.
- generator 10 was formed to provide a reference voltage of approximately 1.2 volts on output 15 and to operate at a 2.2% duty cycle.
- the enable signal had a pulse width of about forty (40) micro-seconds and a period of about two (2) milli-seconds .
- Current through resistor 28 was formed to be approximately five (5) micro- amps when reference 11 was enabled and generator 10 correspondingly consumed a current of about thirty (30) micro-amps. With reference 11 disabled, generator 10 consumed a current of about ten (10) nano-amps . The total average current consumption of generator 10 was about 0.6 micro-amps.
- reference 11 used a large current through transistors 32 and 34 in order to form a reliable reference voltage, and consumed a small amount of current when disabled in order to lower the total power dissipation. Additionally at these current levels, the pole of generator 10 was at a frequency greater than about one Kilo-Hertz (iKHz) which improved the PSRR of generator 10.
- FIG. 5 schematically illustrates an enlarged plan view of a portion of an embodiment of a semiconductor device 75 that is formed on a semiconductor die 76.
- Generator 10 is formed on die 76 along with a load 77 that utilizes the reference voltage formed by generator 10.
- a novel device and method is disclosed. Included, among other features, is forming a voltage reference to operate a bandgap reference cell at a duty cycle that is less than one hundred per cent. Forming the voltage reference to operate at a high current level when enabled minimizes the low current effects from the reference voltage. The high current consumption minimizes the leakage current effects and also improves the power supply rejection ratio. Thus, the low duty cycle operation reduces the power dissipation of the reference generator and improves the accuracy of the reference voltage.
- the enable signal may be formed by various pulse generator implementations.
- the bandgap cell may use any one of many different implementations to form the reference voltage when the bandgap cell is enabled.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2003234137A AU2003234137A1 (en) | 2003-04-18 | 2003-04-18 | Method of forming a reference voltage and structure therefor |
PCT/US2003/012082 WO2004099892A1 (en) | 2003-04-18 | 2003-04-18 | Method of forming a reference voltage and structure therefor |
US10/512,767 US7285943B2 (en) | 2003-04-18 | 2003-04-18 | Method of forming a reference voltage and structure therefor |
CNB038141604A CN100492246C (en) | 2003-04-18 | 2003-04-18 | Method and structure of forming reference voltage |
TW093109162A TWI333602B (en) | 2003-04-18 | 2004-04-02 | Method of forming a reference voltage and structure therefor |
HK06101190.0A HK1081283A1 (en) | 2003-04-18 | 2006-01-26 | Method of forming a reference voltage and structure therefor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2003/012082 WO2004099892A1 (en) | 2003-04-18 | 2003-04-18 | Method of forming a reference voltage and structure therefor |
Publications (1)
Publication Number | Publication Date |
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WO2004099892A1 true WO2004099892A1 (en) | 2004-11-18 |
Family
ID=33434334
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/012082 WO2004099892A1 (en) | 2003-04-18 | 2003-04-18 | Method of forming a reference voltage and structure therefor |
Country Status (5)
Country | Link |
---|---|
CN (1) | CN100492246C (en) |
AU (1) | AU2003234137A1 (en) |
HK (1) | HK1081283A1 (en) |
TW (1) | TWI333602B (en) |
WO (1) | WO2004099892A1 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5068522B2 (en) * | 2006-12-08 | 2012-11-07 | 株式会社リコー | Reference voltage generation circuit |
US7764059B2 (en) * | 2006-12-20 | 2010-07-27 | Semiconductor Components Industries L.L.C. | Voltage reference circuit and method therefor |
US9218014B2 (en) * | 2012-10-25 | 2015-12-22 | Fairchild Semiconductor Corporation | Supply voltage independent bandgap circuit |
KR102455877B1 (en) * | 2016-02-15 | 2022-10-21 | 에스케이하이닉스 주식회사 | Voltage generation circuit and integrated circuit including the same |
TWI760023B (en) * | 2020-12-22 | 2022-04-01 | 新唐科技股份有限公司 | Reference voltage circuit |
CN115390610A (en) * | 2022-08-22 | 2022-11-25 | 哲库科技(北京)有限公司 | Power utilization system, frequency control method, chip and storage medium |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0661616A2 (en) * | 1993-12-29 | 1995-07-05 | AT&T Corp. | Bandgap voltage reference generator |
US6118266A (en) * | 1999-09-09 | 2000-09-12 | Mars Technology, Inc. | Low voltage reference with power supply rejection ratio |
US6400207B1 (en) * | 2001-04-03 | 2002-06-04 | Texas Instruments Incorporated | Quick turn-on disable/enable bias control circuit for high speed CMOS opamp |
US6535054B1 (en) * | 2001-12-20 | 2003-03-18 | National Semiconductor Corporation | Band-gap reference circuit with offset cancellation |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4772793A (en) * | 1987-10-05 | 1988-09-20 | The United States Of America As Represented By The United States Department Of Energy | Dead-time compensation for a logarithmic display rate meter |
FR2767589B1 (en) * | 1997-08-21 | 2000-07-21 | Sgs Thomson Microelectronics | “RESET” TYPE SUPPLY VOLTAGE MONITORING DEVICE |
-
2003
- 2003-04-18 CN CNB038141604A patent/CN100492246C/en not_active Expired - Fee Related
- 2003-04-18 WO PCT/US2003/012082 patent/WO2004099892A1/en not_active Application Discontinuation
- 2003-04-18 AU AU2003234137A patent/AU2003234137A1/en not_active Abandoned
-
2004
- 2004-04-02 TW TW093109162A patent/TWI333602B/en not_active IP Right Cessation
-
2006
- 2006-01-26 HK HK06101190.0A patent/HK1081283A1/en not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0661616A2 (en) * | 1993-12-29 | 1995-07-05 | AT&T Corp. | Bandgap voltage reference generator |
US6118266A (en) * | 1999-09-09 | 2000-09-12 | Mars Technology, Inc. | Low voltage reference with power supply rejection ratio |
US6400207B1 (en) * | 2001-04-03 | 2002-06-04 | Texas Instruments Incorporated | Quick turn-on disable/enable bias control circuit for high speed CMOS opamp |
US6535054B1 (en) * | 2001-12-20 | 2003-03-18 | National Semiconductor Corporation | Band-gap reference circuit with offset cancellation |
Also Published As
Publication number | Publication date |
---|---|
CN100492246C (en) | 2009-05-27 |
CN1662863A (en) | 2005-08-31 |
HK1081283A1 (en) | 2006-05-12 |
TW200510986A (en) | 2005-03-16 |
AU2003234137A1 (en) | 2004-11-26 |
TWI333602B (en) | 2010-11-21 |
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