WO2004084230A1 - 特殊書き込みモードを有する半導体記憶装置 - Google Patents

特殊書き込みモードを有する半導体記憶装置 Download PDF

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Publication number
WO2004084230A1
WO2004084230A1 PCT/JP2003/003446 JP0303446W WO2004084230A1 WO 2004084230 A1 WO2004084230 A1 WO 2004084230A1 JP 0303446 W JP0303446 W JP 0303446W WO 2004084230 A1 WO2004084230 A1 WO 2004084230A1
Authority
WO
WIPO (PCT)
Prior art keywords
storage device
semiconductor storage
write
write mode
special write
Prior art date
Application number
PCT/JP2003/003446
Other languages
English (en)
French (fr)
Inventor
Toshiya Uchida
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2003/003446 priority Critical patent/WO2004084230A1/ja
Publication of WO2004084230A1 publication Critical patent/WO2004084230A1/ja

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/229—Timing of a write operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

複数のデータ入力端子を有する半導体記憶装置において、各入力端子に入力される情報に応じて、“０”又は“１”を対応するメモリセルに書き込む第１の書き込み動作と、各入力端子に入力される情報に依らずに、“０”又は“１”を対応するメモリセルに書き込む第２の書き込み動作のどちらを行うかを判定する第１の判定手段と、前記第２の書き込み動作を行う場合に、各入力端子毎に、書き込み動作を行うか否かを判定する第２の判定手段とを有する構成とする。
PCT/JP2003/003446 2003-03-20 2003-03-20 特殊書き込みモードを有する半導体記憶装置 WO2004084230A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2003/003446 WO2004084230A1 (ja) 2003-03-20 2003-03-20 特殊書き込みモードを有する半導体記憶装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2003/003446 WO2004084230A1 (ja) 2003-03-20 2003-03-20 特殊書き込みモードを有する半導体記憶装置

Publications (1)

Publication Number Publication Date
WO2004084230A1 true WO2004084230A1 (ja) 2004-09-30

Family

ID=33018175

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2003/003446 WO2004084230A1 (ja) 2003-03-20 2003-03-20 特殊書き込みモードを有する半導体記憶装置

Country Status (1)

Country Link
WO (1) WO2004084230A1 (ja)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05282867A (ja) * 1992-04-02 1993-10-29 Nec Ic Microcomput Syst Ltd 半導体記憶回路
JPH0620474A (ja) * 1992-06-30 1994-01-28 Nec Corp 半導体メモリ回路
JPH0644780A (ja) * 1992-07-23 1994-02-18 Toshiba Corp 半導体記憶装置
JPH0676565A (ja) * 1992-06-30 1994-03-18 Nec Corp 半導体記憶装置
JPH06309878A (ja) * 1993-04-23 1994-11-04 Nec Ic Microcomput Syst Ltd 半導体記憶回路
JPH08249884A (ja) * 1995-03-08 1996-09-27 Sanyo Electric Co Ltd 半導体メモリのライトパービット回路
JP2001135082A (ja) * 1999-11-09 2001-05-18 Fujitsu Ltd 半導体集積回路およびその制御方法
JP2001351377A (ja) * 2000-06-08 2001-12-21 Matsushita Electric Ind Co Ltd 半導体記憶装置
JP2002208284A (ja) * 2000-11-13 2002-07-26 Toshiba Corp 半導体記憶装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05282867A (ja) * 1992-04-02 1993-10-29 Nec Ic Microcomput Syst Ltd 半導体記憶回路
JPH0620474A (ja) * 1992-06-30 1994-01-28 Nec Corp 半導体メモリ回路
JPH0676565A (ja) * 1992-06-30 1994-03-18 Nec Corp 半導体記憶装置
JPH0644780A (ja) * 1992-07-23 1994-02-18 Toshiba Corp 半導体記憶装置
JPH06309878A (ja) * 1993-04-23 1994-11-04 Nec Ic Microcomput Syst Ltd 半導体記憶回路
JPH08249884A (ja) * 1995-03-08 1996-09-27 Sanyo Electric Co Ltd 半導体メモリのライトパービット回路
JP2001135082A (ja) * 1999-11-09 2001-05-18 Fujitsu Ltd 半導体集積回路およびその制御方法
JP2001351377A (ja) * 2000-06-08 2001-12-21 Matsushita Electric Ind Co Ltd 半導体記憶装置
JP2002208284A (ja) * 2000-11-13 2002-07-26 Toshiba Corp 半導体記憶装置

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