WO2004077499A2

WO2004077499A2 - Method for integration of single and dual gate logic into one mask set

Info

Publication number: WO2004077499A2
Application number: PCT/IB2004/050128
Authority: WO
Inventors: Albert J. Huitsing; Rene R. Voshol; Johannes M. A. M. Van Kempen
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2003-02-28
Filing date: 2004-02-18
Publication date: 2004-09-10
Also published as: WO2004077499A3

Abstract

The present invention relates to a method for fabrication of semiconductor devices providing a predetermined number of at least one particular function, each constituted by an elementary integrated circuitry. A plurality of said elementary integrated circuitries are arranged on a wafer by a usual semiconductor process, such that groups with a predetermined number of said elementary integrated circuitries, which will be incorporated within one of said final semiconductor devices, can be determined in a back-end step of the semiconductor production process. In one of the last production steps electrical connections are made between said elementary integrated circuitries within each of said groups by a semiconductor process step. The final wafer is diced into dies, where each die contains one of said groups of said elementary integrated circuitries. Thus, the wafer can be seen as a chocolate bar, which can be broken into small chunks and bigger chunks, which are defined by the predetermined breaking lines of the chocolate bar. In this metaphor a small chocolate chunk corresponds to a die containing one elementary integrated circuitry and a bigger chunk corresponds to a die containing a group of elementary integrated circuitries, which are electrically connected. Therefore, this method has been named chocolate method.

Description

Chocolate method for integration single and dual gate logic into one mask set

The present invention relates to a method for fabrication of semiconductor devices according to claim 1 and a semiconductor device made by such method according to claim 7.

More specifically, the invention relates to a method for fabrication of semiconductor devices providing a predetermined number of at least one particular function, each constituted by an elementary integrated circuitry. Further, the invention relates to a semiconductor device made by the method according to the invention which comprises at least a power supply lead and a reference potential lead, at least one input signal lead and at least one output signal lead, and at least two elementary integrated circuitries, each of said elementary integrated circuitries providing a particular function.

One of the major challenges of today's digital processing industry is overall system cost reduction while complexity and functionality increase. As a result, circuit integration and board miniaturization become necessary for success in a competitive market. Single and dual gate semiconductor devices, which provide a single or dual logic function, packed in a standardized package are one important example of this evolutionary process. These devices offer popular functions such as AND, NAND, OR, NOR, INV, etc. in a space saving package that can be placed in any desired position on a circuit board. Moreover, one major advantage over multiple-gate devices is obvious: there is no longer need for routing of multiple leads from distinct partitions on a printed circuit board through one multiple-gate logic device, which results in shortening and simplifying of routes on the board and thus avoids a waste of board space. This allows straightforward implementation of products and shortens time to market. Given its broad range of application possibilities, gate logic devices are an ideal product for all electronic markets. Therefore, such low cost logic components form today a significant part of the sales of component manufactures.

However, market forces built up high pressure also on the side of component manufactures: as feature sizes have to be reduced permanently in IC production, development costs increase and become more and more the critical competitive factor. For instance, a single mask set for fabrication of a specific semiconductor component costs round about 100k US-Dollars. As mentioned above, single-gates and dual-gates portfolios of a component manufacturer form nowadays a significant part of sales. With respect to development and production cost, for both portfolios two complete mask sets of a particular function are needed and the whole developing process has to be done twice, though a single gate device is not that different from a dual gate device, except for pin count and pin layout.

Therefore, it is an object of the present invention to provide an improved method for fabrication of semiconductor devices, in particular of single and dual gate devices, which brings a reduction of the development costs. It is a further objective to provide more flexibility with regard to the production decision between single and dual gate devices and thus, reduce the reaction time to market demands.

Accordingly, the improved method for fabrication of semiconductor devices providing a predetermined number of at least one particular function, each constituted by an elementary integrated circuitry comprises the following steps:

Firstly, a plurality of the elementary integrated circuitries are arranged on a wafer by a semiconductor process, which can be carried out using any known semiconductor technology. The plurality of elementary integrated circuitries are preferably arranged substantially in a matrix like manner on the wafer. In each field of the matrix there is one of the elementary integrated circuitries, such that columns and rows of the matrix are formed by such arranged elementary integrated circuitries. It goes without saying that the orientation of the matrix can be chosen independently of the wafer orientation. In each column of the matrix the circuitry layout of adjacent elementary integrated circuitries is substantially symmetrical or point-symmetrical to each other. In each row of the matrix the circuitry layout of adjacent elementary integrated circuitries is substantially symmetrical or point- symmetrical to each other. Such arrangement of the circuit layouts on the wafer makes sure that, in case the used bonder of the semiconductor processing apparatus is not capable of rotating dies, and therefore, it is necessary to process the wafer twice, where in the first run the 180 degrees rotated dies are skipped and processed after the total wafer is rotated 180 degrees, in both positions substantially the same number of dies is bonded.

Secondly, there is a step where groups with a predetermined number of the elementary integrated circuitries are defined. The predetermined number of the elementary integrated circuitries will be incorporated within one of the semiconductor devices produced by the method according to the invention. Thus, one group comprises the predetermined number of the elementary integrated circuitries, preferably such a group comprises adjacent elementary integrated circuitries of a row of the matrix on the wafer.

Thirdly, electrical connections are formed by a semiconductor process step between the elementary integrated circuitries within each of the groups on the wafer. In a preferred embodiment of the invention, in the step of forming the electrical connections between the elementary integrated circuitries in each of the predetermined groups a common power supply node and a common node for a fixed reference potential for each elementary integrated circuitry within each predetermined group are provided. Fourthly, the wafer is diced into dies, wherein each die contains exactly one of the predetermined groups of the elementary integrated circuitries.

Accordingly, a semiconductor device made by the method of the present invention comprises at least a power supply lead and a reference potential lead, at least one input signal lead and at least one output signal lead, and at least two elementary integrated circuitries on a single die, each of the elementary integrated circuitries providing a particular function. The elementary integrated circuitries preferably provide a particular function between at least one input lead and at least one output lead of the semiconductor device.

As to a particular function realized by an elementary integrated circuitry, that may be a Boolean logic function, a buffer circuit, a Schmitt Trigger, a multiplexer, an analog switch, a flip-flop, or any other suitable function. In those cases, the produced devices are compatible with the known families of dual and triple gate devices. Such devices have a power supply lead for supplying a supply voltage and a lead for a fixed reference potential, e.g. ground of the connected circuit of the printed circuit board to which the logic device is mounted in a specific application, and of course necessary input and output leads for the particular functions. For instance, a 1G00 is a single logic gate device, which provides the Boolean NAND function between two input signals at one output lead.

As to the elementary integrated circuitries on the wafer, each of these is substantially surrounded by a seal ring. This seal ring integrated into the wafer during the semiconductor process in which the elementary integrated circuitries are arranged on the wafer, provide the area designated for attaching a final die to the package of the device by welding or soldering techniques. In a preferred embodiment of the invention, the seal rings of two or more elementary integrated circuitries, which are to be contained on a single die, are electrically connected to each other and - depending on the semiconductor manufacturing technology - to the common reference potential lead or power supply lead of the semiconductor device and to each of the integrated circuitries.

Further, electrical interconnections are arranged between the elementary integrated circuitries connecting at least the reference potential lead and the common power supply lead of the semiconductor device with each of the integrated circuitries. The reference potential connection and power supply connection between the elementary integrated circuitries are realized by metal tracks which are made in the back-end of the fabrication of the semiconductor device. For instance, when a p-substrate technology is applied, a metal track cuts through the seal rings of the adjacent elementary integrated circuitries to merge the power supply rails of all elementary integrated circuitries. Additionally, the seal rings of the adjacent elementary integrated circuitries are connected via metal tracks for providing a common reference potential to both elementary integrated circuitries. Since the aforementioned embodiment is based on a p-substrate technology the seal rings are grounded, however, when the concept of the present invention is used with an n-substrate technology, then the seal ring is to be connected to Vic, and GND is to be connected to both elementary integrated circuits in the way as described herein for Vic.

Preferably, the elementary integrated circuitries have substantially comparable circuitry layouts. In a standard case the layout of the elementary integrated circuitries may be substantially identical, e.g. each circuitry provides a same logic function, but it is also possible to provide two ore even more different functions on a die produced according the present invention and thus, in one semiconductor device. This means with respect to the preferred embodiments of the invention where two or three identical logic functions are implemented in one semiconductor device, that such a device may also provide two or more different functions, e.g. one NAND and one OR logic function. Advantageously, during the fabrication process of the elementary logic functions, different logic functions can be realized by only some small changes in some of the metal mask steps. This requires only the change of only some masks in the mask set and not the change of the entire mask set of the whole process. In this way, the fabrication process according to the method of the invention becomes even more flexible: in one mask set only some masks have to be adapted for providing different functions within the elementary integrated circuitries on the wafer, and by means of only some masks in the back-end of the process the number of these elementary integrated circuitries can be determined which are to be electrically interconnected and thus, are contained on one final die, which is to be incorporated in one semiconductor device according the present invention. In the preferred embodiment, the particular functions are electrically independent of each other with respect to the input leads and output leads. This means that the elementary integrated circuitries which provide the particular functions between the input and output leads of the semiconductor device will have no effect on each other; however, due to the electrical interconnection made between the elementary integrated circuitries they will have a common connection to a power supply, e.g. a supply voltage Vac, and a common connection to a fixed reference potential, e.g. a ground potential GND, where these common connections correspond to respective leads of the semiconductor device.

In a preferred embodiment of the invention the predetermined number of the particular elementary functions in one group is two and thus, the semiconductor device is a dual gate device. Accordingly, as regards the circuitry layout, two particular elementary integrated circuitries arranged adjacent to each other on the die of a specific semiconductor device are point-symmetrical. This fact results from the pin layout configuration of the 2GXX products, i.e. the device that contains two respective 1GXX functions. For instance, a 1 GO 1 contains a 2-Input NOR gate and a 2G02 provides two 2-Input NOR gates, where, as regards the pin layout, the respective logic gates are point symmetrical. Thus, by a point- symmetrical arrangement of the adjacent elementary integrated circuits on the die, the configuration of the respective bonding pads on the die is compatible with the pin layout of the device. However, it is possible that in the future pin layout may change and that rotation is no longer needed. In another embodiment of the invention the predetermined number of the particular elementary functions in one group is three and thus, the semiconductor device is a triple gate device. However, it is noted that the invention is not restricted to two or three elementary integrated circuitries in one group.

The above and other objectives, features and advantages of the present invention will become more clear from the following description of one preferred embodiment thereof, taken in conjunction with the accompanying drawings. It is noted that in all drawings, identical or equivalent parts bear the same reference number. All drawings are intended to illustrate some aspects and embodiments of the present invention. Moreover, it should be noted that in the case of different embodiments only differences are described in detail. Circuits are depicted in a simplified way for reason of clarity. It goes without saying that not all alternatives and options are shown and therefore, the present invention is not limited to the content of the accompanying drawings. In the following, the present invention will be described in greater detail by way of example with reference to the accompanying drawings, in which

Fig. 1 shows a wafer containing a plurality of elementary integrated circuitries, of which each performs an identical logic function, a single elementary integrated circuitry is marked as it will be sawn out during dicing of the wafer; Fig. 1 further shows an example of a single die, which is also illustrated in an enlarged view;

Fig. 2 depicts a number of elementary integrated circuitries in greater detail as arranged on the wafer in Fig. 1 together with the scribe lanes along which the wafer is sawn or broken during dicing; Fig. 3 is an enlarged view of a single die of Fig. 1 or Fig. 2 as diced from the wafer and incorporated into the final semiconductor device;

Fig. 4 shows a wafer containing a plurality of elementary integrated circuitries, of which each performs an identical logic function, two adjacent elementary integrated circuitries are marked as they will be sawn out during dicing of the wafer; Fig. 4 further shows an example of a single die, which is also illustrated in an enlarged view;

Fig. 5 depicts a number of elementary integrated circuitries in greater detail as arranged on the wafer in Fig. 4 together with the scribe lanes along which the wafer is sawn or broken during dicing;

Fig. 6 is an enlarged view of a single die of Fig. 4 and Fig. 5 as diced from the wafer and incorporated into the final semiconductor device;

Fig. 7 depicts an example of the semiconductor device of Figs. 1 to 3 implemented in a standard component package; and

Fig. 8 depicts an example of the semiconductor device of Figs. 4 to 6 implemented in a standard component package.

Fig. 1 shows a wafer 10, e.g. a silicon wafer, containing a plurality of elementary integrated circuitries 20, of which each performs an identical logic function. From Fig. 1 it can clearly be seen how the elementary integrated circuitries 20 are arranged in a matrix- like manner comprising rows R and columns C, both of which are indicated by dotted arrows in Fig. 1. It goes without saying that the orientation of the rows R and columns C of the matrix can be chosen independently of the wafer orientation. A single elementary integrated circuitry 21 is marked to demonstrate how it will be sawn out during dicing of the wafer 10. Further, there is shown an example of a single diced die 30, which is also illustrated in an enlarged view. As to the elementary integrated circuitries 21 and the die 30, they will be referred to in more detail in Fig. 3.

Fig. 2 depicts, on an enlarged scale and in more detail, a fraction of the wafer 10 of Fig. 1. A number of elementary integrated circuitries 20 are shown as arranged on the wafer 10 of Fig. 1 together with the scribe lanes 32, also known as scribe streets, along which the wafer 10 in Fig. 1 will be diced by for instance an adequate sawing or breaking method. Again dotted arrows indicate rows R and columns C of the matrix formed by the elementary circuitries 20 on the wafer. Further, it can be derived from the marked scribe lines 32 that each elementary integrated circuitry 20 will be on a single die 30 after the wafer is diced. It can also clearly be seen from Fig. 2 that, as regards the circuit layout, all elementary integrated circuitries 20 in each column C are symmetrically orientated, while in each row R, adjacent elementary integrated circuits 20 are point-symmetrically orientated.

Fig. 3 is an enlarged view of a single die 40, which corresponds to a die 30 of Fig. 1 or Fig. 2, containing one of the elementary integrated circuitries 20 of Fig. 1 or Fig. 2 as it is when diced from the wafer 10 and incorporated into the final semiconductor device, e.g. the final logic gate device as shown in Fig. 7. In the embodiment of the invention described here the elementary integrated circuitry 20 on the die 40 is a circuit for a single logic gate device, which, by way of example, provides a single Boolean NAND function, and is also known as 1G00 single gate device. It is clear for the skilled person that any other suitable function, e.g. a Boolean logic function, a buffer circuit, a Schmitt Trigger, a multiplexer, an analog switch, a flip-flop, can be used together with the method according to the invention and thus lead to a device according to the present invention. The integrated circuitry of the die 40 is not shown in detail since it is not relevant for the understanding of the present invention. Thus, only the bond pads which are provided for connecting the elementary circuitry 20 contained in the die 40 are shown. However, from the arrangement of these bond pads the orientation of the whole circuit layout of the elementary integrated circuitry 20 can be derived.

There are two bond pads 42 and 43 for connecting the input signals A and B to the integrated logic NAND function and further there is the bond pad 44 for the output signal Y of the integrated NAND function. For supplying the elementary integrated circuitry with a supply voltage Vcc there is a bond pad 46 for connecting the power supply and a power supply rail 47, which provides the supply voltage Vcc to the whole integrated circuitry 20. There is also a bond pad 48 for connecting a reference potential, e.g. ground signal GND, to the whole integrated circuitry 20. The bond pad 48 is also electrically connected with a seal ring 34 of the die by a circuit track 49.

According to the invention the power supply bond pad 46 and the power supply rail 47, illustrated in black, are processed during the fabrication in the back-end of the semiconductor process, which is a metal process step. However, it is also possible to provide these electrical connections in another metal layer. It will be clear, also see Fig. 6, that only this point in the fabrication requires some different processing steps, and thus for the remaining steps the same masks of the mask set can be used for the production of at least two different semiconductor devices. This brings a reduction in cost and more flexibility for the fabrication process.

Fig. 4 shows again the wafer 10 containing a plurality of elementary integrated circuitries 20, of which each provides an identical logic function. The elementary integrated circuitries 20 are arranged exactly as described in Fig. 1 and thus will not be described again in detail. However, in the embodiment according to the improved fabrication method of the invention, two elementary integrated circuitries 21 and 22, which are arranged adjacent to each other in a row R of the matrix, are marked, as they will be sawn out together during dicing of the wafer 10. Again, an example of the single diced die 30 is shown, which is also illustrated to an enlarged scale. The elementary integrated circuitries 21 and 22 and the die 30 will be referred to in more detail in the description of Fig. 6. Fig. 5 depicts in an enlarged and more detailed view, a fraction of the wafer 10 of Fig. 4. A number of elementary integrated circuitries 20 are shown as arranged on the wafer 10 of Fig. 4 together with the scribe lanes 32 along which the wafer 10 of Fig. 4 will be diced. Again, dotted arrows indicate rows R and columns C of the matrix formed by the elementary circuitries 20 on the wafer. Further, it can be derived from the marked scribe lines 32 that two adjacent elementary integrated circuitries 20 in each row R will be together on a single die 30 after the wafer is diced. It can also clearly be seen from Fig. 5 that the circuit layouts of each elementary integrated circuitry 20 in each column C are symmetrically orientated to each other, while in each row R the circuit layouts of adjacent elementary integrated circuits 20 are point-symmetrically orientated to each other. As already mentioned, adjacent dies in a row R are rotated with respect to each other due to the pin layout configuration of the 2GXX product, i.e. the device which contains two 1GXX functions (here XX stands for a particular logic gate function, e.g. XX = 00 is the logic NAND function). Thus, the final dies can easily be bonded to the leads of the package of the device. However, it is possible that in the future pin layout may change and rotation is no longer needed. Fig. 6 shows, on an enlarged scale, a die 50, which corresponds to the dies 30 of Fig. 4 and Fig. 5, as it is to be diced from the wafer 10 and to be incorporated into the final semiconductor device, i.e. the final logic gate device. In the embodiment of the invention herein described, each of the two elementary integrated circuitries 21 and 22 on the die 50 is a circuit for a single logic gate device, which provides a single Boolean NAND function. Since two of these logic NAND functions are provided by the die 50, it forms a 2G00 dual gate device. The integrated circuitry of the die 50 is also not shown in detail since it is not relevant for the invention and it is known to the skilled person. Thus, only the bond pads through which the elementary integrated circuitries contained in the die 50 can be connected are shown. From the arrangement of these bond pads also the orientation of the whole circuit layout of the elementary integrated circuitries 21 and 22 can be derived.

The elementary integrated circuitry 21 provides two bond pads 42a and 43 a for connecting the input signals Al and Bl to the integrated logic NAND1 function, and further the bond pad 44a for the output signal Yl of the integrated NAND1 function. As to the elementary integrated circuitry 22, which is point-symmetrically orientated with respect to the elementary integrated circuitry 21 on the left side of the die 50, it provides two bond pads 42b and 43b for connecting the input signals A2 and B2 to the integrated logic NAND2 function, and further the bond pad 44b for the output signal Y2 of the integrated NAND2 function. For supplying the two elementary integrated circuitries 21 and 22 on the die 50 with a common supply voltage Vcc, there is provided a bond pad 56 for connecting the power supply with a power supply rail 57, which provides the supply voltage Vcc to both integrated circuitries 21 and 22. It goes without saying that the power supply rail 57, which is connected to the power supply bond pad 56 for supplying both elementary integrated circuitries with the Vcc voltage, cuts through the seal rings 34a and 34b. It should be noted that for a better mechanical stability of the final die, which contains both - or even more - elementary integrated circuitries, an extra top passivation layer may be used, e.g. an additional silicon nitride or silicon oxide layer. This may be achieved with a final passivation mask step and will result in preventing the desired dies from breaking along the scribe lanes between two adjacent elementary integrated circuitries, which have been electrically interconnected. Thus, the fabrication output is advantageously increased.

For connecting a common ground signal GND to the integrated circuitries 21 and 22, there is provided a bond pad 58. The bond pad 58 is electrically connected via a metal track 59 with the seal ring 34b of the elementary integrated circuitry 22 and by means of metal tracks 36a and 36b with the seal ring 34a of the elementary integrated circuitry 21. Individual bond pads for ground comiection 48a and 48b of the particular elementary integrated circuitries 21 and 22 are connected via metal tracks 49a and 49b to the respective seal rings 34a and 34b, so that there is no need to use these for bonding when packaging the final semiconductor device. For the sake of completeness, it is noted that the given example of a preferred embodiment is based on a p-substrate technology, therefore the seal rings are grounded, i.e. connected to the common GND node of the device. However, it is also possible to apply the concept of the present invention to an n-substrate technology, where the seal ring is connected to Vcc, and GND is connected to both elementary integrated circuits in the way described herein for Vcc.

According to the invention, the power supply bond pad 56, the power supply rail 57 and the ground bond pad 58, illustrated in black, are processed during fabrication in the back-end semiconductor process, which is a metal process step. Now it becomes very clear that in comparison with Fig. 3 up to this point the fabrication of at least two different semiconductor devices is identical, as it is described for 1G00 or 2G00 devices as examples for a preferred embodiment of the invention.

To the skilled person it is general knowledge that a couple of individual mask steps are needed to realize the interconnection between adjacent elementary integrated circuits according to the present invention. For instance, in one way of setting up the electrical interconnection three mask steps are used, where the electrical interconnections between two adjacent elementary integrated circuits are made in a last metal step, i.e. there are one metal, one interconnect and one nitride mask steps. Another possibility is to connect two adjacent elementary integrated circuits in a lower metal layer, wherein four mask steps are needed, i.e. there are one metal, two interconnect, and one nitride mask steps. However, it should once again be emphasized that only this part in the fabrication of at least two different semiconductor devices is different, and thus the same set of optical masks is used in the remaining fabrication steps. Since the cost of a mask increases quite rapidly with the scaling of technology, a reduction of the number of masks brings a desired reduction in cost.

Figs. 7 and 8 depict by way of example the final semiconductor devices, which can be fabricated by the method according to the present invention wherein one mask set can be used for both. It has been clearly demonstrated that only during the last semiconductor production process step, which is a metal process step, it can be decided whether to make single gate or dual gate devices in such a way that no valuable die area is sacrificed and, moreover, a saving in development and mask costs is achieved. Thus, Fig. 7 shows a 1G00 single gate logic device, which provides one Boolean NAND logic function in a standard 5- pin package 70. The package 70 has five leads L, of which one is the power supply lead Vcc and the ground lead GND. Further, there are two input leads A and B which connect two input signals with the integrated logic gate NAND function. The output signal is provided at an output lead Y. In Fig. 8 the corresponding dual gate logic device 2G00 is illustrated which provides two Boolean NAND logic functions, NAND1 And NAND2, within one standard package 80. The package 80 has eight leads L, of which one is a power supply lead Vcc and one is a ground lead GND. Further, there are two input leads Al and Bl which connect two first input signals with the first integrated logic gate NAND1 function. Furthermore, there are two input leads A2 and B2 which connect two second input signals with the second integrated logic gate NAND2 function. The first output signal of the first integrated logic gate NAND1 function is provided at an output lead Yl and the second output signal of the second integrated logic gate NAND2 function is provided at an output lead Y2.

The above-presented invention has introduced a method for fabrication of semiconductor devices providing a predetermined number of at least one particular function, each constituted by an elementary integrated circuitry. A plurality of said elementary integrated circuitries is arranged on a wafer by a usual semiconductor process, such that groups with a predetermined number of said elementary integrated circuitries, which will be incorporated within one of said final semiconductor devices, can be determined in the back- end of the semiconductor production process. In one of the last production steps electrical connections are installed between said elementary integrated circuitries within each of said groups by a semiconductor process step. The final wafer can be diced into dies, where each die contains one of said groups of said elementary integrated circuitries. Thus, the wafer can be seen as a chocolate bar, which can be broken into small chunks or bigger chunks, which are defined by the predetermined breaking lines of the chocolate bar. In this metaphor a small chocolate chunk corresponds to a die containing one elementary integrated circuitry and a bigger chunk corresponds to a die containing a group of elementary integrated circuitries, which are electrically connected. Therefore, this method has been named chocolate method. It should be noted that the present invention is not restricted to the embodiment of the present invention; in particular the invention is not restricted to a 2G00 type dual gate logic device, which has been used in this specification by way of example. Moreover, the principle of the present invention can be applied to any semiconductor fabrication process where the functional circuitry of a device family can be subdivided into elementary integrated circuitries, which can be used as stand-alones within a semiconductor device or which can be incorporated functionally independently as described together with the invention. However, it goes without saying that it is possible to have different elementary integrated circuitries arranged on a wafer according to the invention and to connect a specific combination of such different elementary integrated circuitries in a final semiconductor process step for implementation in a semiconductor device. Moreover, it is clear to the skilled person that it is also within the scope of the invention that such a combination of elementary integrated circuitry will also enable combining the electrical functions which are performed by the elementary integrated circuitry, such that a circuit with a more complex function between the input and output signals of the whole circuit can be built. Therefore, by virtue of the invention a substantial improvement of the semiconductor production has been introduced which enables both development and production costs to be saved. Moreover, the present invention provides more flexibility in steering the production output of different semiconductor devices since the final decision as to which device will have to be produced can be deferred to nearly the very last production step.

Claims

CLAIMS:

1. A method for fabrication of semiconductor devices providing a predetermined number of at least one particular function, each constituted by an elementary integrated circuitry, comprising the steps: arranging a plurality of said elementary integrated circuitties on a wafer by a semiconductor process; defining groups with the predetermined number of said elementary integrated circuitries to be incorporated within one of said semiconductor devices; setting up electrical connections between said elementary integrated circuitties within each of said groups by a semiconductor process; and - dicing said wafer into dies, where each die contains one of said groups with said predetermined number of said elementary integrated circuitties.

2. The method according to claim 1, wherein in said arranging step said plurality of elementary integrated circuitries is arranged on said wafer substantially in a matrix- like manner, which matrix comprises columns and rows of said elementary integrated circuitties.

3. The method according to claim 2, wherein in each column of said matrix adjacent elementary integrated circuitties are symmetrical or point-symmettical in circuitry layout.

4. The method according to claim 2 or 3, wherein in each row of said matrix adjacent elementary integrated circuitries are symmettical or point-symmettical in circuitty layout.

5. The method according to claim 2, wherein one of said groups with a predetermined number of said elementary integrated circuitries comprises adjacent elementary integrated circuitries in a row or a column of said matrix on said wafer.

6. The method according to one of the claims 1 to 5, wherein in said step of processing electrical connections at least a common power supply node and a common fixed reference potential node for said elementary integrated circuitties within each of said predetermined groups are provided.

7. A semiconductor device made by the method according to one of the claims 1 to 6, comprising a power supply lead, a reference potential lead, at least one input signal lead and al least one output signal lead, and at least two elementary integrated circuitries (21, 22), each of said elementary integrated circuitries (21, 22) providing a particular function, wherein said elementary integrated circuitties (21, 22) are contained on a single die (50); each of said elementary integrated circuitries (21, 22) is substantially surrounded by a seal ring (34a, 34b), said seal rings (34a, 34b) being electrically connected to each other and to one of said reference potential lead or power supply lead of said semiconductor device, and electrical interconnections (57, 36a, 36b, 59, 49a, 49b) are arranged between said elementary integrated circuitries (21, 22) connecting at least said power supply lead and said reference potential lead of said semiconductor device with each of said integrated circuitries (21, 22).

8. The semiconductor device according to claim 7, wherein each elementary integrated circuitry (21, 22) has a substantially comparable circuitry layout.

9. The semiconductor device according to one of the claims 7 or 8, wherein said particular functions are electtically independent of each other with respect to said input leads and output leads.

10. The semiconductor device according to one of the claims 7 to 9, wherein, as regards said circuitry layout, two particular elementary integrated circuitries (21, 22) arranged adjacent to each other on said die (50) are symmetrical or point-symmettical.

11. The semiconductor device according to one of the claims 7 to 10, wherein said reference potential lead is a ground or earth lead of said semiconductor device (80).

12. The semiconductor device according to one of the claims 7 to 11, wherein each of said elementary integrated circuitties (21, 22) provides a particular function between at least one input lead and one of said output leads of said semiconductor device.

13. The semiconductor device according to one of the claims 7 to 12, wherein said particular function is a Boolean logic function, a buffer circuit, a Schmitt Trigger, a multiplexer, an analog switch, a flip-flop, or other suitable function.

14. The semiconductor device according to one of the claims 7 to 13, wherein the number of said particular elementary functions in said groups is two and the semiconductor device is a dual function device.

15. The semiconductor device according to one of the claims 7 to 13, wherein the number of said particular elementary functions in said groups is three and the semiconductor device is a triple function device.