JPH03209852A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To surely prevent a dielectric breakdown from occurring in an inerlaminar insulting layer which isolates a connection pattern connected to an unused lead (NC lead) from a wiring of different potential by a method wherein a modifying pattern is provided between a bonding pad and a peripheral circuit in a wiring process if necessary. CONSTITUTION:A connection pattern 8 not connected to any of bonding pads 2a and 2d and a circuit element 3 is provided between the pads 2a and 2b and the circuit element 3, and a modifying pattern 12 is provided between the bonding pads 2a and 2b and the connection pattern 8 and the circuit element 3 and the connection pattern 8 respectively in a following wiring process if necessary. A bonding pad 2 is electrically connected to the circuit element 8. By this setup, even if an NC lead is stored with charges, the NC lead is connected to a connection pattern, so that an interlaminar insulating film which isolates the connection pattern from a wiring of different potential can be surely protected against dielectric breakdown.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a manufacturing technology for semiconductor integrated circuit devices, and in particular to a technology that is effective when applied to countermeasures against electrostatic damage in logic LSIs created by a master slicing method. It is something.

[Conventional technology]

A gate array, which is a typical example of a logic LSI manufactured by the master slicing method, usually has bonding pads arranged at the periphery of a semiconductor chip, and peripheral circuits such as input buffer circuits and output buffer circuits arranged inside the bonding pads. Then, by arranging a large number of basic cells in a matrix inside this peripheral circuit and combining these basic cells as appropriate depending on the product type, an inverter, an AND (
NAND) gate, OR (NOR) gate, flip
Create various logic circuits such as flops.

Note that conventional techniques related to the chip layout of gate arrays include, for example, Japanese Patent Application Laid-Open Nos. 58-190036, 62-150884, and 63-53948.
There are publications, etc.

FIG. 6 shows the chip layout near the bonding pads and peripheral circuits at the time when the gate array diffusion process is completed. In the figure, 20 is a peripheral circuit configured by alternately arranging input buffer circuits I and output buffer circuits 0, and 21 is a bonding pad. A connection pattern 22 is provided between each bonding pad 21, 21, . . . and the peripheral circuit 20 to connect them. One end of this connection pattern 22 is connected to the bonding pad 21, but the other end is not yet connected to the peripheral circuit 20.

On the other hand, FIG. 7 shows the chip layout near the bonding pads and peripheral circuits at the time when the wiring process and assembly process (wire bonding process and packaging process) of the gate array are completed. In the figure, 23 is a package, and 24 is a semiconductor substrate (chip).

25.25. . . . are leads constituting external terminals of the gate array, and each lead 25 and bonding pad 2
1 and is electrically connected through a wire 26.

Power supply wiring (Vcc) and GN formed in the wiring process
The D wiring and the connection pattern 22 are separated from each other by an interlayer insulating film (not shown). Note that illustration of signal wiring formed in the wiring process is omitted.

The peripheral circuit 20 and the connection pattern 22 are connected by a modified pattern 27 formed in a wiring process, thereby completing the electrical connection between the predetermined lead 25 and the predetermined peripheral circuit 20. The modification pattern 27 can be modified between the manual buffer circuit I and the connection pattern 22, or between the output buffer circuit O and the connection pattern 22 (or between the input buffer circuit and the output buffer circuit O), depending on the type of gate array. (The figure shows a case where it is provided between the input buffer circuit and the connection pattern 22).

However, depending on the type of gate array, some of the leads may not be used. In such a case, the correction pattern 27 is not provided between the peripheral circuit 20 and the connection pattern 22 connected to an unused lead (for example, the lower lead 25 in the figure).

[Problem to be solved by the invention]

As described above, in a master slice type logic LSI such as a gate array, some leads may not be used depending on the type of LSI (hereinafter, such leads will be referred to as NC leads). However, if charge is accumulated on the NC lead for some reason after the assembly process is completed, the interlayer insulating film that separates the connection pattern connected to the NC lead from wiring of different potential, such as power supply wiring, will be damaged by electrostatic discharge. The inventor has discovered that there is a problem in that this causes a short circuit between the connection pattern and the different potential wiring.

The present invention has been made focusing on the above problems,
The purpose is to develop a technology that can reliably prevent electrostatic discharge damage to the interlayer insulating film that separates the connection pattern connected to the NCIJ-board and the different potential wiring when mounting semiconductor integrated circuits created using the master slicing method. It is about providing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

One invention of the present application provides a connection pattern that is not connected to any of them between a bonding pad and a circuit element, and in the next wiring process, connections between the bonding pad and the connection pattern and between the circuit element and the connection pattern are provided. The bonding pads and circuit elements are electrically connected by providing correction patterns between them as necessary.

Another invention of the present invention is that when manufacturing a master slice type semiconductor integrated circuit device, instead of the above-mentioned means, a correction pattern is provided between the bonding pad and the peripheral circuit in the wiring process as necessary. , electrically connects the bonding pad and peripheral circuitry.

[Effect]

According to the above means, even if charge is accumulated in the NC lead, since the connection pattern is not connected to the NC lead, electrostatic breakdown of the interlayer insulating film separating the connection pattern and the different potential wiring can be prevented. This can be reliably prevented.

[Example 1] FIG. 3 shows a CMO3 (complementary type M
O3) A plan view of the semiconductor substrate 1 at the time when the gate array diffusion process is completed.

On the main surface of the substrate 1, bonding pads 2, 2 . ... are provided, and inside thereof are peripheral circuits 3, 3 constituted by a manual buffer circuit I and an output buffer circuit 0 (not shown in FIG. 3).
．． ...is provided.

The input buffer circuit I and the output buffer circuit ◯ are constituted by a predetermined number of circuit elements, for example CMO3) transistors.

Internal circuit area 4 surrounded by the peripheral circuit 3
includes a large number of basic cell columns 5, 5 extending along the column direction.
．． ...is provided. These basic cell columns 5, 5
．． ... are provided at predetermined intervals along the row direction, and their entire area serves as the wiring channel region 6. Each basic cell column 5 is made up of a large number of basic cells arranged in series along the column direction, and each basic cell is made up of a predetermined number of CMOS transistors and transistors.

FIG. 1 is an enlarged view of the area surrounded by the broken line in FIG. 3. bonding para)'2 (2a.

2b) and the peripheral circuit 3 is provided with a connection pattern 8 that is not connected to any of them. This connection pattern 8 is made of a conductive material such as aluminum.

Next, FIG. 2 is an enlarged view of the region A surrounded by the broken line in FIG. 3 and its vicinity at the time when the wiring process and assembly process (wire bonding process and packaging process) of the CMOS gate array are completed. be.

A predetermined number of leads 10 (10a, 10, Ob) forming external terminals of the CMOS gate array are provided on the side surface of the package 9 in which the substrate (chip) 1 is sealed.

One end of the lead 10 buried inside the package 9 and the bonding pad 2 are electrically connected by a wire 11 formed in a wire bonding process. In addition, the bonding pad 2b and the connection pattern 8
, and the peripheral circuit 3 and the connection pattern 8 are electrically connected by a modified pattern 12 formed in a wiring process. The modified pattern 12 that connects the peripheral circuit 3 and the connection pattern 8 may be between the buffer circuit III and the connection pattern 8, or between the output buffer circuit 0 and the connection pattern 22 (or between the output buffer circuit 0 and the connection pattern 22) depending on the type of gate array. (The figure shows a case where it is provided between the manual buffer circuit ■ and the connection pattern 22.)

In the CMOS gate array of the first embodiment, the lead 10a is not used. That is, the lead 10a is an NC lead that is not connected to the peripheral circuit 3. Therefore, there is a correction pattern 12 between the bonding pad 2a connected to this lead 10a and the connection pattern 8 in the vicinity.
is not provided.

In the wiring process, in addition to the correction pattern 12, signal wiring, power supply wiring [voo], and GND wiring are formed.
AND (NAND) gate, OR (NOR) gate,
Various logic circuits (not shown) such as flip-flops are created. In FIG. 2, among the above-mentioned wirings, the power supply wiring CVCC: ] and the GND wiring are illustrated, and the signal wiring is omitted. The power supply wiring [Vcc] (and the GND wiring) and the connection pattern 8 (and the correction pattern 12) are formed in different wiring layers and are separated from each other by an interlayer insulating film (not shown).

As described above, in the manufacturing process of the CMOS gate array according to the first embodiment, first, in the diffusion process, a connection pattern 8 that is not connected to any of the bonding pads 2 and the peripheral circuit 3 is provided between the bonding pads 2 and the peripheral circuits 3. Then, in the subsequent wiring process, the bonding pad 2 and the connection pattern 8 and the peripheral circuit 3 and the connection pattern 8 are connected by the modified pattern 12, respectively. At that time, NC!
Bonding pad 2 connected to l-)' (10a)
The correction pattern 12 is not provided between a and the connection pattern 8.

As a result, even if charge is accumulated in the NCll-de for some reason after the assembly process is completed, this charge will not be transmitted to the connection pattern 8, so that the interlayer separating the connection pattern 8 and the power supply wiring CVCJ Electrostatic breakdown of the insulating film can be reliably prevented, and a highly reliable CMOS gate array can be obtained.

[Example 2] In the manufacturing process of a CMOS gate array according to Example 2, as shown in FIG. 4, a connection pattern 8 is formed between the bonding pad 2 and the peripheral circuit 3 in the diffusion process
is not provided. Then, as shown in FIG. 5, in the subsequent wiring process, a correction pattern 12 is provided directly between the bonding pad 2 and the peripheral circuit 3. Also, at that time, N
C! The correction pattern 12 is not provided between the bonding pad 2a connected to the J-board (10a) and the peripheral circuit 3.

As a result, even if charge is accumulated in the NCIJ-do for some reason after the assembly process is completed, this charge will not be transmitted to the connection pattern 8, as in the case of the first embodiment, and therefore the modified pattern Electrostatic damage to the interlayer insulating film that separates 12 and the power supply wiring (Vcc:l) can be reliably prevented.

Above, the invention made by the present inventor has been specifically explained based on Example 19, but the present invention is based on Example 1.
It goes without saying that the present invention is not limited to 2 and can be modified in various ways without departing from the gist thereof.

In Embodiment 1.2, the case where it is applied to a CMOS gate array has been described, but the present invention is not limited to this, and can be applied to an ECL (emitter coupled logic) gate array, a B1-CMOS gate array, etc. The present invention can be applied to various semiconductor integrated circuit devices manufactured by the master slicing method.

Further, the present invention can be applied not only to semiconductor integrated circuit devices using a bonding wire method in which leads and bonding pads are connected by wires, but also to semiconductor integrated circuit devices using a flip chip method or a TAB method.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

(1) When manufacturing a master slice type semiconductor integrated circuit device, a connection pattern that is not connected to any of the bonding pads and peripheral circuits is provided in the diffusion process, and the bonding pads are not connected to any of them in the next wiring process. The semiconductor integrated circuit of the present invention electrically connects the bonding pad and the peripheral circuit by providing correction patterns as necessary between the bonding pad and the connection pattern and between the peripheral circuit and the connection pattern, respectively. According to the manufacturing method of the device, the connection pattern is not connected to the NC leads that are not connected to the internal circuit of the chip, so it is necessary to ensure that the interlayer insulating film that separates the connection pattern from the different potential wiring is not damaged by electrostatic discharge. Can be prevented.

(2) When manufacturing a master slice type semiconductor integrated circuit device, by providing a correction pattern as necessary between the bonding pad and the peripheral circuit in the wiring process, the bonding pad and the peripheral circuit can be connected electrically. According to the method for manufacturing a semiconductor integrated circuit device that is connected to
Since the correction pattern is not connected to the NC leads that are not connected to the internal circuit of the chip, the same effect as (1) above can be obtained.

[Brief explanation of drawings]

1 and 2 are enlarged views of main parts of a semiconductor substrate showing the manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 3 is an overall plan view of this semiconductor substrate, and FIG. 5 and 5 are enlarged views of main parts of a semiconductor substrate showing the manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 6 and FIG. 7 are semiconductor integrated circuit devices according to the prior art. FIG. 3 is an enlarged view of a main part of a semiconductor substrate showing the manufacturing process of FIG. 1.24... Semiconductor substrate, 2.21... Bonding pad, 3.20... Peripheral circuit, 4... Internal circuit area, 5... Basic cell row, 6... Wiring channel area , 7... Basic cell, 8°22... Connection pattern, 9
, 23...Package, 10.25 ・ ・ ・
Lead, "11.26...Wire, 12°/correction pattern.

Claims (1)

[Claims] 1. After providing a connection pattern that is not connected to any of the bonding pads provided on the semiconductor substrate and the circuit element, the connection pattern between the bonding pad and the connection pattern and the circuit element is provided. A method of manufacturing a semiconductor integrated circuit device, characterized in that the bonding pad and the circuit element are electrically connected by providing a correction pattern between the element and the connection pattern as necessary. 2. After forming bonding pads, peripheral circuits, and basic cell rows in which a plurality of basic cells are arranged in a matrix on the main surface of the semiconductor substrate in the diffusion process, in the wiring process the basic cells are interconnected according to the product type. A method for manufacturing a semiconductor integrated circuit device using a master slice method in which a desired logic circuit is created by connecting the semiconductor integrated circuit device, the method comprising: providing a correction pattern as necessary between a bonding pad and a peripheral circuit in the wiring process; A method of manufacturing a semiconductor integrated circuit device, comprising electrically connecting the bonding pad and a peripheral circuit.