WO2004061903A3 - Method for fabrication of semiconductor device - Google Patents

Method for fabrication of semiconductor device Download PDF

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Publication number
WO2004061903A3
WO2004061903A3 PCT/US2003/039878 US0339878W WO2004061903A3 WO 2004061903 A3 WO2004061903 A3 WO 2004061903A3 US 0339878 W US0339878 W US 0339878W WO 2004061903 A3 WO2004061903 A3 WO 2004061903A3
Authority
WO
WIPO (PCT)
Prior art keywords
fabrication
area
customization
forming
semiconductor device
Prior art date
Application number
PCT/US2003/039878
Other languages
French (fr)
Other versions
WO2004061903A2 (en
Inventor
Zvi Or-Bach
Laurence Cooke
Adrian Apostol
Romeo Iacobut
Original Assignee
Easic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/321,669 external-priority patent/US6953956B2/en
Application filed by Easic Corp filed Critical Easic Corp
Priority to EP03814808A priority Critical patent/EP1579495A4/en
Priority to AU2003297119A priority patent/AU2003297119A1/en
Priority to JP2005508594A priority patent/JP2006521684A/en
Priority to CA002509673A priority patent/CA2509673A1/en
Publication of WO2004061903A2 publication Critical patent/WO2004061903A2/en
Publication of WO2004061903A3 publication Critical patent/WO2004061903A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os (36) and also including the step of forming redistribution layer (32) for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.
PCT/US2003/039878 2002-12-18 2003-12-16 Method for fabrication of semiconductor device WO2004061903A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP03814808A EP1579495A4 (en) 2002-12-18 2003-12-16 Method for fabrication of semiconductor device
AU2003297119A AU2003297119A1 (en) 2002-12-18 2003-12-16 Method for fabrication of semiconductor device
JP2005508594A JP2006521684A (en) 2002-12-18 2003-12-16 Manufacturing method of semiconductor device
CA002509673A CA2509673A1 (en) 2002-12-18 2003-12-16 Method for fabrication of semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/321,669 2002-12-18
US10/321,669 US6953956B2 (en) 2002-12-18 2002-12-18 Semiconductor device having borderless logic array and flexible I/O
US10/730,064 US7105871B2 (en) 2002-12-18 2003-12-09 Semiconductor device
US10/730,064 2003-12-09

Publications (2)

Publication Number Publication Date
WO2004061903A2 WO2004061903A2 (en) 2004-07-22
WO2004061903A3 true WO2004061903A3 (en) 2005-04-14

Family

ID=32716846

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/039878 WO2004061903A2 (en) 2002-12-18 2003-12-16 Method for fabrication of semiconductor device

Country Status (6)

Country Link
EP (1) EP1579495A4 (en)
JP (1) JP2006521684A (en)
KR (1) KR20050111310A (en)
AU (1) AU2003297119A1 (en)
CA (1) CA2509673A1 (en)
WO (1) WO2004061903A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4937475A (en) * 1988-09-19 1990-06-26 Massachusetts Institute Of Technology Laser programmable integrated circuit
US5994766A (en) * 1998-09-21 1999-11-30 Vlsi Technology, Inc. Flip chip circuit arrangement with redistribution layer that minimizes crosstalk
US6184711B1 (en) * 1998-05-28 2001-02-06 Lsi Logic Corporation Low impact signal buffering in integrated circuits
US6316334B1 (en) * 1999-04-12 2001-11-13 Tanner Research, Inc. Method of fabricating various-sized passivated integrated circuit chips from a borderless gate array

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63261852A (en) * 1987-04-20 1988-10-28 Nippon Denso Co Ltd Semiconductor integrated circuit
JPH01244642A (en) * 1988-03-25 1989-09-29 Matsushita Electron Corp Semiconductor integrated circuit device
JPH0287550A (en) * 1988-09-22 1990-03-28 Nec Corp Master slice type semiconductor integrated circuit
US5217916A (en) * 1989-10-03 1993-06-08 Trw Inc. Method of making an adaptive configurable gate array
JPH03201561A (en) * 1989-12-21 1991-09-03 Lsi Logic Corp Manufacture of ic and wafer for ic manufacture
JPH0563165A (en) * 1991-06-25 1993-03-12 Kawasaki Steel Corp Semiconductor device
JPH053285A (en) * 1991-06-25 1993-01-08 Kawasaki Steel Corp Semiconductor device
JPH05102322A (en) * 1991-10-11 1993-04-23 Miyagi Oki Denki Kk Manufacture of semiconductor device
US6242943B1 (en) * 1998-12-31 2001-06-05 Khaled Ahmad El-Ayat Programmable multi-standard I/O architecture for FPGAS
JP2000269339A (en) * 1999-03-16 2000-09-29 Toshiba Corp Semiconductor integrated circuit device and method for wiring layout
US6271679B1 (en) * 1999-03-24 2001-08-07 Altera Corporation I/O cell configuration for multiple I/O standards

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4937475A (en) * 1988-09-19 1990-06-26 Massachusetts Institute Of Technology Laser programmable integrated circuit
US4937475B1 (en) * 1988-09-19 1994-03-29 Massachusetts Inst Technology Laser programmable integrated circuit
US6184711B1 (en) * 1998-05-28 2001-02-06 Lsi Logic Corporation Low impact signal buffering in integrated circuits
US5994766A (en) * 1998-09-21 1999-11-30 Vlsi Technology, Inc. Flip chip circuit arrangement with redistribution layer that minimizes crosstalk
US6316334B1 (en) * 1999-04-12 2001-11-13 Tanner Research, Inc. Method of fabricating various-sized passivated integrated circuit chips from a borderless gate array

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1579495A4 *

Also Published As

Publication number Publication date
EP1579495A4 (en) 2008-12-10
KR20050111310A (en) 2005-11-24
AU2003297119A1 (en) 2004-07-29
JP2006521684A (en) 2006-09-21
AU2003297119A8 (en) 2004-07-29
CA2509673A1 (en) 2004-07-22
EP1579495A2 (en) 2005-09-28
WO2004061903A2 (en) 2004-07-22

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