JPH03201561A - Manufacture of ic and wafer for ic manufacture - Google Patents

Abstract

PURPOSE: To eliminate inefficiency incident to matching the design and a master splice of the chip size and to avoid cost increase by providing a metallized layer such that an integrated circuit can be formed by interconnecting circuit component building blocks. CONSTITUTION: An I/O structure 103 and bonding pads 104 are arranged in chips 107, 108. Building blocks are formed such that a core transistor 101 and the I/O structure 103 are integrated and the components of an integrated circuit can be implemented. At the time of solder bump bonding, a metal trace is applied onto an insulating substrate onto which a chip must be fixed at first. Solder bumps are arranged at positions on a chip where bonding pads are expected. The chips are arranged upside down and held at a predetermined position while aligning the bonding pads with the solder bumps. Subsequently, it is placed in a reflow furnace under that state and heated up to a temperature higher than the melting point of solder material thus accomplishing the bonding.

Description

[Detailed description of the invention] [Object of the invention] <Industrial application field>
The present invention relates to the design and fabrication of mask slices for integrated circuits used in channelless arrays with gale) and similar techniques.

Prior Art In the prior art, each mask slice wafer could only be used to build chips of one size and one input/output (1/0) configuration. Depending on the intended application, different chip sizes are required since different chips have different chip complexity. Additionally, the desired logic gate to I/O structure ratios often vary widely depending on the intended application as well. As a result, the core millimeter of the mask slice is required to satisfy such varying conditions. (
For example, at LSI Logic Inc., 10K
Various CMOS from 100K transistors to
MOS Coapacte
dArray(R) provides core millimeters of mask slices. ) In a conventional mask slicing design, a wafer is divided into an array of equally sized chips separated by unused areas called scribe lines. Each chip has a core of transistors surrounded by an outer ring of I/O cells with bonding pads. These elements form building blocks from which the circuit components that make up the integrated circuit are constructed.

The I/O cells are custom designed with transistors optimized for current drive, power speed, and area issues. The I/O cells provide an interface to the outside of the integrated circuit. The transistors in the core are the smallest sized transistors from which logic gates, storage elements and other circuit components are constructed. Logic gates of different sizes are obtained by interconnecting these transistors.

The construction and interconnection of these circuit components is performed at a relatively late stage in the chip manufacturing process. This process, referred to as metallization, involves defining and placing regions of interconnect material, usually metal such as aluminum, on the wafer surface.

This technology focuses on the area of interconnectivity (routing
The wiring material is routed to overlie the unused transistors since the channels ("channels") are not pre-planned. In this way, wasted silicon "real estate" or area due to unused reserved routing channels is minimized.

SUMMARY OF THE INVENTION However, inventory and other costs severely limit the number of mask slices that can be used to meet particular design requirements.

All a designer can do is roughly match the chip size and I10 requirements that he or she needs. If the application is gate-limited or gate-based, that is, by selecting the mask slice that most closely approximates the number of core transistors and therefore logic gates required for its implementation, the designer may be forced to choose a mask slice with a large number of I10 structures that remain unused. In other cases, the application may be "pad-11mlLe
d) or pad referenced, i.e. by choosing the mask slice closest to the number of I10 structures required for the application, many core transistors are left unused. In the prior art, "pad-only" or "gate-only" applications made implementation inefficient. The degree of nonconformity determines the degree of inefficiency in manufacturing.

Because the wafer is divided into arrays of equally sized chips, it is not possible in the prior art to build prototypes consisting of chips of different sizes on the same wafer. Because of this, the costs of prototyping, which is essentially an engineering activity, are correspondingly high.

SUMMARY OF THE INVENTION It is therefore a first object of the present invention to adapt the design to a mask slice of a given chip size by providing a mask slice that allows the size of the chip to be determined during the metallization process. The aim is to eliminate the associated inefficiencies and avoid their costs.

A second object of the invention is to provide a mask slice that is flexible in logic gate to I10 structure ratio so that inefficiencies due to the necessity of adapting a design to a mask slice consisting of a predetermined number of I10 structures are eliminated. There is a particular thing.

A third object of the present invention is to have an I10 structure divided into clusters arranged regularly across the wafer so that groups of input and output signals requiring substantially the same skew can be easily accommodated. The purpose is to provide mask slices.

A fourth object of the present invention is to provide a mask slice that can have chips of various sizes on the same wafer 1. This reduces prototyping costs because various designs can be placed on the same wafer and manufactured in the same manufacturing process.

Furthermore, a fifth object of the present invention is that other objects and advantages of various core transistor vs. If any, it can be easily understood from the detailed explanation given below.

SUMMARY OF THE INVENTION A mask slice is provided in which a wafer is filled with a regular array of core transistors. This mask slice is initially not divided into chips. Dividing into chips is done during the metallization process during manufacturing. In a preferred embodiment, custom designed I10 structures and bonding pads are regularly placed on the wafer. In another preferred embodiment, the I10 structure is formed from core transistors and bonding pads cover unused core transistors. In a third preferred embodiment, custom designed I10 structures are arranged in regularly spaced clusters across the wafer. In a fourth preferred embodiment, the placement of the custom-designed I10 structures on the wafer is atypical, such that chips of various process conditions are built on the same wafer.

<Operation> According to the present invention, the waste of transistors, especially in pad-limited applications, and the waste of the I10 structure, particularly in gate-limited applications, are eliminated. According to the present invention, chips of different sizes can be present on the same wafer, providing an economical means for performing prototyping operations.

<Example> In the present invention, mask slices are not divided into chips.

The unprocessed mask-sliced wafer is a -like regular array of core transistors. Dividing the wafer into chips is performed in a metallization process simultaneously with the interconnection and configuration of logic gates, memory components, and other circuit components. The division of the chip is defined by scribe lines consisting of metallization layers deposited during the metallization process. Since the size of the chips is not predetermined as in the prior art, it is no longer possible to build a ring-shaped 110 structure and bonding pads surrounding the core transistors in each chip. Instead, I10 structures and bonding pads are placed within the chip. Together, the core transistor and I10 structure form a building block upon which the implementation of the circuit components of an integrated circuit can be made. These I1
Computer-aided design tools for automatically routing circuit outputs to zero structures and bond pads will require changes to optimize use of this new configuration.

A first preferred embodiment is shown in FIG. In this embodiment, wafer 100 first includes core transistor 1.
It is covered with a regular array consisting of 01. Within the regular array of core transistors 101 are I10 cells 10
3 regular arrays are distributed. These I10 cells 1
03 is custom designed and optimized to meet external timing, drive/sink or electrostatic discharge requirements.

In this first preferred embodiment, a logic cell is formed from a core transistor 101. A scribe line 105 is selected at design time to carry out the intended use and provide the required 11
0 functionality, encompassing the minimum area delineated by chip border 106 necessary to provide 0 functionality. Chips 107, 108 are shown in FIG. 1, illustrating the flexibility of the method to provide different sizes of chips and I10 structures on this same wafer. Chip 107 is shown with six I10 structures and chip 108 is shown with four I10 structures.

Although shown individually in a regular array in FIG. 1, in some applications I10 cells are arranged in clusters, each of which is an element of a regular array of I10 cell clusters. It is desirable to do so. This is illustrated in FIG. 3 and will be discussed below in connection with the third preferred embodiment.

The distributed bond pad configuration makes it impractical to use individual bond wires to connect to external package bins. Instead, another assembly utilizing solder bump or tape automated bonding (TAB) techniques should be used. Since these techniques are well known in the art, they will be briefly described below.

In solder bump bonding, metal traces are first deposited on an insulating substrate to which the chip is to be attached. A blob of solder material, or solder bump, is placed on the chip at the location where bonding pads are expected. The chip is placed upside down and maintained in place with the bonding pads aligned with the solder bumps. Next, in this state, it is placed in a reflow oven and heated to a temperature equal to or higher than the melting point of the solder material to achieve the bonding.

In TAB technology, the traces connecting the wires are made of Mylar® or Kapton.
pton) films (Kapton is a trade name for polyimide films manufactured by DuPont Corp.), whereas the rest of the film Forms a flexible support for the wire. A copper layer is then plated over the wire portions of the traces on the film to provide electrical conductivity. Furthermore, since copper has relatively poor bonding properties, a gold layer is used to plate the copper wire. The chips are then secured to the wire traces on the film using solder bumps or other techniques.

Since the I10 cell is custom designed, this embodiment has the advantage of an optimized I10 structure. On the other hand, the problem of adapting pad-only or gate-only applications is not completely resolved since the I10 structure to core transistor ratio is predetermined. Nevertheless, since the size of the chip is no longer constant, each core transistor pair 11
With only 2.3 mask slices with 0 structure ratio, the problem of pad-only or gate-only suitability is substantially solved.

Therefore, by achieving the objective of providing chips of various sizes on the same wafer, prototyping costs are substantially reduced.

For applications such as memory arrays, where large, highly regular, preferably closely spaced structures are required, the presence of regularly spaced I10 structures is not desirable and the size of each structure in close proximity It is restrictive. This problem is solved by the second preferred embodiment shown in FIG.

In a second preferred embodiment, shown in FIG.
is entirely covered by a regular array of core◆transistors 204. Unlike the first preferred embodiment, the wafer is not provided with I10 cells and bonding pads at predetermined locations. Instead, the I10 cell 202 is the core transistor 204
Logic cells 203 are formed from core transistors 204 in a similar manner by interconnecting them.

A bonding pad 201 is placed near the I10 cell 202 as a metallization layer covering unused core transistors.

Scribe lines and chip boundaries are formed in a manner similar to the first preferred embodiment described above.

In this second embodiment, since the I10 cell 202 and bonding pad 201 are formed from the core transistor, they can actually be formed anywhere on the chip within the chip boundaries. In particular, the I1
0 cells and bonding pads can be placed once again around the periphery of the chip to allow conventional wire bonding. Alternatively, one may choose to use an arranged I10 structure as described with respect to the first preferred embodiment. This latter method requires sophisticated bonding techniques such as those exemplified in the above description.

Since the I10 cell in the second preferred embodiment is formed from the core transistor, optimizations in custom designed I10 cells such as clamping diodes are not readily available in this embodiment. . Even so, since the I10 cells represent a relatively small portion of the total chip area, the area penalty incurred in our approach as a result of large I10 cells is
This does not have a significant impact, especially considering that the issue of suitability for gate-only and pad-only applications is completely eliminated. A generally optimal use of silicon real estate is achieved. Additionally, the convenient location of the I10 cells and bonding pads facilitates accommodating large regular structures in close proximity, such as memory arrays.

FIG. 3 shows a third preferred embodiment. A mask sliced wafer 300 has an I10 structure consisting of custom designed I10 cells 303 and I10 pads 304 divided into clusters 302 regularly spaced throughout the wafer. Clustering is desirable when a group of input and output signals need to have approximately the same skew in time. Examples of such signals are data or address buses.

As in the case of the first embodiment, the chip is connected to the scribe line 30.
6 and surrounds the integrated circuit within a chip boundary 305. Similar to the first preferred embodiment, bonding to the I10 pad may be accomplished using solder bumps or T-pads as described above.
Advanced bonding technology such as AB is required. Since the I10 structures are clustered, in order to meet the predetermined core transistor to I10 structure ratio conditions, the clusters must be moved closer together as individual I10 structures as in the first preferred embodiment. There is no need to place it. This also aids in the application of large scale close circuit components such as memory arrays.

A fourth preferred embodiment is shown in FIG. 4, in which a mask-sliced wafer 400 has custom-designed I10 structures formed by I10 cells 401 and bonding pads 402 uniformly across the wafer. They are arranged in a scattered manner rather than in a uniform manner. This is illustrated in FIG. 4, where the distance between adjacent I10 structures is 1!1i4
03.403- is not the same at two different locations on the wafer. With this arrangement, the chip boundary 4
The chips enclosed within 04.404' can be fabricated on the same wafer 400 and have different I10 structure to core transistor ratios.

Such an arrangement provides another means of reducing prototyping costs. In this variant of the fourth preferred embodiment, the crusted I10 structures are non-uniformly distributed. The benefits of adapting timing skew and varying chip size are achieved simultaneously.

It should be noted that the preferred embodiments described above are merely illustrative of the present invention,
This is not intended to limit the technical scope of the invention. Further, as will be apparent to those skilled in the art, the present invention can be implemented by adding various modifications and changes to the above-described embodiments within the technical scope thereof.

EFFECTS OF THE INVENTION Thus, according to the present invention, any of the four preferred embodiments described above can be used to determine what to fabricate on a single wafer for array-based technologies. This provides almost complete flexibility.

Prototyping costs are minimized because several unequal sized chips are prototyped on the same wafer. In the first embodiment or the third embodiment, the maximum
Inventory costs are minimized because 1 mask slices (varying the I10 cell-to-core transistor ratio) are required, and in the second or fourth embodiments, only one mask slice is required. . Required logic, memory,
The ability to use the same core building block transistors for Ilo or other components allows near-optimal utilization of silicon value.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention. FIG. 2 is a plan view showing a second embodiment of the invention. FIG. 3 is a plan view showing a third embodiment of the present invention. FIG. 4 is a plan view showing a fourth embodiment of the present invention. DESCRIPTION OF SYMBOLS 100... Wafer, 101... Core transistor, 103... I10 cell, 104... Bonding pad, 105... Scribe line, 106... Chip boundary, 107.108... Chip, 200... Wafer, 201... Bonding pad, 202-...
I10 cell, 203...Logic cell, 204...Core transistor, 300...Wafer, 302...Cluster, 303...I10 cell, 304...I10
Pad, 305... Chip boundary, 306... Scribe line, 400... Wafer, 401... I10 cell, 402... Bonding pad, 403.403'
...Distance, 404.404-...Chip boundary IG, j FIG, 2 FIG, 4

Claims (14)

[Claims] (1) A method for manufacturing an integrated circuit comprising: providing a semiconductor wafer with building blocks of circuit components assembled in an array; the building blocks of circuit components are connected together to form a larger circuit component, and the building blocks of circuit components are connected to each other to form the integrated circuit. A method for manufacturing an integrated circuit, comprising the step of providing a metallization layer. 2. A method according to claim 1, wherein said building blocks of circuit components consist of transistors, predetermined input/output cells and bonding pads. (3) the building blocks of the circuit component consist of transistors, and the step of providing a metallization layer further includes forming input/output cells from the transistors and forming metallized regions that can be used as bonding pads; 2. The integrated circuit manufacturing method according to claim 1, further comprising the steps of: (4) The integrated circuit manufacturing method according to claim 2, wherein the input/output cells and the bonding pads are arranged in a regular array. (5) The input/output cell and the bonding pad are
3. The method of manufacturing an integrated circuit according to claim 2, wherein the integrated circuit is divided into clusters arranged over the entire wafer. (6) The input/output cell and the bonding pad are
3. The integrated circuit manufacturing method according to claim 2, wherein the semiconductor wafer is not uniformly disposed on the semiconductor wafer. (7) The integrated circuit manufacturing method according to claim 6, wherein the input/output cells and the bonding pads are divided into clusters. (8) A semiconductor wafer for manufacturing integrated circuits, comprising an array of building block circuit components and metallization interconnecting the building block circuit components to form integrated circuits, each of a different size. A semiconductor wafer for manufacturing integrated circuits, characterized by comprising layers. 9. The semiconductor wafer of claim 8, wherein said building block circuit components consist of transistors, predetermined input/output cells, and bonding pads. 10. A semiconductor wafer for manufacturing integrated circuits as claimed in claim 8, wherein said building block circuit components consist of transistors forming I/O cells. 11. The semiconductor wafer of claim 9, wherein said array of building block circuit components is a regular array. (12) A ninth aspect characterized in that the predetermined I/O cell and the bonding pad are divided into clusters.
A semiconductor wafer for manufacturing integrated circuits according to the claims. (13) The semiconductor wafer for manufacturing integrated circuits according to claim 9, wherein the predetermined input/output cells and the bonding pads are not uniformly arranged on the semiconductor wafer. (14) A first method characterized in that the predetermined input/output cells and the bonding pads are divided into clusters.
A semiconductor wafer for manufacturing integrated circuits according to claim 3.