WO2004056162A8 - フリップチップ実装用電子部品及びその製造法、回路板及びその製造法、実装体の製造法 - Google Patents
フリップチップ実装用電子部品及びその製造法、回路板及びその製造法、実装体の製造法Info
- Publication number
- WO2004056162A8 WO2004056162A8 PCT/JP2002/013203 JP0213203W WO2004056162A8 WO 2004056162 A8 WO2004056162 A8 WO 2004056162A8 JP 0213203 W JP0213203 W JP 0213203W WO 2004056162 A8 WO2004056162 A8 WO 2004056162A8
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- producing
- same
- flip
- chip mounting
- electronic component
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/003—Apparatus or processes specially adapted for manufacturing resistors using lithography, e.g. photolithography
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C1/00—Details
- H01C1/16—Resistor networks not otherwise provided for
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/28—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/0542—Continuous temporary metal layer over metal pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002357592A AU2002357592A1 (en) | 2002-12-18 | 2002-12-18 | Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package |
JP2004560580A JPWO2004056162A1 (ja) | 2002-12-18 | 2002-12-18 | フリップチップ実装用電子部品及びその製造法、回路板及びその製造法、実装体の製造法 |
US10/538,584 US20060286716A1 (en) | 2002-12-18 | 2002-12-18 | Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package |
PCT/JP2002/013203 WO2004056162A1 (ja) | 2002-12-18 | 2002-12-18 | フリップチップ実装用電子部品及びその製造法、回路板及びその製造法、実装体の製造法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2002/013203 WO2004056162A1 (ja) | 2002-12-18 | 2002-12-18 | フリップチップ実装用電子部品及びその製造法、回路板及びその製造法、実装体の製造法 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004056162A1 WO2004056162A1 (ja) | 2004-07-01 |
WO2004056162A8 true WO2004056162A8 (ja) | 2005-06-23 |
Family
ID=32587961
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2002/013203 WO2004056162A1 (ja) | 2002-12-18 | 2002-12-18 | フリップチップ実装用電子部品及びその製造法、回路板及びその製造法、実装体の製造法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20060286716A1 (ja) |
JP (1) | JPWO2004056162A1 (ja) |
AU (1) | AU2002357592A1 (ja) |
WO (1) | WO2004056162A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070138628A1 (en) * | 2005-12-15 | 2007-06-21 | Lam Ken M | Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package |
US8258599B2 (en) * | 2005-12-15 | 2012-09-04 | Atmel Corporation | Electronics package with an integrated circuit device having post wafer fabrication integrated passive components |
US7932590B2 (en) * | 2006-07-13 | 2011-04-26 | Atmel Corporation | Stacked-die electronics package with planar and three-dimensional inductor elements |
KR100984132B1 (ko) * | 2007-11-12 | 2010-09-28 | 삼성에스디아이 주식회사 | 반도체 패키지 및 그 실장방법 |
CN102057763B (zh) * | 2008-06-10 | 2016-01-20 | 皇家飞利浦电子股份有限公司 | 电子纺织品、制造其的方法以及用于其的纱线 |
KR101007932B1 (ko) * | 2008-07-25 | 2011-01-14 | 세크론 주식회사 | 패턴 위치 결정 방법, 캐비티 위치 결정 방법 및 솔더 범프형성 방법 |
JP2010141055A (ja) * | 2008-12-10 | 2010-06-24 | Sanyo Electric Co Ltd | 半導体モジュール、半導体モジュールの製造方法および携帯機器 |
JP6668656B2 (ja) * | 2015-09-28 | 2020-03-18 | 日亜化学工業株式会社 | パッケージ、発光装置、発光モジュール、及び、パッケージの製造方法 |
US10083781B2 (en) | 2015-10-30 | 2018-09-25 | Vishay Dale Electronics, Llc | Surface mount resistors and methods of manufacturing same |
US10438729B2 (en) | 2017-11-10 | 2019-10-08 | Vishay Dale Electronics, Llc | Resistor with upper surface heat dissipation |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4940181A (en) * | 1989-04-06 | 1990-07-10 | Motorola, Inc. | Pad grid array for receiving a solder bumped chip carrier |
JP3258764B2 (ja) * | 1993-06-01 | 2002-02-18 | 三菱電機株式会社 | 樹脂封止型半導体装置の製造方法ならびに外部引出用電極およびその製造方法 |
JP2000077218A (ja) * | 1998-09-01 | 2000-03-14 | Matsushita Electric Ind Co Ltd | チップ形抵抗ネットワーク |
US6406991B2 (en) * | 1999-12-27 | 2002-06-18 | Hoya Corporation | Method of manufacturing a contact element and a multi-layered wiring substrate, and wafer batch contact board |
JP2001332582A (ja) * | 2000-05-19 | 2001-11-30 | Sony Corp | 半導体装置及びその製造方法 |
JP3870013B2 (ja) * | 2000-07-17 | 2007-01-17 | 日本アビオニクス株式会社 | ウェハレベルcspの端子形成方法 |
JP2002190549A (ja) * | 2000-10-03 | 2002-07-05 | Sumitomo Bakelite Co Ltd | 多層配線板および多層配線板の製造方法 |
JP2002261407A (ja) * | 2001-03-05 | 2002-09-13 | Matsushita Electric Ind Co Ltd | プリント配線板とその製造方法および電子部品の実装方法 |
JP2002313996A (ja) * | 2001-04-18 | 2002-10-25 | Toshiba Chem Corp | 半導体パッケージ用基板およびその製造方法 |
-
2002
- 2002-12-18 AU AU2002357592A patent/AU2002357592A1/en not_active Abandoned
- 2002-12-18 JP JP2004560580A patent/JPWO2004056162A1/ja active Pending
- 2002-12-18 US US10/538,584 patent/US20060286716A1/en not_active Abandoned
- 2002-12-18 WO PCT/JP2002/013203 patent/WO2004056162A1/ja active Application Filing
Also Published As
Publication number | Publication date |
---|---|
AU2002357592A1 (en) | 2004-07-09 |
WO2004056162A1 (ja) | 2004-07-01 |
US20060286716A1 (en) | 2006-12-21 |
JPWO2004056162A1 (ja) | 2006-04-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8115104B2 (en) | Circuit board with buried conductive trace formed thereon and method for manufacturing the same | |
US6864586B2 (en) | Padless high density circuit board | |
EP1915040A3 (en) | Printed wiring board and printed wiring board manufacturing method | |
EP1032041A3 (en) | Semiconductor device comprising an internal wiring pattern | |
US7141879B2 (en) | Semiconductor device | |
EP1895586A3 (en) | Semiconductor package substrate | |
EP1005082A4 (en) | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, PRINTED CIRCUIT BOARD, AND ELECTRONIC APPARATUS | |
SG133406A1 (en) | Substrates including innovative solder ball pad structure | |
EP0913866A4 (en) | ELECTRONIC COMPONENT AND SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, PRINTED CIRCUIT BOARD THUS EQUIPPED, AND ELECTRONIC EQUIPMENT COMPRISING SUCH A PRINTED CIRCUIT BOARD | |
SG81960A1 (en) | Semiconductor device, substrate for a semiconductor device, method of manufacture thereof, and electronic instrument | |
WO2003017324A3 (en) | Structure and method for fabrication of a leadless chip carrier with embedded inductor | |
MXPA05010527A (es) | Metodo para la elaboracion de un modulo electronico y un modulo electronico. | |
EP0917195A4 (en) | ELECTRONIC COMPONENT, SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, PRINTED BOARD, AND ELECTRONIC EQUIPMENT | |
EP1198003A4 (en) | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, CIRCUIT BOARD, AND ELECTRONIC DEVICE | |
GB2441265A (en) | Method for manufacturing a circuit board structure, and a circuit board structure | |
WO2003021672A3 (en) | An electronic package having a thermal stretching layer | |
TW200610204A (en) | Semiconductor device and manufacturing method thereof | |
WO2001080303A3 (en) | Method and apparatus for manufacturing an interconnect structure | |
TW200605279A (en) | Semiconductor device and manufacturing method thereof | |
US5525204A (en) | Method for fabricating a printed circuit for DCA semiconductor chips | |
WO2003103042A3 (de) | Elektronisches bauteil mit äusseren flächenkontakten und verfahren zu seiner herstellung | |
EP0818822A3 (en) | Package structure for multichip modules | |
WO2004056162A8 (ja) | フリップチップ実装用電子部品及びその製造法、回路板及びその製造法、実装体の製造法 | |
TW365035B (en) | Semiconductor device package having a board, manufacturing method thereof and stack package using the same | |
EP1394856A3 (en) | Surface-mounted electronic component module and method for manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SK SL TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2004560580 Country of ref document: JP |
|
CFP | Corrected version of a pamphlet front page | ||
CR1 | Correction of entry in section i |
Free format text: IN PCT GAZETTE 27/2004 ADD "DECLARATION OF INVENTORSHIP TOR THE PURPOSES OF THE DESIGNATION OF US ONLY (RULE 4.17(IV))." |
|
122 | Ep: pct application non-entry in european phase | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2006286716 Country of ref document: US Ref document number: 10538584 Country of ref document: US |
|
WWP | Wipo information: published in national office |
Ref document number: 10538584 Country of ref document: US |