WO2004054332A2

WO2004054332A2 - Strip-line topology for a high speed pcb with low dissipation

Info

Publication number: WO2004054332A2
Application number: PCT/RU2003/000529
Authority: WO
Inventors: Igor Anatolievich Abrosimov
Original assignee: Igor Anatolievich Abrosimov
Priority date: 2002-12-06
Filing date: 2003-11-27
Publication date: 2004-06-24
Also published as: AU2003287116A1; WO2004054332A3; AU2003287116A8

Abstract

A multilayer printed circuit board is provided, comprising a plurality of planar layers made of dielectric material, and a plurality of conductor traces secured with their rough surfaces to these dielectric material layers, their smooth surfaces looking outwards or facing each other in superposed laminar relation to form a coplanar structure, so that the skin effect losses in the circuit structure are reduced. The traces can be driven in parallel to form a single conductor line.

Description

HIGH SPEED LOW DISSIPATION PCB TOPOLOGIES

BACKGROUND OF THE INVENTION Technical Field

The present invention relates to methods of transmitting electrical signals through Printed Circuit Board (PCB) with minimized signal losses. More particularly, the present invention concerns topology of PCB strip-lines or micro- strips to achieve maximum benefit from conductor surface treatment to minimize skin effect losses.

Background of the Invention

Data rate of signals transmitted over PCB in electronic equipment, such as computers, network switches and routers, servers or supercomputers is reaching level at which dissipation in the PCBs could be as big as 10 times over single transmission line. This limits data rate and/or distance of the channel.

There are two major components which causing losses. They are dielectric losses in the insulator and losses caused by limited conductivity of the metal used to transmit signals. At frequencies above 1GHz and distances up to 80" both components are in same order of magnitude. An extensive work is carried out to make insulators with lower dielectric losses for such high speed interconnect systems. In particular, very good results are achieved with PTFE based (Teflon) materials which reduces dielectric losses and makes skin effect losses dominating.

Moreover, skin effect losses are amplified when conductor surface roughness, i.e. average variations in the metal surface height, exceeds the depth of the skin layer. This effect causes losses to be growing much faster with higher frequencies than it will be with flat surface.

One of the known approaches to reduce this effect is additional surface treatment to reduce roughness from typical 15μm down to 5μm and less. For example, US 5,215,645 describes a process for preparing a low profile copper foil for printed circuit boards by using a special electrodeposition bath solution comprising a surface roughness decreasing agent. However, such surface treatment is suitable for outer conductor sides and is in contradiction to mechanical requirements for adhesive side because copper is fixed on the core due to adhesion and flat surface degrades mechanical strength of this contact dramatically. Thus roughness on adhesive side of the copper shall exceed certain level because the certain controlled degree of roughness is desired by the copper foil user so that the bond strength is increased between the copper foil and the dielectric support to which the copper foil is adhered, and the copper foil. Roughness contributes to the strength of the bond by increasing the surface area available for bonding. If surface treatment is provided for outer sides only, then effect from this treatment is almost halved due to much less conductivity on high frequency of the layer closed to the PCB core.

Other known approach to solve this problem is to provide extra process steps where core is additionally flattened and then metal of the conductor is built having bottom layer also flat. However, this method might not be suitable for low cost applications due to more complicated processing involved. A double treated copper foil is mentioned also in "Surface Roughness" by Howard Johnson, in Electronic Design News, pages 30-32, December 6, 2001.

A process of preparing a PCB's package having good electrical characteristics at frequencies in excess of 1 GHz is disclosed in US 5,268,064. To counteract skin effect losses, the process avoids oxidising step so that the PCB package obtained comprises a double sided double treated copper clad laminate used as an inner layer in which propagation speeds are not worsened by oxide. However, the known method of preparing PCB package requires some additional steps that makes the process more complex.

Other multilayer PCB packages are known comprising single and double sided copper clad laminates that have only single treated copper foil. However, typically, they have significantly lower characteristics. BRIEF SUMMARY OF THE INVENTION

It is an object of the present invention to reduce signal losses in PCB by improved PCB traces and stack topologies, such that electrical losses from skin effect becomes less using conventional materials and single side surface treated conductors.

Cross section of one PCB core with metal traces attached to this core is shown in Fig. 4. Metal is attached to the core using adhesion of both core surface and metal surface. To make this contact strong enough, both surfaces shall be rough up to tens of microns. However, the outer surface can be passed through additional surface treatment, such as silver coating and/or roughness treatment. If a relative area occupied by signal traces is small, then this additional roughness treatment will not affect assembled PCB strength due to sufficient area for adhesive contact between prepreg and core material directly.

The key idea is to determine a topology of the metals, core and prepreg as used in general PCB process with electromagnetic field existing mostly between surfaces of the metal conductors faced to the prepreg, and thus suitable for extra treatment, and minimize the amount of this field between surfaces faced to the core. Thus, the signal current will be concentrated mostly at the metal surface suitable for extra treatment, such as silver plating and/or roughness treatment, minimizing losses from skin effect, in the absence of electromagnetic filed and, hence, losses from roughly shaped edge between the core and metal suitable for usual adhesive connection. Additional benefit from this technique is that PCB's made of mixed materials can be used where prepreg is low losses material, such as PTFE based, while core is usual low cost material such as FR4. Dielectric losses will be also lowered because electromagnetic energy is transferred mostly through the prepreg material, the core being used for mechanical purposes only, to provide a sufficient strength and good adhesive surface for both metal and prepreg.

Thus, in one aspect of the invention, a multilayer printed circuit board is provided, comprising a plurality of planar layers made of dielectric material, and a plurality of conductor lines secured to these dielectric material layers, wherein each conductor line is formed by a first and a second conductive traces driven in parallel, the traces being made of electrically conductive material secured to the dielectric with their rough surfaces, their smooth surfaces looking outwards in superposed laminar relation to form a coplanar structure, so that the skin effect losses in the circuit structure are reduced. Conductive traces can be formed from an etched copper metallization layer.

The surface of the core layer can be coated with suδ or another polyimide to produce a very flat surface, such as flat to within 15nm over short distances. According to example implementation shown in Fig. 5a, both first and second conductive traces are secured with their rough surfaces to a single dielectric layer in an over/under orientation. Another option is that the first and second conductive traces are secured with their rough surfaces to different dielectric layers in an over/under orientation, so that their smooth surfaces are facing each other.

Preferably, said first and second conductive traces are of equal width and overlap each other in an over/under orientation.

In another example implementation shown in Fig.δg., a conductive trace faces with its smooth surface a ground plane.

In still another example embodiment, the first and the second conductor lines form a differential pair in a side-by-side orientation, each conductor line being formed of two conductive traces in an over/under orientation, each conductor line being formed of a single conductive trace secured with its rough surface to the inner surface of the dielectric layer, facing with their smooth surfaces each other or a ground layer in an over/under orientation.

Both said first and second conductive traces can be secured to a single dielectric layer in a side-by-side orientation, or to different dielectric layers in an over/under orientation. Preferably, said first and second conductive traces are of equal width and overlap each other in an over/under orientation.

The multilayer printed circuit board can further include a differential generating circuit electrically coupled to said first and second conductor lines for generating and supplying thereto a pair of complementary current or voltage varying signals. In another aspect of the invention, a method of reducing skin effect losses within a multilayer circuit structure is provided, comprising the steps of: applying a first signal to a first conductive trace; and applying a second signal to a second conductive trace adjacent the first conductive trace and separated by at least one dielectric layer, wherein the first and the second conductive traces are secured with their rough surfaces to dielectric layer or layers, their smooth surfaces disposed in superposed laminar relation in an over-under orientation in a vertical plane to form a coplanar structure, so that their smooth surfaces look outwards or face each other.

Alternatively, the conductive traces can be secured with their rough surfaces to a single dielectric layer, their smooth surfaces facing a ground layer. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

These and another aspects of the present invention will now be described in detail with reference to example embodiments of the invention and accompanying drawings which, however, should not be taken to limit the invention to the specific embodiments described, but are for explanation and understanding only.

Fig. 1 shows an example of a conventional approach to implement 50 Ohm (100 Ohm differential impedance) differential pair in PCB with improved dielectric, silver coating and single side roughness treatment.

Fig. 2 shows an example of improved implementation of 50 Ohm (100 Ohm differential impedance) differential pair according to the present invention using the same materials, process and space as shown in Fig. 1.

Fig. 3 shows an amplitude-frequency response of 80" transmission lines having conventional (1) and improved PCB topology (2) built as shown on Fig. 1 and Fig. 2 respectively. Fig. 4 shows cross section of one PCB core with metal conductors on both sides in detail.

Fig. 5 shows different PCB topologies according to the present invention. A) Single Ended micro-strip with roughness treatment for signal traces and ground plane. B) Differential micro-strip pair with roughness treatment for signal traces and ground plane.

C) Single Ended strip-line with roughness treatment for signal traces and ground planes.

D) Differential strip-line pair with roughness treatment for signal traces and ground planes.

E) Differential coplanar pair with roughness treatment for signal traces only.

F) Differential coplanar pair with roughness treated ground planes. G) Single Ended low impedance micro-strip with roughness treatment for signal traces and ground plane. H) Differential micro-strip low impedance pair with roughness treatment for signal traces and ground plane. DETAILED DESCRIPTION OF THE INVENTION

According to the first example embodiment of the present invention, each transmission line is implemented as a coplanar structure of two simultaneously driven traces, i.e. used in parallel. With this arrangement, electromagnetic field will occupy the space between signal conductors and the closest ground plane, being absent in the gap between traces because they will have the same electric potential. Thus, signal current will concentrate at outer surfaces having reduced roughness as a result of treatment, while signal current through rough surface will be significantly lower. This approach is suitable for either single ended traces or differential pairs and independently for either strip-lines or micro-strips. These topologies of the traces and PCB stack are shown on Fig. 5A, Fig. 5B, Fig. 5C and Fig. 5D. In Fig.3, the results of SPICE simulation are presented for the models as shown in Fig. 1 and Fig. 2 for configurations illustrating conventional approach (plot 1) and the present invention (plot 2). Assuming the link can operate at -20dB level, the approach proposed according to the present invention provides transmitting data 2.5 times faster than conventional approach using the same materials, process and space.

For lower impedance micro-strip applications, the width of the conductor is greater, so that electromagnetic field is mostly concentrated in the space between the ground plane and the closest conductor(s) surface. In this case, there is no significant energy transfer above this layer, so that the structures shown in Figs. 5A and 5B can be implemented as shown in Figs. 5G and 5H according to another example embodiments advantageous for Single Ended and Differential signaling respectively.

Another friendly to roughness treatment topology of the traces is differential coplanar structure shown in Figs. 5E and 5F with flat surfaces of the signal traces being faced each other. In this case, electromagnetic field will be enclosed in the gap between signal traces with current reduced greatly at rough surfaces. This topology is especially suitable for low impedance signals, such as less than 30 Ohm impedance, allowing for more compact implementation.

If ground planes treated to reduce roughness are used in the above described configurations, then areas of these planes distal from signal traces shall be cut to provide direct prepreg to core adhesive contact.

Although the preferred embodiment only has been described in detail, it should be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

CLAIMS 1. A multilayer printed circuit board, comprising: a plurality of planar layers made of dielectric material, and a plurality of conductor lines secured to these dielectric material layers, wherein each conductor line is formed by a first and a second conductive traces driven in parallel, the traces being made of electrically conductive material secured with their rough surfaces to at least one dielectric layer and disposed with their smooth surfaces in superposed laminar relation to form a coplanar structure, so that the skin effect losses in the circuit structure are reduced.

2. The multilayer printed circuit board of claim 1 , wherein both first and second conductive traces are secured with their rough surfaces to a single dielectric layer in an over/under orientation.

3. The multilayer printed circuit board of claim 1 , wherein said first and second conductive traces are secured with their rough surfaces to different dielectric layers in an over/under orientation.

4. The multilayer printed circuit board of claim 1 , wherein the smooth surfaces of the conductive traces are facing each other.

5. The multilayer printed circuit board of claim 1 , wherein the smooth surfaces of the conductive traces are looking outwards.

6. The multilayer printed circuit board of claim 1 , wherein said first and second conductive traces are of equal width and overlap each other in an over/under orientation.

7. The multilayer printed circuit board of claim 1 , wherein said first and second conductive traces are of different width, the wider trace overlapping the narrow trace in an over/under orientation.

8. The multilayer printed circuit board of claim 1 , wherein each said conductive trace is formed from an etched copper metallization layer.

9. The multilayer printed circuit board of claim 1 , comprising a first and a second conductor lines to form a differential pair in a side-by-side orientation, each conductor line being formed of two conductive traces in an over/under orientation.

10. The multilayer printed circuit board of claim 1 , comprising a first and a second conductor lines to form a differential pair in a side-by-side orientation, each conductor line being formed of a single conductive trace secured with its rough surface to the inner surface of the dielectric layer, facing with their smooth surfaces a ground layer in an over/under orientation.

11. A multilayer printed circuit board, comprising: a plurality of planar layers made of dielectric material, and a plurality of conductor lines secured to these dielectric material layers, wherein a differential pair is formed by at least one first and a least one second conductive traces made of electrically conductive material, the traces being separated by at least one dielectric layer, or at least a portion of a dielectric layer, the traces being secured with their rough surface to the inner side or sides of the dielectric layer or layers, facing each other or a ground layer with their smooth surfaces, so that the skin effect losses in the circuit structure are reduced.

12. The multilayer printed circuit board of claim 11 , wherein both first and second conductive traces are secured to a single dielectric layer in a side-by-side orientation.

13. The multilayer printed circuit board of claim 11 , wherein said first and second conductive traces are secured to different dielectric layers in an over/under orientation.

14. The multilayer printed circuit board of claim 11 , wherein said first and second conductive traces are of equal width and overlap each other in an over/under orientation.

15. The multilayer printed circuit board of claim 11 , wherein said first and second conductive traces are of different width, the wider trace overlapping the narrow trace in an over/under orientation.

16. The multilayer printed circuit board of claim 11 , wherein each said conductive trace is formed from an etched copper metallization layer.

17. The multilayer printed circuit board of claim 11 , further including a differential generating circuit electrically coupled to said first and second conductor lines for generating and supplying thereto a pair of complementary current or voltage varying signals.

18. A method of reducing skin effect losses within a multilayer circuit structure, comprising the steps of: applying a first signal to a first conductive trace; and applying a second signal to a second conductive trace adjacent the first conductive trace and separated by at least one dielectric layer, wherein the first and the second conductive traces are secured with their rough surfaces to dielectric layer or layers disposed in superposed laminar relation in an over-under orientation in a vertical plane to form a coplanar structure.

19. The method of claim 18, wherein the conductive traces are secured to a single dielectric layer, their smooth surfaces looking outwards, and driven in parallel.

20. The method of claim 18, wherein the conductive traces are secured to different dielectric layers, their smooth surfaces facing each other and driven differentially.

21. The method of claim 18, wherein the conductive traces are secured with their rough surfaces to a single dielectric layer, their smooth surfaces facing a ground layer.