WO2004053967A1

WO2004053967A1 - Semiconductor apparatus, wiring board forming method, and substrate treatment apparatus

Info

Publication number: WO2004053967A1
Application number: PCT/JP2003/015808
Authority: WO
Inventors: Kanae Nakagawa; Masataka Mizukoshi; Kazuo Teshirogi
Original assignee: Fujitsu Limited
Priority date: 2002-12-10
Filing date: 2003-12-10
Publication date: 2004-06-24
Also published as: JP4489016B2; JPWO2004053967A1

Abstract

A wiring board forming method, wherein a substrate supporting base (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting base (201) by sucking a wiring formation surface (1a) onto the supporting surface (201a), for example, by vacuum sucking. The wiring formation surface (1a) is forcibly flattened by the suction thereof onto the supporting surface (201a) so that the wiring formation surface (1a) can be used as a reference plane for flattening a rear surface (1b). In this state, the rear surface (1b) is mechanically ground to grind off projected parts (12) from the rear surface (1b) for flattening treatment. Thus, the flattening can be easily and rapidly performed at low cost without producing any inconvenience such as dishing and without being restricted by wiring design by uniformizing a variation in the thickness of the substrate (particularly, semiconductor substrate).

Description

Description: Semiconductor device, method for forming wiring substrate, and substrate processing apparatus

The present invention relates to a method for forming a multilayer wiring together with an electronic device such as an LSI on a substrate, particularly a semiconductor substrate, and further forming a multilayer wiring layer on a supporting base made of a metal material or an insulating material, and removing the supporting base. The present invention relates to a method for forming a multilayer wiring film, a semiconductor device having a multilayer wiring, and a substrate processing apparatus. Background art

In recent years, the demand for further miniaturization and higher integration of semiconductor devices has been increasing, and accordingly, multilayer wiring has been required, and accordingly, advanced flattening technology has been required. This flattening technology is applied mainly to semiconductor substrates typified by silicon wafers, and is also expected to be applied to, for example, SIP (Silicon in Package), which has recently attracted attention. There is a film-shaped multi-layer wiring thin film. Conventionally, as a method of flattening an insulating layer or a wiring layer formed on a silicon semiconductor substrate, a chemical mechanical polishing (CMP) method is mainly used. In this method, an insulating layer or wiring layer to be processed is formed relatively flat in advance, a flat polishing pad is pressed, and a slurry (chemical polishing material) is used to chemically and mechanically surface the surface. Is precisely processed to be flat. The previously provided hard insulating material surface ゃ metal surface becomes the stop layer, and the CMP is completed. CMP is a method that does not depend on TTV (Total Thickness Variation) defined by the thickness variation of the semiconductor substrate and the difference between the maximum thickness and the minimum thickness of the semiconductor substrate.

Other than the CMP method, for example, several flattening methods using a cutting tool have been devised (for example, see Patent Documents 1, 2, 3, and 4). However, all of them are aimed at flattening the SOG film in the partial region on the LSI, and like CMP, This method is based on the surface to be cut and does not depend on the TTV of the semiconductor substrate.On the other hand, in the mounting substrate required for realizing SIP, only the thin film wiring layer is required to be formed inexpensively and easily. It is conceivable to use it as a poser. Conventionally, as a thin-film multilayer wiring board without through-holes, a single resin film filled with a conductive base and a plurality of wirings formed with peer holes and prepared in a final process by batch lamination Is being developed. Although this wiring board can be realized at low cost, the via diameter is about 120 to 200 μm; LZS (line space) is about 100 urn / 100; 0 u rn / 200; approx. Wm, making miniaturization difficult. Therefore, in order to realize both miniaturization and low cost, it is effective to separate a multilayer wiring thin film formed on a substrate into a substrate.

If CMP is used, fine planarization can be achieved, but the processing equipment is expensive, the throughput is low, and the manufacturing cost is high. When a metal such as copper and an insulator are planarized at the same time, a depression called dishing may appear in a portion where the pattern is sparse. Since it is necessary to avoid the occurrence of dishing, the size of the wiring pattern in an LSI or the like is limited. Therefore, it is necessary to arrange the wiring pattern so that a blank portion of the pattern is not formed. On the other hand, in order to form the above-described multilayer wiring thin film, it is necessary to first form a multilayer wiring thin film on a support base and peel or remove the support base. As a method of peeling, the adhesion improving material is applied only to the outer peripheral portion of the substrate by utilizing the low adhesiveness between the insulating resin of the multilayer wiring thin film and the supporting base, and after the formation of the wiring layer is completed, the application portion of the adhesion improving material is applied. There is a method of separating the multi-layered wiring thin film from the supporting base by separating the multi-layer wiring thin film from the supporting base by separating the uncoated portion from the support. This method of peeling is the image of peeling the film, which may damage the circuit. On the other hand, the method of removing the supporting substrate is a method of removing the supporting substrate by a grinder and etching, for example, when the supporting substrate is a semiconductor substrate. If a metal plate such as A 1 or Cu is used as the support base, it is removed by etching. Whichever of these methods is adopted, the supporting substrate itself is reflected in the cost, and when the supporting substrate is used as the semiconductor substrate in the latter method, the residue left by the grinding becomes waste as it is. The garbage generated in the process is enormous, and the negative impact on the environment cannot be ignored. Patent Document 1

Japanese Patent Application Laid-Open No. Hei 7—3 2 6 6 14

Patent Document 2

Unexamined Japanese Patent Publication No. Hei 8-11109

Patent Document 3

Japanese Patent Application Laid-Open No. 9-1 8 2 6 16

Patent Document 4

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its main object a machining method other than CMP represented as a planarization method. In consideration of this, uniformity in thickness of substrates (especially semiconductor substrates, conductors, and insulating substrates) is uniform, and high-speed flattening is easy and inexpensive without inconveniences such as dicing and with no restrictions on wiring design. To achieve. In addition, when the substrate is finally removed to obtain a multilayer wiring thin film by itself, precise control of the film thickness of each wiring layer constituting the multilayer wiring thin film is easily performed, and efficiently and at low cost. It is an object of the present invention to provide a method for forming a wiring board, a semiconductor device, and a substrate processing apparatus, which are capable of realizing a wiring thin film having a fine wiring structure by removing a copper plate. Disclosure of the invention

The method of forming a wiring board according to the present invention is a method of forming wiring on a substrate, wherein a flattening process is performed by a first machining process on a back surface of the wiring forming surface with reference to the wiring forming surface of the substrate. And an insulation covering the wiring and the wiring on the wiring forming surface. A step of forming a film; and a step of performing a planarization process by a second mechanical processing so that a surface of the wiring and a surface of the insulating film are continuously flattened with reference to the back surface. In the method for forming a wiring board according to the present invention, a step of uniforming the thickness of a support base by a first machining is provided, and a wiring and an insulating film covering the wiring are formed on the surface of the support base having a uniform thickness. Forming a wiring layer composed of the wiring and the insulating film by performing a flattening process by a second machining so that the surface of the wiring and the surface of the insulating film are continuously flat. Forming a wiring thin film having the wiring layer and having a uniform thickness by removing the support base. A semiconductor device of the present invention includes a semiconductor substrate, a semiconductor element formed on a surface of the semiconductor substrate, and a multi-layer wiring in which each wiring is stacked in a plurality of layers in an insulator together with the semiconductor element. In the semiconductor device, the semiconductor substrate is subjected to machining based on the front surface on a rear surface side of the front surface on which the semiconductor element is formed, so that the rear surface is flattened and the substrate thickness is made uniform. Has been done. The substrate processing apparatus of the present invention is a substrate processing apparatus for forming wiring on a substrate, has a flat support surface, adsorbs the substrate to the support surface on one side, and forcibly applies the one side. A substrate support for supporting and fixing the substrate as a flat reference surface, and a byte for cutting the other surface of the substrate supported and fixed to the substrate support, and forming the wiring of the substrate with the byte. The surface is cut and flattened so that the surface of the wiring and the surface of the insulating film are continuously flat. BRIEF DESCRIPTION OF THE FIGURES

1A to 1E are schematic sectional views showing the method for forming the multilayer wiring board according to the present embodiment in the order of steps.

2A to 2C are schematic cross-sectional views illustrating a method of forming a multilayer wiring board according to the first embodiment in the order of steps. 3A to 3C are schematic cross-sectional views showing a method for forming a multilayer wiring board according to the first embodiment in the order of steps.

4A to 4C are schematic cross-sectional views illustrating a method for forming a multilayer wiring board according to the first embodiment in the order of steps.

FIG. 5 is a schematic diagram showing a specific example of each of the planarization steps in FIGS. 2A, 3A, and 4B.

FIG. 6 is a schematic diagram showing another specific example of each of the flattening steps in FIGS. 2A, 3A, and 4B.

FIG. 7 is a schematic sectional view showing a comparative example of the first embodiment.

8A and 8B are configuration diagrams of a grinding device.

FIG. 9 is a block diagram showing the configuration of the cutting device.

10A to 10G are schematic configuration diagrams showing the configuration of the cutting device.

FIG. 11 is a schematic configuration diagram showing an arrangement configuration of each part of the cutting apparatus.

FIG. 12 is a flowchart of the cutting process.

FIG. 13 is a schematic perspective view showing an overview of a semiconductor device to which the present invention is applied. FIG. 14 is a schematic plan view showing an overview of a semiconductor device to which the present invention is applied and disclosed in the present embodiment.

15A to 15D are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device including multilayer wiring according to the second embodiment in the order of steps.

16A to 16C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device including multilayer wiring according to the second embodiment in the order of steps.

FIGS. 17A to 17C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device including multilayer wiring according to the second embodiment in the order of steps.

FIG. 18A to FIG. 18C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device including multilayer wiring according to the second embodiment in the order of steps.

FIGS. 19A to 19C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device including multilayer wiring according to the second embodiment in the order of steps.

FIG. 2 OA and FIG. 2 OB are schematic cross-sectional views showing a state in which a MOS transistor is formed in an element region. FIG. 21 is a schematic cross-sectional view showing main steps in a modification of the method for manufacturing a semiconductor device including the multilayer wiring according to the second embodiment.

22A to 22C are schematic cross-sectional views illustrating a method of forming a multilayer wiring board according to the third embodiment in the order of steps.

23A to 23C are schematic cross-sectional views illustrating a method of forming a multilayer wiring board according to the third embodiment in the order of steps.

24A to 24C are schematic cross-sectional views illustrating a method of forming a multilayer wiring board according to the fourth embodiment in the order of steps.

25A and 25B are schematic cross-sectional views illustrating a method of forming a multilayer wiring board according to the fourth embodiment in the order of steps. BEST MODE FOR CARRYING OUT THE INVENTION

One basic principle of the present invention

First, the basic gist of the present invention will be described.

In the present invention, it is assumed that the main object of the flattening method is a machining method other than CMP represented by cutting using a byte. Metals such as copper, aluminum and nickel, and insulating materials such as polyimide are materials that can be easily cut with a byte. Wiring and insulating films made of these materials on a semiconductor substrate can be easily and rapidly planarized by using cutting. There is no dishing in cutting. The problem when using cutting for flattening a semiconductor substrate typified by a silicon wafer is that cutting is performed on the back side (back side) of the substrate. Generally, the TTV of a silicon substrate is in the range of 1 m to 5 m, and 5! ! ! Degree of order has no effect on photolithography and is usually not considered. However, in the case of cutting, it is greatly affected by the value of TTV. The flatness accuracy by cutting does not fall below the value of TTV. Therefore, when cutting is used for flattening a semiconductor substrate, it is first necessary to control the TTV of the substrate to a target cutting accuracy or less. In consideration of the above circumstances, the present inventor, before forming the wiring and the insulating film, first grinds the back surface with reference to the surface on which the wiring is formed, and reduces the cutting accuracy to below the TTV of the semiconductor substrate. I thought of keeping it down. In this case, it is ideal that τ TV is reduced and the thickness variation of each semiconductor substrate is suppressed to the cutting accuracy or less. However, if the TTV can be made smaller, the thickness of individual semiconductor substrates can be detected during cutting. The amount of cutting can be controlled by detecting the thickness of each individual semiconductor substrate. Further, in the present invention, the above-mentioned cutting technique is applied to the formation of a film-like multilayer wiring thin film. That is, it is used when a wiring layer is laminated on a support base made of an insulating material and a conductive material to form a multilayer wiring thin film, and then the support base is removed to provide only the multilayer wiring thin film as an interposer. In this case, since a metal plate or an insulating plate is used as the support base, the flattening (uniform thickness) step of the support base, which is a pre-process of forming a wiring layer, can be performed by cutting. Then, the flattening process at the time of forming each wiring layer is performed by cutting, and the supporting base can be removed by cutting in the supporting base removing step. In this way, the flattening of the support base, the flattening of each wiring layer at the time of formation, and the series of cutting of the support base can all be performed by cutting using a byte. High precision planarization of the layer and substrate removal are achieved. Furthermore, when the support base is an insulating plate, the support base is removed by an arbitrary thickness when the support base is removed by utilizing the easy, high-speed, and high-precision flatness controllability of the cutting process. It is also possible to leave it flat and to use it as an insulating layer. In addition, when the support base is a metal plate, it becomes possible to collect the cuttings generated by the cutting and reuse it for forming the support base. One specific embodiment of the present invention

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings based on the above-described basic structure. This will be described in detail with reference to FIG.

(First Embodiment)

Here, a silicon semiconductor substrate (silicon wafer) is exemplified as a substrate, and a case is described in which a multilayer wiring in which wirings are stacked in a plurality of layers in an insulator is formed on the semiconductor substrate.

1A to 1E, 2A to 2C, 3A to 3C, and 4A to 4C are schematic cross-sectional views illustrating a method of forming a multilayer wiring board according to the present embodiment in the order of steps. FIG. First, as shown in FIG. 1A, a silicon semiconductor substrate 1 is prepared. Normally, the silicon semiconductor substrate is not uniform in thickness as shown in the figure, but is in a state accompanied by undulation. Therefore, as a pre-process for performing cutting using a byte, which will be described later, on one main surface of the semiconductor substrate 1, here, the substrate surface (wiring forming surface la), the other main surface of the semiconductor substrate 1, here Then, the back surface 1b (of the wiring forming surface 1a) is flattened.

Specifically, as shown in FIG. 1B, a substrate support table 201 having a flat support surface 201a is prepared, and a wiring is formed by suction on the support surface 201a, for example, by vacuum suction. The semiconductor substrate 1 is fixed to the substrate support 201 by adsorbing the surface 1a. At this time, the wiring forming surface 1a is forcibly made flat by adsorption to the support surface 201a, whereby the wiring forming surface 1a becomes a reference surface for flattening the back surface 1b. In this state, the back surface 1 b is machined, in this case, ground, and the convex portion 12 of the back surface 1 b is ground and removed to be flattened. In this case, it is preferable to control the amount of cutting of the back surface 1b by the distance from the wiring forming surface 1a. As a result, the thickness of the semiconductor substrate 1 is controlled to be constant, specifically, TTV (the difference between the maximum thickness and the minimum thickness of the substrate) is equal to or less than a predetermined value, specifically, the TTV is controlled to 1 m or less. Will be. Subsequently, as shown in FIG. 1C, the semiconductor substrate 1 is detached from the substrate support base 201, and a photosensitive resin, for example, photosensitive polyimide 13 is coated on the wiring forming surface 1a of the semiconductor substrate 1. Then, the photosensitive polyimide 13 is processed by photolithography to form a predetermined electrode pattern 13a. Subsequently, as shown in FIG. 1D, a metal, for example, a copper film is formed on the wiring forming surface 1 a by, for example, a sputtering method so as to cover the photosensitive polyimide 13, thereby forming a seed layer 2. Subsequently, as shown in FIG. 1E, using the seed layer 2 as an electrode, copper is deposited by a plating method so as to embed the photosensitive polyimide 13 to form a ground (GND) electrode 3. Subsequently, a cutting process using a byte is performed on the wiring forming surface 1a to make it flat. Specifically, as shown in FIG. 2A, the back surface 1 b of the semiconductor substrate 1 is attracted to the support surface 11 a of the substrate support 11 by, for example, vacuum suction, and the semiconductor substrate 1 is attached to the substrate support 11. Fixed to. At this time, the thickness of the semiconductor substrate 1 is kept constant by the flattening process shown in FIG. 1B, and further, there is no undulation or the like due to the suction shown in FIG. 2A. This is a reference plane for flattening the wiring forming surface 1a. In this state, the surface layer of the GND electrode 3 on the wiring forming surface 1a is machined, in this case, cut using a byte 10 made of diamond or the like, and is flattened. Subsequently, as shown in FIG. 2B, a photoresist 14 is applied on the flattened GND electrode 3, and the photoresist 14 is processed by photolithography to form a predetermined via pattern 14a. An opening is formed. Then, copper or the like is buried in the opening of the via pattern 14a by a plating method to form the via portion 4. Subsequently, as shown in FIG. 2C, for example, after the photoresist 14 is peeled off, an insulating resin 5 is formed on the wiring forming surface 1a so as to cover and bury the via portion 4. Next, the wiring forming surface 1a is cut again using a byte and flattened. Specifically, as shown in FIG. 3A, the back surface 1b is attracted to the support surface 11a of the substrate support 11 by, for example, vacuum suction, and the semiconductor substrate 1 is fixed to the substrate support 11. At this time, similarly to the above, the back surface 1b becomes a reference surface for flattening the wiring forming surface 1a. In this state, the via layer 4 and the surface layer of the insulating resin 5 on the wiring forming surface 1a are machined.In this case, the pipe 10 is used, and the semiconductor substrate 1 is rotated, for example, at 800 rpm to 160 rpm. They are cut at a rotation speed of about a degree to flatten them. By this flattening process, the via layer 4 exposes its upper surface, and the via layer 4 is embedded in the insulating resin 5 to form the peer layer 21 having a uniform thickness. Subsequently, as shown in FIG. 3B, a copper film is deposited on the planarized via portion 4 and the surface of the insulating resin 5 by a sputtering method to form a shield layer 6, and then the first photoresist is formed. Then, the first photoresist 15 is processed by photolithography to form a predetermined wiring pattern 15a. Then, using the shield layer 6 as an electrode, the wiring pattern 15 a of the first photoresist 15 is buried by a plating method to form a wiring 7. Subsequently, as shown in FIG. 3C, after removing the first photoresist 15 using, for example, an alkaline stripper, a second photoresist 16 is applied to the wiring 7 so as to bury the same. The second photoresist 16 is processed by photolithography to form a predetermined via pattern 16a. Then, a via pattern 16a is buried with copper or the like by a plating method to form a via portion 8. Subsequently, as shown in FIG. 4A, after removing the second photoresist 16 and the seed layer 6 using, for example, an alkaline stripper, wiring is formed so as to cover and bury the wiring 7 and the via portion 8. An insulating resin 9 is formed on the surface 1a. Subsequently, the wiring forming surface 1a is again subjected to cutting using a byte and flattened. Specifically, as shown in FIG. 4B, the back surface 1b is sucked to the support surface 11a of the substrate support 11 by, for example, vacuum suction, and the semiconductor substrate 1 is fixed to the substrate support 11. At this time, similarly to the above, the back surface 1b becomes a reference surface for flattening the wiring forming surface 1a. In this state, the via layer 8 and the surface layer of the insulating resin 9 on the wiring forming surface 1a are machined and flattened. Here, cutting using byte 10 is performed as an example of machining. By this planarization process, the wiring 7 and the via portion 8 connected thereto are buried in the insulating resin 9 so that the upper surface of the via portion 8 is exposed. 22 is formed. Then, as shown in FIG. 4C, a series of steps similar to those at the time of forming the first wiring layer 22, that is, FIGS. 3B, 3C, 4A, and 4B are performed several times. The wiring and the via connected thereto are embedded in the insulating resin to form a laminated structure. In the drawing, the wiring 31 and the via portion 32 connected thereto are embedded in the insulating resin 33, and the second wiring layer 23 having a uniform thickness, and the second wiring layer 23 The wiring 34 formed above is illustrated. Thereafter, a multilayer wiring structure is completed on the semiconductor substrate 1 through formation of a protective film (not shown) covering the entire surface of the semiconductor substrate 1 and the like. In the present embodiment, one semiconductor substrate has been described. However, the steps of the present embodiment may be performed on a plurality of semiconductor substrates constituting a lot, and the thickness of each semiconductor substrate may be made uniform. . As a result, for example, it is possible to perform processing such as cutting on each substrate in one and the same lot under the same conditions. In each of the flattening steps in FIGS. 2A, 3A, and 4B, the semiconductor substrate 1 is parallelized based on the back surface lb, and the position of the wiring forming surface 1a is detected and detected. The amount of shaving is calculated from the wiring formation surface 1a, and the byte 10 is controlled.

Specifically, “parallel alignment” means, as shown in FIG. 5, when detecting the position of the wiring forming surface 1 a using the laser beam irradiation means 17, the portion around the wiring forming surface 1 a is detected. Insulating resin 5, 9 and photosensitive poly at a plurality of locations, for example, three locations A, B, C Irradiation is performed by irradiating the laser light 17a to the imid 13 (or the seed layer 2 in some cases), heating and scattering them, and exposing a part of the wiring forming surface 1a. In this case, as shown in FIG. 6, when detecting the position of the wiring forming surface 1a, the semiconductor substrate 1 is suction-fixed to the substrate support base 11 having the opening 11b and the infrared laser The backside 1b is irradiated with infrared laser light from the opening 11b using the light irradiator 18 to reflect the reflected light from the wiring forming surface 1a to this infrared laser light irradiator 18 (or The measurement may be performed by a laser light measuring device provided in the vicinity. Here, a comparative example of the present embodiment is shown in FIG. In this comparative example, a case where a multilayer wiring structure 202 is formed on a semiconductor substrate 201 without performing the flattening process of the present embodiment will be exemplified. As described above, when the flattening process is not performed, as the number of wiring layers increases, unevenness on the upper surface becomes remarkable, and multilayer wiring is hindered. On the other hand, in the present embodiment, first, the back surface 1b of the semiconductor substrate 1 is flattened on the basis of the wiring formation layer 1a, and then the thickness of the wiring formation layer 1a is determined on the basis of the back surface 1b. Since a uniform via layer 21 and wiring layers 22 and 23 are sequentially formed, even if a larger number of wiring layers are stacked, the generation of unevenness is suppressed without impairing the flatness. A fine wiring structure is realized. As described above, according to the present embodiment, the thickness variation of the semiconductor substrate 1 is equalized, and inconvenience such as dicing does not occur. As a result, high-speed flattening can be performed easily and inexpensively without restriction of wiring design. Further, it is possible to easily and precisely realize a fine multilayer wiring structure.

[Configuration of grinding machine]

Here, a specific apparatus configuration for performing the grinding process described with reference to FIG. 1B will be described.

Fig. 8 shows the configuration of the grinding machine. Fig. 8A is a plan view and Fig. 8B is a side view. is there. The grinding apparatus includes a storage section 202 for storing a semiconductor substrate (semiconductor wafer 18) 1, a hand section 203 for transporting the semiconductor substrate 1 to each processing section, and a semiconductor for grinding. It comprises a turntable 204 on which the substrate 1 is mounted and fixed, and a grinder part 205 for grinding the semiconductor substrate 1. The storage section 202 has a storage cassette 211 in which a plurality of semiconductor substrates 1 are stored, and each semiconductor substrate 1 is stored as shown in FIG. 8B.

The hand section 203 has a transfer hand 211, which removes the semiconductor substrate 1 from the storage cassette 211, transfers the semiconductor substrate 1 to the turntable 204 in the illustrated example, and also processes the semiconductor substrate 1 after the processing. The semiconductor substrate 1 is transported from the turntable 204 to the storage section 202. The turntable 204 is provided with a plurality (three in this case) of chuck tables 2 13 for chucking the semiconductor substrate 1 on the surface, and is rotatable, for example, in the direction of arrow M in FIG. 8B.

The grinder part 205 has a grindstone 214 attached to its lower surface in a detachable manner, and the grindstone 214 is brought into contact with the surface of the semiconductor substrate 1 chucked on the chuck table 213. 8 Grind and grind in the direction of arrow N of B. Here, for example, two types of whetstones with different roughness are used. In order to perform a grinding process using this grinding device, first, the semiconductor substrate 1 is taken out of the storage portion 202 by the transfer hand 211 of the hand portion 203, and the chuck table 210 of the turntable 204 is taken out. Place and fix on 3. Subsequently, the grindstone 2 14 of the grinder part 205 is brought into contact with the surface of the semiconductor substrate 1 to perform grinding, and the surface is ground. At this time, first grind with a coarse grindstone, and then with a fine grindstone for finishing. Then, the semiconductor substrate 1 after finishing grinding is removed from the chuck table 2 13 by the transfer hand 2 12 and stored in the storage section 202.

[Configuration of cutting equipment] Here, a specific device configuration for executing the cutting process described with reference to FIGS. 2A, 3A, and 4B will be described.

FIG. 9 is a block diagram showing the configuration of the cutting apparatus, and FIGS. 10A to 10G are similar schematic configuration diagrams. This cutting device includes a storage unit 101 (FIGS. 9 and 10A) for storing a semiconductor substrate (semiconductor wafer 18) 1 and a hand unit 1 for transporting the semiconductor substrate 1 to each processing unit. 0 2 (Fig. 9, Fig. 10B, Fig. 10C), a chuck table section 103 for chucking the semiconductor substrate 1 during cutting (Fig. 9, Fig. 10D), and a Positioning Sensing unit 104 (Fig. 9, Fig. 10E), Cutting unit 105 for flattening the semiconductor substrate 1 (Fig. 9, Fig. 10F), and cleaning after cutting Cleaning unit 106 (Fig. 9, Fig. 10G), optical sensor unit 107 for photographing the cutting state (Fig. 9, Fig. 10D), and control unit 108 for controlling these (FIG. 9). Note that FIGS. 10A to 10G are component diagrams of each part, and the installation direction, scale, and the like are not accurate for convenience. The storage section 101 includes a storage cassette 111 for storing a plurality of semiconductor substrates 1 and an elevator mechanism 1 1 2 for raising and lowering the semiconductor substrate 1 to a height at which the transfer hand 114 is taken out. And a Z-axis drive unit 113 that drives the elevator mechanism up and down. The hand unit 102 removes the semiconductor substrate 1 from the storage cassette 111, sucks the vacuum, suctions the semiconductor substrate 1, and transports the semiconductor substrate 1 to the sensing unit 104. Driving with 1 axis (1st rotation axis) to Θ 3 axis (3rd rotation axis) ® 1 axis drive unit 1 15 a, Θ 2 axis (2nd rotation axis) drive unit 1 15 b, ® 3 axis It has a drive unit 115c and a Z-axis drive unit 115d that drives the Z-axis. The transfer hand 114 is a scalar type 1 pot and can be easily handled to each processing unit. The port mechanism of the transfer hand 114 is not limited to this, and may be, for example, an XY axis orthogonal type. The chuck table section 103 mounts and fixes the semiconductor substrate 1 by, for example, vacuum suction, and the substrate support table (rotating table) 11 configured to rotate the semiconductor substrate 1 at a predetermined rotation speed. And a rotation drive unit 116 for driving the substrate support 11. The substrate support 11 fixes the semiconductor substrate 1 by a vacuum mechanism. The substrate support 11 serves as a reference plane for processing. Therefore, in order to maintain planar accuracy at the time of fixing and processing, it is preferable that the chuck surface (supporting and fixing surface) is made of a porous material and the entire surface of the semiconductor substrate 1 is chucked. Metal, ceramic, resin, etc. are used for the material including the chuck surface. In the present embodiment, during the cutting of the surface of the semiconductor substrate 1, the semiconductor substrate 1 mounted and fixed on the substrate support 11 is rotated at a rotation speed of, for example, about 800 rpm to about 160 rpm. Rotate for cutting. The sensing unit 104 includes a CCD camera 117, a semiconductor substrate 1 mounted thereon and fixed, and a rotary table 118 configured to freely rotate the semiconductor substrate 1 at a predetermined rotation speed. And a rotation drive unit 119 for driving the semiconductor substrate 1. The CCD camera 117 captures an image of the outer periphery of the semiconductor substrate 1 installed on the rotary table 118. The cutting section 105 includes a hard byte 10 which is a cutting tool made of diamond or the like, and an X-axis stage 120 and a Y-axis stage 122 on which the byte 10 is installed, and an X-axis stage. The X-axis drive unit 122 drives the byte 10 in the X direction (shown by the arrow M in Fig. 10E) at the stage 120 and the Y direction (Fig. 10E) (Indicated by an arrow N in the middle) and a Y-axis drive unit 123 for driving the byte 10. The cleaning unit 106 includes a spin table 124 for fixing the semiconductor substrate 1 in a vacuum and rotating at a predetermined rotation speed, a rotation driving unit 125 for rotating the spin table 124, and a semiconductor substrate 1. A nozzle 1226 for discharging cleaning water is provided on the surface, and while the semiconductor substrate 1 is vacuum-fixed by the spin table 124, the semiconductor substrate 1 is rotated from the nozzle 126 while rotating. Cleaning water is discharged onto the surface of the Wash away foreign objects. Thereafter, the semiconductor substrate 1 is rotated at a high speed by a spin table 124 while air blowing, and dried while blowing off cleaning water remaining on the substrate surface. The optical sensor unit 107 has a light emitting unit 127 and a light receiving unit 128 arranged opposite to the semiconductor substrate 1 mounted and fixed on the substrate support table 11 of the chuck table unit 103. The light emitting section 127 is arranged on one side and the light receiving section 128 is arranged on the other side. The control unit 108 is a Z-axis drive unit 113 of the storage unit 101, a 1-axis to a 3-axis drive unit 1150 of the node unit 102, and a Z-axis drive unit. 1 1 5 d, rotation table 1 16 of the check table section 103, rotation drive section 1 19 of the sensing section 104, X axis drive section 1 2 2 of the cutting section 105, and Y axis drive section 1 2 3, a drive control unit 1 2 9 that controls the rotary drive 1 2 5 of the cleaning unit 1 06, a detection unit 1 3 0 that detects light emission and reception of the optical sensor 1 7 0, and sensing Calculating unit 1 3 1 that calculates the center position of the semiconductor substrate 1 using the image captured by the CCD camera 1 17 of the unit 104, and measures and calculates the dimensions of the semiconductor substrate 1 together with the optical sensor unit 107. And a main control unit 132 that integrally controls the drive control unit 12 9, the detection unit 13 0, and the calculation unit 13 1, and a display unit 13 that displays the control state of the main control unit 13 2 3 and various drive commands to the main control And a movement command unit 1 34 for obtaining. The cutting process will be described with reference to FIGS. 11 and 12.

Fig. 11 is a schematic diagram showing an arrangement state of the storage unit 101, the chuck table unit 103, the sensing unit 104, the cutting unit 105, and the cleaning unit 106 centered on the hand unit 102. is there. Here, illustration of the optical sensor unit 107 and the control unit 108 is omitted. FIG. 12 is a flowchart showing the cutting process.

First, the transfer hand 114 of the hand unit 102 takes out the semiconductor substrate 1 from the storage cassette 111 of the storage unit 101 in which the semiconductor substrate 1 is stored (step S1). Income By the elevator mechanism 112 of the storage section 101, it is moved up and down to the take-out height of the semiconductor substrate 1 of the transfer hand 114. Next, the transport hand 114 vacuum sucks the semiconductor substrate 1 and transports it to the sensing unit 104. In the sensing unit 104, the semiconductor substrate 1 is rotated by 360 ° using the rotary table 118, the outer periphery of the semiconductor substrate 1 is imaged by the CCD camera 112, and the result is stored in the control unit 108. Processing is performed by the operation unit 13 1 to calculate the sensor 1 position of the semiconductor substrate 1 (step S 2). Next, the transfer hand 114 corrects the center one position based on the calculation result of the center one position, and conveys the semiconductor substrate 1 to the chuck table part 103, and the substrate support base 11 vacuums this. Fix (step S3). The substrate support 11 serves as an additional reference plane. Therefore, in order to maintain the planar accuracy at the time of fixing and processing, it is preferable that the chuck surface is made of a porous material and the entire surface of the semiconductor substrate 1 is chucked. The material is metal, ceramic, resin, etc. A light-emitting unit 114 and a light-receiving unit 115 are arranged opposite to the top and bottom of the chucked semiconductor substrate 1, respectively, and the dimensions of the semiconductor substrate 1 are measured and calculated together with the control unit 108, and the result is calculated. It feeds back to the X-axis drive unit 112 of the cutting unit 105 to instruct the movement amount for cutting. Here, when the cut surface is a wiring forming surface, specifically, as shown in FIG. 5, it is preferable to irradiate a laser beam, heat and scatter the resist mask, and expose the surface. Then, the position is measured using a reflection sensor using infrared laser light as shown in FIG. Note that a transmission sensor may be used for measuring the position. Then, based on the above calculation results (substrate dimensions), the byte 10 to be cut is moved by the X-axis stage 120 in the direction of the arrow M as in FIG. 1 OF, and cutting is started (step S4). ). In this way, when the cutting amount reaches the set value, the cutting to the set dimension is completed (step S5). Next, the transfer hand 1 14 removes the semiconductor substrate 1 from the substrate Step S6), and transport to the cleaning section 106. In the cleaning unit 106, while the semiconductor substrate 1 is vacuum-fixed to the spin table 124 and rotated, the foreign matter remaining on the surface of the processed semiconductor substrate 1 is washed away by the cleaning water discharged from the nozzle 126. After that, it is rotated at high speed with air blow and dried while blowing off the washing water (Step S7). After the drying is completed, the transfer hand takes out the semiconductor substrate 1 again and finally stores it in the storage cassette 111 of the storage section 101 (step S8). In this embodiment, after the back surface is ground using the above-described grinding apparatus with reference to the wiring forming surface on which the wiring and the insulating film are formed, each of the above-described grinding machines is used to reference the back surface. The surface of the wiring and the surface of the insulating film are planarized.

(Second embodiment)

Here, a silicon semiconductor substrate is exemplified as a substrate, and a case where a multilayer wiring layer formed by laminating a plurality of wiring layers formed of respective wirings in an insulator when manufacturing an LSI is disclosed. As a semiconductor device including a multilayer wiring layer, there is a semiconductor device having a form as shown in FIGS. In the semiconductor device of FIG. 13, an electrode 63 a is formed on a silicon semiconductor substrate 101 so as to surround an element region 102 in which a plurality (many) of semiconductor elements (such as MOS transistors) are formed. It is formed so that each semiconductor element is electrically connected to the electrode 63a. On the other hand, in the semiconductor device shown in FIG. 14, a plurality of electrodes 63 a are formed in a matrix on a silicon semiconductor substrate 101, and a plurality (many) of semiconductor elements are formed between the electrodes 63 a. It is. That is, in the case of FIG. 14, the region between the electrodes 63 a becomes the element region 103. The present invention is applicable to both the semiconductor devices of FIGS. 13 and 14. However, in the following description, for convenience, the semiconductor device of the embodiment shown in FIG. 14 is exemplified. The schematic cross section along the line I is shown in Fig. 15 and subsequent figures. Figure 15 A to Figure 15 D, Figure 16 A to Figure 16 C, Figure 17 A to Figure 17 C, Figure 18 A FIGS. 18C and 19A to 19C are schematic cross-sectional views showing the method of manufacturing the semiconductor device including the multilayer wiring according to the present embodiment in the order of steps. As shown in FIG. 15A, a silicon semiconductor substrate 1 is prepared, and an impurity diffusion region 61 and an impurity diffusion region 61 each having an impurity diffusion layer of each semiconductor element formed on the substrate surface (wiring forming surface 1a). A protective film 64 is sequentially formed on the LSI wiring 63 so that the surface of the LSI wiring 63 embedded in the insulating layer 62 made of, for example, an inorganic material, and the electrode 63 a of the LSI wiring 63 is exposed. I do. In the illustrated example, the region between the adjacent electrodes 63a (and the LSI wiring 63) is the element region 103 in FIG. In this case, the element region 103 collectively covers the region between the adjacent electrodes 63a. Here, in FIG. 15A, illustration of each semiconductor element is omitted for convenience. More precisely, as shown in FIG. 20A, a plurality (many) of semiconductor elements, here a MOS transistor 104, are formed in the element region 103. As shown in FIG. 20B, in each MOS transistor 104, a gate electrode 112 is patterned on the surface of the element region 103 via a gate insulating film 111, and the gate electrode 110 is patterned. Impurities are introduced into the impurity diffusion regions 61 on both sides of the substrate 12 to form a pair of impurity diffusion layers 113 serving as a source / drain. On the surface of the element region 103, wirings 114 are patterned so as to be connected to the respective impurity diffusion layers 113. These wirings 114 constitute a part of the LSI wiring 63. I do. Note that the impurity diffusion region 61 is a region in which a large number of impurity diffusion layers are formed in a large number of MOS transistors, and there are portions where the impurity diffusion layer actually exists and portions where the impurity diffusion layer does not exist. For convenience, these regions are collectively expressed as impurity diffusion regions.

Since an extremely large number of MOS transistors 104 are formed only in one region between the adjacent electrodes 63a, the MOS transistor 104 is illustrated in FIG. 15A and the following drawings for convenience. Is omitted. Then, as described above, the MOS transistor 104, the LSI wiring 63, the protective film 6 The back surface 1b of the wiring forming surface 1a is flattened as a pre-process for performing a cutting process using a byte, which will be described later, on the wiring forming surface 1a formed with 4 or the like. Specifically, as shown in FIG. 15B, a substrate support table 201 having a flat support surface 201a is prepared, and the support surface 201a is suctioned, for example, wiring is performed by vacuum suction. The semiconductor substrate 1 is fixed to the substrate support 201 by adsorbing the formation surface 1a. At this time, the wiring forming surface 1a is forcibly flattened by adsorption to the support surface 201a, whereby the wiring forming surface 1a becomes a reference surface for flattening the back surface 1b. In this state, the back surface 1b is machined, in this case, ground, and the convex portion 12 of the back surface 1b is ground and removed to be flattened. In this case, it is preferable to control the cutting amount of the back surface 1b by the distance from the back surface 1b. Thereby, the thickness of the semiconductor substrate 1 is controlled to be constant, specifically, the TTV (difference between the maximum thickness and the minimum thickness of the substrate) is controlled to 1 or less. Subsequently, as shown in FIG. 15C, the semiconductor substrate 1 is detached from the substrate support base 201, and a photosensitive resin, for example, photosensitive polyimide 13 is applied onto the wiring forming surface 1a of the semiconductor substrate 1. The photosensitive polyimide 13 is processed by photolithography to form a wiring pattern 13b having a shape exposing some of the electrodes 63a of the LSI wiring 63. Subsequently, as shown in FIG. 15D, a metal, for example, a copper film (a gold film or the like may be used) on the wiring forming surface 1 a by, for example, a sputtering method so as to cover the photosensitive polyimide 13. Then, it will be described as copper.) To form a seed layer 2. Subsequently, as shown in FIG. 16A, a photoresist 92 is applied on the wiring forming surface 1a, the photoresist 92 is processed by photolithography, and a predetermined pattern is formed on the photoresist 92. After the opening, copper is deposited by plating using the shield layer 2 as an electrode. Subsequently, as shown in FIG. 16B, the photoresist 92 is peeled off and deposited. The seed layer 2 is removed by etching using the copper as a mask. Subsequently, as shown in FIG. 16C, an insulating resin 42 is applied so as to embed the wiring 41 and is solidified. When forming the insulating resin 42, the exposed seed layer 2 may be removed. Subsequently, a cutting process using a byte is performed on the wiring forming surface 1a to make it flat.

Specifically, as shown in FIG. 17A, the back surface 1 b is sucked to the support surface 11 a of the substrate support 11 by, for example, vacuum suction, and the semiconductor substrate 1 is fixed to the substrate support 11. At this time, the thickness of the semiconductor substrate 1 is kept constant by flattening the back surface lb as shown in FIG. 15B, and the back surface 1b is forcibly undulated by the adsorption to the support surface 11a. In this state, the back surface 1b becomes a reference surface for flattening the wiring forming surface 1a. In this state, the surface layers of the wiring 41 and the insulating resin 42 on the wiring forming surface 1a are machined.In this case, using the byte 10, the semiconductor substrate 1 is rotated at, for example, 800 rpm to 160 rpm. It is cut at a rotation speed of about a degree and flattened. By this flattening process, a first wiring layer 51 is formed in which the upper surface of the wiring 41 is exposed and embedded in the insulating resin 42. In FIG. 17A, for convenience, the surface layers of the wiring 41 and the insulating resin 42 are illustrated as continuous flat surfaces. Subsequently, as shown in FIG. 17B, after a seed layer 19 serving as a plating electrode is formed on the planarized first wiring layer 51 by sputtering, a photoresist 14 is applied, and a photoresist 14 is applied. The photoresist 14 is processed by photolithography to form an opening in a predetermined via pattern 14a. Then, the via pattern 14a is buried with copper or the like by a plating method to form the via portion 4. Subsequently, as shown in FIG. 17C, after the photoresist 14 is peeled off, the seed layer 19 is removed by, for example, wet etching using hydrofluoric acid, and the via portion 4 is covered and buried. An insulating resin 5 is formed on the wiring forming surface 1a. Subsequently, the wiring forming surface 1a is again subjected to cutting using a byte, and is flattened. Specifically, as shown in FIG. 18A, the back surface 1 b is sucked to the support surface 11 a of the substrate support 11 by, for example, vacuum suction, and the semiconductor substrate 1 is fixed to the substrate support 11. At this time, similarly to the above, the back surface 1b becomes a reference surface for flattening the wiring forming surface 1a. In this state, the surface layer of the pier portion 4 and the insulating resin 5 on the wiring forming surface 1a is machined, in this case, cut using a byte 10 and flattened. By this flattening process, the via layer 4 has its upper surface exposed and is embedded in the insulating resin 5 to form the peer layer 21 having a uniform thickness. Actually, the via layer 4 and the surface layer of the insulating film 5 are flattened for the first time by cutting with the byte 10, but in FIG. 18A, for convenience of illustration, the byte 10 has not yet passed. The surface layers of the via portion 4 and the insulating film 5 are also shown as continuous flat surfaces. Subsequently, as shown in FIG. 18B, a copper film is deposited on the planarized via portion 4 and the surface of the insulating resin 5 by a sputtering method to form a seed layer 6, and then a photoresist 15 is applied. Then, the photoresist 15 is processed by photolithography to form a predetermined wiring pattern 15a. Then, using the seed layer 6 as an electrode, a wiring 7 for embedding the wiring pattern 15a of the photoresist 15 is formed by a plating method. Subsequently, as shown in FIG. 18C, after removing the photoresist 15 using, for example, an alkaline stripping solution, a photoresist 16 is applied so as to embed the photoresist 16 on the wiring 7, and the photoresist 16 is applied. 16 is processed by photolithography to form a predetermined via pattern 16a. Then, the via pattern 16a is buried with copper or the like by a plating method to form the via portion 8. Subsequently, as shown in FIG. 19A, after the photoresist 16 is peeled off, the seed layer 6 is removed by wet etching using, for example, hydrofluoric acid, and the wiring 7 and the via portion 8 are covered and buried. Resin 9 is formed on wiring forming surface 1a as described above. Subsequently, the wiring forming surface 1a is again subjected to cutting using a byte and flattened. More specifically, as shown in FIG. 19B, the back surface 1b is sucked to the support surface 11a of the substrate support 11 by, for example, vacuum suction, and the semiconductor substrate 1 is fixed to the substrate support 11. At this time, similarly to the above, the back surface 1b becomes a reference surface for flattening the wiring forming surface 1a. In this state, the via layer 8 and the surface layer of the insulating resin 9 on the wiring forming surface 1a are machined, in this case, cut using a byte 10 to flatten them. By this flattening process, the wiring 7 and the via portion 8 connected thereto are buried in the insulating resin 9 so that the upper surface of the via portion 8 is exposed. 2 is formed. In FIG. 19B, for convenience of illustration, the via layer 8 and the surface layer of the insulating film 9 are illustrated as continuous flat surfaces. Then, as shown in FIG. 19C, a series of steps similar to those at the time of forming the second wiring layer 52, that is, the same steps as those of FIGS. 18B, 18C, 19A, and 19B are performed. After several times, a wiring and a via connected thereto are buried in an insulating resin to form a laminated structure. In the figure, a wiring 31 and a peer portion 32 connected to the wiring 31 are embedded in an insulating resin 33, and the third wiring layer 53 having a uniform thickness, and the third wiring layer 5 The wiring 34 formed on 3 is illustrated. Thereafter, after forming a protective film (not shown) covering the entire surface of the semiconductor substrate 1, the element region 103 (including a plurality of MOS transistors 104) and the multilayer wiring structure are formed on the semiconductor substrate 1. Is completed. In the present embodiment, first, the back surface 1 b of the semiconductor substrate 1 is flattened on the basis of the wiring forming layer 1 a, and then the via layer 2 having a uniform thickness is formed on the wiring forming layer 1 a on the basis of the back surface 1 b. 1 and each wiring layer 5 1 to 5 3 are formed in order. In order to adopt this structure, even if a large number of wiring layers are stacked, the generation of uneven pattern is suppressed without impairing the flatness and the fine wiring structure. Is realized. As described above, according to the present embodiment, the thickness variation of the semiconductor substrate 1 is reduced. It realizes a semiconductor device having a fine and multi-layered wiring structure easily and precisely, enabling high-speed flattening easily and inexpensively without any limitation of wiring design without causing inconvenience such as dishing. be able to. In the present embodiment, one semiconductor substrate has been described. However, the steps of the present embodiment may be performed on a plurality of semiconductor substrates constituting a lot, and the thickness of each semiconductor substrate may be made uniform. . As a result, for example, it is possible to perform processing such as cutting on each substrate in one and the same lot under the same conditions. (Modification)

Hereinafter, a modified example of the present embodiment will be described.

In this modification, in the cutting process using the bytes described in the second embodiment, trace processing of the cut surface is added. The outline of this trace processing is shown below in Figure 21. In the cutting process using the byte according to the second embodiment, a wide range of cutting can be performed with extremely high precision (with a nano-order flat roughness) at low cost and in a short time.

However, in this case, cutting chips are generated during the cutting process and may adhere to the cutting surface. Of the insulating layers and wiring (including vias) to be cut, the cuttings of the insulating material are only attached to the cut surface by static electricity, so they can be removed after cutting. However, if wiring materials, especially Au cuttings adhere to the cutting surface, they will be bonded to it and cannot be easily removed by washing or the like. As a result, a cutting surface having a size of several im to several tens of meters adheres to a cutting surface having high flatness on the order of nanometers, which may hinder the flattening process. This is particularly remarkable when the wiring material is Au as described above, but also causes a problem with Cu and its alloys. In this modified example, in a cutting process using a byte, after a flat cut surface is formed by cutting, the cut surface is traced again using the byte at the same position (cut 0) as that of the cut. Since the depth of cut is 0, almost all new cutting chips are generated Without removing, the cutting chips adhering to the cutting surface can be reliably removed. However, it is expected that the cuttings removed by the trace treatment will adhere to the cutting surface again. In order to prevent this, it is effective to spray air, water, or a cutting oil in the byte feed direction during the trace processing. Here, in order for the byte to come into contact with the entire surface of the cutting surface, the feed speed of the byte must be equal to or lower than that during cutting. Specifically, in the cutting process shown in FIG. 17A, the surface layer of the wiring 41 and the insulating resin 42 on the wiring forming surface 1a is cut using a byte 10 and flattened. As shown in Fig. 21, with the semiconductor substrate 1 fixed on the substrate support 11, trace the byte 10 at the same byte position (cut 0) as the cut position at the time of finishing the flattening process . The feed at this time is the same as the finish, for example, 10 πι Ζ rotation. At this time, air is blown from the air delivery section 93 to the cut surface in the same direction as the feed direction of the byte 10 to prevent the cutting chips 94 from re-adhering. Here, especially in a situation where cutting chips easily adhere, water or a cutting oil may be blown at a high pressure instead of air. The tracing process of the present modified example is similarly applied to the cutting process of FIG. 18 and the cutting process of FIG. According to the present modification, the thickness variation of the semiconductor substrate 1 is made uniform, the occurrence of undulation and warpage is prevented, and high-speed operation can be performed easily and inexpensively without inconveniences such as dishing and without any restrictions on wiring design. In addition, a semiconductor device with an easy and precise fine multilayer wiring structure is realized, which enables fine flattening and also reliably removes cutting chips at the time of flattening and maintains the flatness of the cut surface. can do.

(Third embodiment)

Nikko uses a supporting substrate, specifically a copper plate, as a substrate, and A case of forming a film-like multilayer wiring thin film used as the above is disclosed. FIG. 22A to FIG. 22C and FIG. 23A to FIG. 23C are schematic cross-sectional views showing the method of forming the multilayer wiring board according to the present embodiment in the order of steps. First, as shown in FIG. 22A, for example, a copper plate 71 having a thickness of a little over l mm and a diameter of 8 inches is attracted to, for example, the chuck table 104 of the above-mentioned cutting apparatus, and a The copper plate 71 is cut using a pad 10 until the byte 10 abuts on the entire surface of the copper plate 71 to make the thickness of the copper plate 71 uniform. The cutting chips generated at this time are collected and used for copper plate regeneration. Subsequently, as shown in FIG. 22B, a resist is applied to the surface of the copper plate 71 and processed by lithography to form a first-layer wiring pattern. The LZS of the wiring pattern at this time is, for example, 5 im / 5. Then, the wiring 72 is formed by electrolytic plating using the copper plate 71 as a seed layer. Here, a protective film (not shown) is attached to the back surface of the copper plate 71 to prevent adhesion of the plating. Thereafter, the resist is removed. Subsequently, a via pattern is formed by a resist, and a via post 73 having, for example, a height of about 12 xm and a diameter of about 10 m is formed by electric plating using the copper plate 71 as a seed layer in the same manner as described above. Also in this case, a protective film (not shown) is attached to the back surface of the copper plate 71 to prevent the adhesion of the plating. After that, the resist is removed. Then, a polyimide precursor (for example, product name PI2611 manufactured by HD Microsystems) is applied by spin coating so as to embed the wiring 72 and the via post 73, and then, for example, it is increased by 3700 to 2111 in. The resin is cured by heating at a temperature rate to form a resin film 74. Thereafter, a hole reaching the surface of the copper plate 71 is formed in a part of the resin film 74 by laser light. Subsequently, the copper plate 71 was placed on the chuck table 104 with the back side down, and The depth of the hole is measured, and it is flattened by cutting using a byte 10 from the surface of the copper plate 7 to a height of about 10 mm using a byte 10, and the film thickness is uniform, and the wiring 7 A first wiring layer 81 in which the second and via posts 73 are embedded is formed. Here, the upper surface of the via post 73 is exposed from the surface of the wiring layer 81. The cutting conditions at this time are, for example, a rotation speed of 100 rpm, a feed speed of S mm Z min, a rake angle of 10 bytes of 10 °, and a cutting depth of 1 jum. Next, after forming a seed layer (a laminated film of CrZCu with a thickness of about 100 nm and 300 nm) by a sputtering method, as shown in FIG. Similarly, the wiring 75 and the via post 76 are patterned. After removing the resist, the seed layer is etched away. Subsequently, similarly, after applying the above polyimide precursor by spin coating so as to embed the wiring 75 and the via posts 76, the polyimide precursor is cured by heating at, for example, 370 ° C. at a heating rate of 2 V / min. A resin film 77 is formed. Thereafter, a hole reaching the surface of the copper plate 71 is formed in a part of the resin film 77 by laser light. Subsequently, the copper plate 71 is placed on the chuck table 104 with the back surface facing down, the depth of the hole is measured, and a byte 10 is extended from the surface of the copper plate 71 to a height of about 10 m. Then, a second wiring layer 82 having a uniform film thickness and having the wiring 75 and the via posts 76 embedded in the resin film 77 is formed. Here, the upper surface of the via post 76 is exposed from the surface of the wiring layer 82. Then, as shown in FIG. 23A, the above-described wiring layer forming step is repeatedly executed to form a multilayer wiring thin film including a desired number of wiring layers. Thereafter, a protective layer made of polyimide and having a thickness of about 13 is formed. Via via laser anywhere 7

After forming 8, the protective layer is flattened to a thickness of about 10 by cutting using a byte 10. In the example shown in the figure, the wiring layer is composed of four wiring layers, and the uppermost wiring layer has a surface formed with only the vias 78 by the above-described cutting process using the byte 10. The layer wiring thin film 80 will be exemplified. In the illustrated example, a portion of the protective layer cut to a thickness of about 10 is indicated by a broken line. Subsequently, as shown in FIG. 23B, the protective layer is placed on the chuck table 104 with the protective layer facing down, and the copper plate 71 is left in a byte 10 to leave a thickness of, for example, about 0.5 / zm. Use cutting to remove. The cutting chips generated at this time are collected and recycled for the copper plate. Then, as shown in FIG. 23C, the remaining copper plate 71 is removed by etching to complete a film-like multilayer wiring thin film 80. In this embodiment, before the copper plate 71 is cut, dicing may be performed slightly deeper than the wiring layer, and the wiring layer may be chipped. As described above, according to the present embodiment, when the support base is finally removed to obtain the multilayer wiring thin film alone, the thickness of each of the wiring layers constituting the multilayer wiring thin film 80 must be precise. The control is easily performed, and the copper plate 71 is easily and efficiently removed at low cost. For example, the via diameter is about 5 m to 10 tm, S is 5 μ, τη / 5 ^ m-20 urn A multilayer wiring thin film having a fine wiring structure of / 20 can be realized.

[Fourth embodiment]

Here, as in the third embodiment, a case is described in which a support base, specifically, a copper plate is used as a substrate to form a film-like multilayer wiring thin film used as an interposer or the like. The method is different.

24A to 24C and FIGS. 25A and 25B are schematic cross-sectional views showing the method of forming the multilayer wiring board according to the present embodiment in the order of steps. First, as shown in Fig. 24A, for example, a copper plate having a thickness of just over 1 mm and a diameter of 8 inches 7

1 is attracted to the chuck table 104 of the above-described cutting device, The copper plate 71 is cut using a diamond-made byte 10 until the byte 10 comes into contact with the entire surface of the copper plate 71 to make the thickness of the copper plate 71 uniform. The cutting chips generated at this time are collected and used for copper plate regeneration. Subsequently, as shown in FIG. 24B, a laminating film 83 made of a photosensitive epoxy resin and having a thickness of about 20 tm was formed on the surface of the copper plate 71, and exposed and developed to have a diameter of 2 μm. 0; A via hole 84 of about m is formed. After roughening the surface of the laminate film 83 with an oxidizing agent, a seed layer is formed by electroless plating. Subsequently, a wiring pattern (L / S = about 10 fim / about 10 m) is formed with a resist having a film thickness of about 10 m, and a wiring layer 85 is formed by electric plating and the via hole 84 is filled. I do. At this time, the plating may hang over the resist. 'Then, the copper plate 71 was placed on the chuck table 104 with the back side down, and the lamination film 83 was cut up to a height of about 5 m from the surface by using a byte 10. A first wiring layer 91 is formed in which the via holes 84 and the wiring layers 85, which are flattened and have a uniform film thickness and are filled in the laminate film 83, are embedded. The cutting conditions at this time are, for example, a rotation speed of 100 rpm, a feed rate of S mmZmin, a rake angle of byte 10 of 0 °, and a cutting depth of 1 Atm. Thereafter, the resist is removed and the seed layer is etched away. Then, as shown in FIG. 24C, the above-described wiring layer forming step is repeatedly executed to form a multilayer wiring thin film including a desired number of wiring layers. Thereafter, a protective layer made of polyimide and having a thickness of about 13 tm is formed. Via via laser anywhere 7

After forming 8, the protective layer is flattened by cutting using a byte 10 to a thickness of about 10 / zm. In the illustrated example, the multilayer wiring thin film 90 has three wiring layers, and the uppermost wiring layer has only the vias 78 formed by the above-described cutting process using the bytes 10. Is exemplified. In the example shown in the figure, the cut thickness is about 10 / zm. The portion of the protective layer that is shown is indicated by a broken line. Subsequently, as shown in Fig. 25A, the protective layer is placed on the chuck table 104 with the protective layer facing down, and the copper plate 71 is cut and removed using a byte 10 so as to leave a thickness of about 5 only. I do. The cutting chips generated at this time will be collected and recycled for the copper plate. Then, as shown in FIG. 25B, the remaining copper plate 71 is patterned to form predetermined wirings 82, thereby completing a film-shaped multilayer wiring thin film 90. As described above, according to the present modification, when the support base is finally removed to obtain a multilayer wiring thin film alone, precise control of the film thickness of each wiring layer constituting the multilayer wiring thin film is performed. And easily remove the copper plate 71 efficiently and at low cost. For example, the peer diameter is 5; m to 10 βm, and L / S is 5 μ. / 5 m to 20 n. A multilayer wiring thin film having a fine wiring structure of / 20 m can be realized. In the present embodiment and its modifications, a conductor substrate (copper plate) is exemplified as the support base, but the support base may be formed of an insulating substrate such as a resin. In this case, as in the present embodiment, the thickness of the support base is made uniform by cutting using a byte, and then the wiring layers are layered while being flattened and the film thickness is made uniform by cutting to form a multilayer wiring thin film. Then, the support base is removed by cutting from the back surface. In this cutting process, it is also preferable to leave the support base at an arbitrary thickness and flatten it to provide the support base with an insulating layer. In addition, when the degree of deflection of the resin to be cut, or the so-called toughness, is high, the rake angle of the byte should be 5 ° or more to reduce the roughness of the finished surface. Can be desirable. Industrial applicability

According to the present invention, the thickness variation of a substrate (especially, a semiconductor substrate) is considered in consideration of a main object other than CMP represented by cutting as a planarization method. It is possible to realize high-speed flattening easily and inexpensively without inconvenience such as dishing and without any restrictions on wiring design. Further, according to the present invention, when the support base is finally removed to obtain the multilayer wiring thin film alone, fine control of the thickness of each wiring layer constituting the multilayer wiring thin film is easily performed. In addition, the copper plate can be removed efficiently and easily at low cost, and a multilayer wiring thin film having a fine wiring structure can be realized.

Claims

The scope of the claims

1. A method of forming wiring on one main surface of a substrate to be processed,

A first step of performing first machining on the other main surface of the substrate with reference to one main surface of the substrate on which the wiring is to be formed, and flattening the other main surface of the substrate; A second step of forming the wiring and an insulating film covering the wiring on one main surface of the substrate;

The second main processing is performed on one main surface of the substrate with reference to the other main surface of the substrate, and the one main surface of the substrate is flattened so that the surface of the wiring and the surface of the insulating film are continuous. A third step of flattening so that

A method for forming a wiring board, comprising:

2. The method according to claim 1, wherein the substrate is a semiconductor substrate.

3. The method for forming a wiring board according to claim 2, further comprising, before the first step, a step of forming a semiconductor element on the one main surface of the semiconductor substrate.

4. A series of steps including the second step and the third step is repeated a plurality of times to form a multilayer wiring in which the wirings are stacked in a plurality of layers in the insulating film. 2. The method for forming a wiring board according to claim 1, wherein:

5. The method for forming a wiring board according to claim 1, wherein the first machining is grinding.

6. The method for forming a wiring board according to claim 1, wherein the second machining is cutting using a byte.

7. The method for forming a wiring board according to claim 2, wherein a difference between a maximum thickness and a minimum thickness of the semiconductor substrate is controlled to 1 im or less by the first machining.

8. The method according to claim 2, wherein the steps are performed on a plurality of the semiconductor substrates, and the thickness of each of the semiconductor substrates is made uniform.

9. In the third step, the semiconductor substrate is parallelized with reference to the other main surface, the position of the one main surface is detected, and the amount of shaving from the detected one main surface is determined. Calculating and controlling the wiring board according to claim 2, Forming method.

10. When detecting the position of the one main surface, the insulating film at a plurality of locations around the one main surface is irradiated with laser light to heat and scatter the insulator of the insulating film. 10. The method for forming a wiring board according to claim 9, wherein a part of one main surface is exposed.

11. The method according to claim 9, wherein when detecting the position of the one main surface, the other main surface is irradiated with infrared laser light, and reflected light from the one main surface is measured. 3. The method for forming a wiring board according to claim 1.

12. The method according to claim 1, wherein the one main surface is a wiring forming surface of the substrate, and the other main surface is a back surface of the substrate.

13. A first step of making the thickness of the support base uniform by first machining, and a second step of forming wiring and an insulating film covering the wiring on the surface of the support base having a uniform thickness. Process and

A second mechanical processing is performed to planarize the surface of the wiring and the surface of the insulating film so as to be continuously flat, thereby forming a wiring layer including the wiring and the insulating film.

3 steps,

A fourth step of forming a wiring thin film having a uniform thickness having the wiring layer by removing the support base;

A method for forming a wiring board, comprising:

14. A series of steps including the second step and the third step is performed by making the entire thickness of the support base and each of the wiring layers uniform during the planarization processing by the second mechanical processing. 14. The method for forming a wiring board according to claim 13, wherein the wiring thin film is formed by laminating a plurality of the wiring layers to form the wiring thin film having a uniform thickness.

15. The method for forming a wiring board according to claim 13, wherein the second machining is cutting using a byte.

16. The method according to claim 15, wherein, after the cutting, the byte is used to retrace the cut surface subjected to the flattening process at the same byte position as the flattening process. A method for forming a wiring board.

17. The method for forming a wiring board according to claim 13, wherein the first machining is cutting using a byte.

18. The method for forming a wiring board according to claim 13, wherein, in the fourth step, the support base is cut from the back surface using a byte, and the support base is removed.

19. The method for forming a wiring board according to claim 18, wherein the support base is made of a conductive material.

20. The method for forming a wiring board according to claim 19, wherein chips generated when the support base is cut in the fourth step are collected and used again for forming the support base. .

21. In the fourth step, after flattening the support base while leaving it at an arbitrary thickness,

21. The method of forming a wiring board according to claim 20, further comprising a fifth step of processing the support base remaining as a conductive layer into an arbitrary pattern.

2 2. Semiconductor substrate,

A semiconductor element formed on one main surface of the semiconductor substrate;

Multi-layer wiring in which each wiring is laminated in multiple layers within an insulator

A semiconductor device comprising:

The semiconductor substrate is characterized in that the other main surface is machined on the basis of the one main surface, and the other main surface is flattened and the substrate thickness is made uniform. Semiconductor device.

23. The semiconductor device according to claim 22, wherein the semiconductor substrate is controlled such that a difference between a maximum thickness and a minimum thickness is 1 m or less.

24. A substrate processing apparatus for forming wiring on a substrate to be processed,

It has a flat support surface, the substrate on which the wiring is formed on one main surface is attracted to the support surface on the other main surface, and the other main surface of the substrate is forcibly flattened. A substrate support for supporting and fixing as a reference surface,

A byte for cutting one main surface of the substrate supported and fixed on the substrate support table When

Including

A substrate processing apparatus, comprising: cutting one main surface of the substrate with the byte; and performing a flattening process so that a surface of the wiring and a surface of the insulating film are continuously flat.

25. The substrate processing apparatus according to claim 24, wherein the substrate is a semiconductor substrate.

26. The substrate processing apparatus according to claim 25, wherein the back surface of the semiconductor substrate having the semiconductor element formed on the one main surface is subjected to a flattening process.

27. Parallelizing the semiconductor substrate with reference to the other main surface, detecting the position of the one main surface, and calculating the amount of scraping from the detected one main surface. 25. The substrate processing apparatus according to claim 24, wherein the apparatus is controlled.

2 8. Equipped with laser beam irradiation means,

When detecting the position of the one main surface, the laser light irradiating means irradiates the insulating film at a plurality of locations around the one main surface with laser light to heat the insulator of the insulating film. 28. The substrate processing apparatus according to claim 27, wherein the substrate is scattered to expose a part of the one main surface.

2 9. Equipped with infrared laser light irradiation measurement means,

When detecting the position of the one main surface, the infrared laser light irradiation measuring unit irradiates the other main surface with the infrared laser light and measures reflected light from the one main surface. 29. The substrate processing apparatus according to claim 28, wherein:

30. The substrate processing apparatus according to claim 24, wherein the substrate is a supporting base.