TW201826897A - Method of manufacturing circuit board - Google Patents

Abstract

The present invention is to provide a wiring board with a higher flatness, capable of more satisfactorily performing connection with an electrode of a mounted component. A method for manufacturing a wiring board comprises: a base insulating layer forming step of forming a base insulating layer on a rear surface of a core board; a rear surface smoothing step of smoothing a surface of the base insulating layer of the rear surface by shaving the same with a bite tool or a grindstone; a groove forming step of forming a groove to serve as a circuit pattern on the base insulating layer by a laser beam or photo-etching; a metal thin film forming step of forming a metal thin film on the base insulating layer by means of sputtering or the like; a metal coating step of coating a surface of the base insulating layer with metal by a plating process, using the metal thin film as an electrode; and a circuit pattern layer forming step of forming a flat circuit pattern layer having an exposed metal circuit pattern by shaving the metal and the base insulating layer with the bite tool until the base insulating layer reaches a predetermined finish thickness.

Description

Manufacturing method of wiring board

FIELD OF THE INVENTION The present invention relates to a method for manufacturing a wiring board.

BACKGROUND OF THE INVENTION Conventionally, a technology related to a wiring board is known, which has an interposer or a redistribution layer such as a printed wiring board that assembles and mounts a semiconductor wafer or various electronic parts and ensures the conduction of these electrodes and other parts. . For example, Patent Document 1 discloses a build-up printed wiring board in which a conductive layer and an organic insulating layer are alternately stacked on a front surface and a back surface of a core substrate.

In addition, Patent Document 2 discloses a printed wiring board in which a first insulating layer formed by impregnating a resin with a reinforcing material is provided, and a core material substrate is reinforced with the first insulating layer, and a layer containing no reinforcing material is laminated. A plurality of second insulating layers. In this printed wiring board, a reinforcing material is included in the core substrate and the first insulating layer, and the thickness of the first insulating layer is made thicker than the thickness of each of the second insulating layers to prevent heat from being applied to the printed wiring board. In the case of history, warping occurs. Prior Art Literature Patent Literature

Patent Document 1: Japanese Patent Laid-Open No. 2001-196743 Patent Document 2: Japanese Patent Laid-Open No. 2013-80823

SUMMARY OF THE INVENTION The problem to be solved by the invention is that the semiconductor wafer or various electronic components mounted on a wiring board described in the above-mentioned Patent Documents 1 and 2 are continuously thinned and shortened, and the electrode pads connected to the electrodes of the wiring board are also reduced. . Therefore, when the wiring substrate is warped or uneven, the electrodes of the mounted semiconductor wafer or various electronic components cannot be well connected to the electrodes of the wiring substrate, and this causes a malfunction. As described above, although the printed wiring board described in Patent Document 2 can suppress the occurrence of warpage when a thermal history is applied, only the deformation caused by the thermal history can be suppressed, and the core substrate may be warped or not flat originally. In the case of this, there is a concern that the wiring substrate cannot be formed flat.

The present invention has been made in view of the above, and an object of the present invention is to provide a wiring board which is a wiring board with a higher flatness that enables better connection with electrodes of mounted components. Means to solve the problem

In order to solve the above-mentioned problems and achieve the object, the present invention is a method for manufacturing a wiring board having a redistribution layer on the front and back sides, and is characterized by comprising: a step of forming a base insulating layer, Resin base insulating layer; front and back flattening step, cutting and planarizing the front and back surface of the base insulating layer with a tool or a grinding stone; groove forming step, by laser light or photo etching Forming a groove that becomes a circuit pattern on the base insulating layer; a metal coating step; after the groove forming step, covering the surface of the base insulating layer with a metal; and a circuit pattern layer forming step that uses a cutter tool to cut the metal and the The base insulating layer is formed until the base insulating layer reaches a predetermined finished thickness to form a flat circuit pattern layer on which the circuit pattern of the metal is exposed. The front and back planarization steps and the circuit pattern layer forming step are used to form a flat layer. Wiring board.

Further, it is preferable that a metal thin film is coated on the surface of the base insulating layer after the trench forming step and before the metal coating step, and the metal thin film is coated with the metal on the substrate as a plating treatment. An electrode on the surface of an insulating layer.

It is also preferable that the circuit pattern layer is further laminated and formed on the circuit pattern layer. Invention effect

In the method of manufacturing a wiring substrate of the present invention, the base insulating layer formed on both the front side and the back side of the substrate serving as the core material is planarized. As a result, even if the core material substrate itself is warped or the surface of the substrate has unevenness, it is possible to form the surface of the underlying insulating layer that will become the circuit pattern layer flat later. In addition, since the metal covered on the base insulating layer and the base insulating layer are cut together to form a circuit pattern layer with the exposed circuit pattern, the surface of the circuit pattern layer can be formed more flatly. Therefore, according to the method for manufacturing a wiring board according to this embodiment, it is possible to obtain a wiring board with a higher flatness, which can better connect with the electrodes of the mounted components.

Embodiments for Implementing the Invention Embodiments (embodiments) for implementing the invention will be described in more detail with reference to the drawings. The present invention is not limited by the contents described in the following embodiments. In addition, the constituent elements described below include things that can be easily conceived by a person having ordinary knowledge in the technical field or substantially the same. In addition, the structures described below can be appropriately combined. Moreover, various structures can be omitted, replaced, or changed without departing from the gist of the present invention.

A method for manufacturing a wiring board according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a wiring substrate manufactured by a wiring substrate manufacturing method according to an embodiment. The wiring board 1 shown in FIG. 1 is a wiring board having an interposer or a rewiring layer such as a printed wiring board that assembles and mounts a semiconductor wafer or various motor parts and ensures conduction between these electrodes and other parts. In the present embodiment, the wiring substrate 1 is an interposer that mounts a semiconductor wafer and is connected to a printed wiring substrate, and connects an electrode of the semiconductor wafer and a wiring pattern of the printed wiring substrate according to a preset pattern. As shown in FIG. 1, the wiring substrate 1 includes a core material substrate 10 serving as a core material, and a circuit pattern layer 20 as a rewiring layer formed on both the front surface 10 a and the back surface 10 b of the core material substrate 10.

The core substrate 10 is an insulating (non-conductive) substrate formed of, for example, glass epoxy resin, ceramic, glass, or the like. The thickness of the core substrate 10 is, for example, about 50 μm. In this embodiment, as shown in FIG. 1, the core material substrate 10 is bent on the back surface 10 b side (lower side in the figure) to form a convex shape. In addition, in the drawings described below including FIG. 1, in order to explain the case where the core material substrate 10 is bent, it is described that the degree of bending caused by the core material substrate 10 is greater.

The circuit pattern layer 20 includes a first circuit pattern layer 21 formed on the front surface 10 a and a back surface 10 b of the core substrate 10, a second circuit pattern layer 22 formed on the first circuit pattern layer 21, and a second circuit. The third circuit pattern layer 23 on the pattern layer 22. The circuit pattern layer 20 may be formed on the core substrate 10 at least one layer, and may be formed in four or more layers.

The first circuit pattern layer 21 has an insulating base insulating layer 21a and a plurality of circuit patterns 21b as electrode circuits embedded in the base insulating layer 21a. The second circuit pattern layer 22 includes an insulating base insulating layer 22 a and a plurality of circuit patterns 22 b as electrode circuits embedded in the base insulating layer 22 a. The third circuit pattern layer 23 has an insulating base insulating layer 23a and a plurality of circuit patterns 23b as electrode circuits embedded in the base insulating layer 23a.

The base insulating layers 21a, 22a, and 23a are dry film-type interlayer insulating materials including a resin material, and an Ajinomoto Fine-Techo Co., Ltd. build-up film (hereinafter referred to as a build-up film) is used. "ABF"). In this embodiment, although the base insulating layers 21a, 22a, and 23a are made of ABF, the materials constituting the base insulating layers 21a, 22a, and 23a are not limited to ABF. The base insulating layers 21a, 22a, and 23a insulate adjacent circuit patterns 21b, 22b, and 23b from each other in each circuit pattern layer 20, and insulate circuit patterns 21b, 22b, and 23b between each circuit pattern layer 20. The thickness of the base insulating layers 21a, 22a, and 23a is, for example, about 40 μm.

Each of the circuit patterns 21b, 22b, and 23b is formed of a metal such as copper. The height of each of the circuit patterns 21b, 22b, and 23b (the height in the lamination direction of the circuit pattern layer) is, for example, about 15 μm to 20 μm. As shown in FIG. 1, each of the circuit patterns 21b, 22b, and 23b is electrically connected at a predetermined position. The circuit pattern 23 b of the third circuit pattern layer 23 located at the outermost layer is exposed outside the wiring substrate 1. The circuit pattern 23b exposed on the outside of the wiring substrate 1 is a circuit pattern of an electrode connected to a semiconductor wafer or a wiring pattern of a printed wiring substrate. The wiring substrate 1 includes a through electrode that penetrates the core substrate 10 from the front surface 10 a to the back surface 10 b and is connected to the circuit pattern layer 20. The wiring substrate 1 is a wiring pattern in which a circuit pattern 23b exposed on the outside of the wiring substrate 1 is connected to an electrode of a semiconductor wafer or a printed wiring substrate, and the circuit patterns 21b, 22b, and 23b of each circuit pattern layer 20 are defined with each other. The electrodes are electrically connected at positions to electrically connect the electrodes of the semiconductor wafer and the wiring pattern of the printed wiring board according to a preset pattern.

Next, a method for manufacturing a wiring board according to an embodiment will be described. FIG. 2 is a flowchart showing a processing procedure for forming each circuit pattern layer as part of a flow of a method for manufacturing a wiring substrate according to an embodiment. As shown in FIG. 2, the method for manufacturing a wiring substrate according to the embodiment includes a base insulating layer forming step ST1, a front and back planarization step ST2, a groove forming step ST3, a metal thin film forming step ST4, a metal coating step ST5, and a circuit pattern layer. Forming step ST6. The wiring substrate 1 is formed by laminating and forming the first circuit pattern layer 21, the second circuit pattern layer 22, and the third circuit pattern layer 23 by repeatedly performing the processing shown in FIG. 2. Hereinafter, with reference to the case where the first circuit pattern layer 21 is formed on the core substrate 10 as an example, the formation order of each circuit pattern layer will be described with reference to the drawings.

FIG. 3 is an explanatory diagram showing the core substrate 10 on which the base insulating layer 21a is formed in the base insulating layer forming step ST1; FIG. 4 is a view showing flattening the surface of the base insulating layer 21a in the front and back planarization step ST2. FIG. 5 is an explanatory diagram showing another example of a case where the surface of the base insulating layer 21a is flattened in the front-back planarization step ST2; FIG. 6 is a view showing the base insulating layer 21a has been flattened An explanatory diagram of the core substrate 10; FIG. 7 is an explanatory diagram showing a case where a plurality of grooves R are formed on the surface of the base insulating layer 21a in the groove forming step ST3; FIG. 9 is an explanatory view showing a core material substrate 10 coated with a metal M on a base insulating layer 21a by a metal coating step ST5; FIG. 9 is an explanatory view showing a core material substrate 10 with a metal thin film 21c formed on a surface of the insulating layer 21a; 10 is an explanatory diagram showing a situation where the metal M and a part of the base insulating layer 21a are cut in the circuit pattern layer forming step ST6. FIG. 11 is an explanatory diagram showing the core material substrate 10 on which the first circuit pattern layer 21 has been formed.

The base insulating layer forming step ST1 is a step of forming a base insulating layer 21 a on the front surface 10 a and the back surface 10 b of the core substrate 10. In the base insulating layer forming step ST1, as shown in FIG. 3, ABF manufactured by Ajinomoto Fine-Techo Co., Ltd. is fixed to both the front surface 10a and the back surface 10b of the core substrate 10 by thermal compression bonding or the like. At this time, the core material substrate 10 of this embodiment is bent to a convex shape on the back surface 10b side (lower side in the figure), and as shown in FIG. 3, the front material 10a and the back surface 10b of the core material substrate 10 are fixed. The surface 211 a of the base insulating layer 21 a opposite to the core material substrate 10 is also bent in accordance with the shape of the core material substrate 10.

The front and back planarization step ST2 is a step of cutting and planarizing the surface 211 a of the base insulating layer 21 a formed on the front surface 10 a and the back surface 10 b of the core substrate 10 with the tool 31. In the front and back planarization step ST2, as shown in FIG. 4, the base insulating layer 21a on one of the front surface 10a and the back surface 10b of the core substrate 10 is attracted and held on the tool cutting device 30 and has a pin made of metal. On the work clamp 32 of the holding surface 32a formed by a pin chuck or the like. Then, the cutter wheel 33 of the cutter cutting device 30 is rotated, the cutter wheel 33 is moved in the lower direction in the figure by a moving mechanism (not shown), and the cutter tool 31 and the work clamp 32 are aligned in a direction parallel to the holding surface 32a. The relative movement is performed to planarize the surface 211a of the base insulating layer 21a by the cutting tool 31. Next, the base insulating layer 21a on the other side of the front surface 10a and the back surface 10b of the core substrate 10 is sucked and held on the work clamp 32, and the surface 211a of the base insulating layer 21a on one side is similarly cut by the tool 31. For flattening. Thereby, as shown in FIG. 6, the surface of the base insulating layer 21a on both the front surface 10a side and the back surface 10b side of the core substrate 10 can be formed flat. In the front-back planarization step ST2, a protective member such as an adhesive tape may be attached to the surface of the base insulating layer 21a that is attracted and held on the side of the work table 31.

In the example shown in FIG. 4, although the surface 211 a of the base insulating layer 21 a is cut and flattened by the tool tool 31 of the tool cutting device 30, the front and back planarization step ST2 can also be performed as shown in FIG. 5. The surface 211 a of the base insulating layer 21 a is ground and flattened by the grinding stone 51 of the grinding device 50. In the case where the surface 211a of the base insulating layer 21a is cut and flattened by the grinding stone 51 of the grinding device 50, the base insulating layer 21a is attracted and held on a work clamp having a holding surface 52a of the grinding device 50 While rotating the work clamp table 52 while the grinding stone 51 of the grinding device 50 is in contact with the base insulating layer 21a on the table 52, the grinding wheel 53 is rotated while the grinding wheel 51 is being rotated. The surface 211a of the base insulating layer 21a is cut to be planarized. Furthermore, even in the case where the polishing device 50 is used in the front-back planarization step ST2, a protective member such as an adhesive tape can be attached to the surface of the base insulating layer 21a attracted and held on the side of the work clamp table 52. on.

In addition, after the front-back planarization step ST2 when forming the first circuit pattern layer 21 is performed, in order to form a through-electrode (not shown) on the wiring substrate 1, laser light is used for the core substrate 10 and the base insulating layer 21a. The ablation process is performed to form through holes (not shown) through the base insulating layer 21a of the core material substrate 10 itself and both the front surface 10a side and the back surface 10b side of the core material substrate 10. The ablation process may be performed in a groove formation step ST3 described later.

The trench forming step ST3 is a step of forming a trench R that becomes a circuit pattern 21b in the base insulating layer 21a by laser light. In the groove forming step ST3, the base insulating layer 21a on one of the front surface 10a side and the back surface 10b side of the core substrate 10 is sucked and held in the laser processing device 40 and is formed of porous ceramics or the like. It is on the work clamp 41 of the holding surface 41a. Then, as shown in FIG. 7, the laser light irradiating section 42 irradiates laser light L such as excimer laser light toward a predetermined range of the base insulating layer 21 a in accordance with a preset pattern so that the surface of the base insulating layer 21 a is irradiated. 211a forms a plurality of grooves R. As described above, by irradiating the laser light L to a predetermined range of the base insulating layer 21a, the plurality of grooves R can be formed more efficiently. In addition, by using laser processing, a plurality of strips can be formed at a low cost compared with the case where the base insulating layer 21a is formed of a resin material that can be photoetched and the grooves R are formed by photoetching, for example. Ditch R. Next, the base insulating layer 21a on the other side of the front surface 10a and the back surface 10b of the core substrate 10 is attracted and held on the work clamp 41, and the laser light L is similarly irradiated on the surface of the base insulating layer 21a on one side. 211a to form a plurality of grooves R. Furthermore, even in the groove formation step ST3, a protective member such as an adhesive tape may be attached to the surface of the base insulating layer 21a that is attracted and held on the side of the work table 41.

The metal thin film forming step ST4 is a step of forming a metal thin film 21c on the surface of the base insulating layer 21a. In the metal thin film forming step ST4, the metal thin film 21c made of a conductive metal is sputtered on the base insulating layer 21a on both the front surface 10a side and the back surface 10b side of the core substrate 10 by sputtering. In order to form a coating film. Thereby, as shown in FIG. 8, the metal thin film 21 c may be formed on the entire surface 211 a of the base insulating layer 21 a on both the front surface 10 a side and the back surface 10 b side of the core substrate 10 including the plurality of grooves R. At this time, a metal thin film 21c is also formed on the inner surface of a through-hole for a through-electrode (not shown). In addition, the metal thin film 21c may be configured such that solder or the like formed of a metal material is formed on the base insulating layer 21c by screen printing or inkjet printing.

The metal coating step ST5 is a step in which the metal thin film 21c is used as an electrode, and the metal M is coated on the surface 211a of the base insulating layer 21a by a plating process. In the metal coating step ST5, the metal thin film 21c is used as an electrode in the solution, and the conductive metal M is electrodeposited on the surface 211a of the base insulating layer 21a. The metal thin film 21c and the inner surface of a through hole (not shown) On the metal thin film 21c, as shown in FIG. 9, a metal M is filled in the groove R. At this time, the through holes for through electrodes (not shown) are also filled with metal M. In the metal coating step ST5, the base insulating layer 21a on both the front surface 10a side and the back surface 10b side of the core substrate 10 is sequentially or simultaneously subjected to plating treatment. As a result, as shown in FIG. 9, on both the front surface 10 a side and the back surface 10 b side of the core substrate 10, the inside of the plurality of grooves R may be covered with the metal M on the surface 211 a of the base insulating layer 21 a.

The circuit pattern layer forming step ST6 is performed by cutting the metal M and the base insulating layer 21a with the tool 31 until the base insulating layer 21a reaches a predetermined finished thickness to form a flat first circuit pattern layer 21 exposed by the metal circuit pattern 21b. step. In the circuit pattern layer forming step ST6, as shown in FIG. 10, the surface of the metal M coated on the base insulating layer 21a on one of the front surface 10a and the back surface 10b of the core substrate 10 is attracted and held by the cutting tool. The device 30 has a work chuck 32 having a holding surface 32a formed by a metal pin chuck or the like. Then, the cutter wheel 33 of the cutter cutting device 30 is rotated, while the cutter wheel 33 and the work table 32 are relatively moved in a parallel direction with respect to the holding surface 32a, the metal M is cut by the cutter tool 31. At this time, the metal M is cut by including the surface layer portion of the base insulating layer 21a. Next, the surface of the metal M coated on the base insulating layer 21 a on the other side of the front surface 10 a and the back surface 10 b of the core material substrate 10 is sucked and held on the work clamp 32. Then, the metal M coated on one side of the base insulating layer 21a is cut by the tool 31 in the same manner. In addition, even in the circuit pattern layer forming step ST6, a protective member such as an adhesive tape may be attached to the surface of the metal M covered with the base insulating layer 21a that is attracted and held on the work clamp 32 side.

Thereby, as shown in FIG. 11, the metal M and the metal thin film 21 c are removed from the surface of the base insulating layer 21 a except for the inside of the plurality of grooves R on both the front surface 10 a side and the back surface 10 b side of the core substrate 10. . The metal M and the metal thin film 21c remaining in the plurality of grooves R become a circuit pattern 21b embedded in the base insulating layer 21a, and are exposed on the surface 211a of the base insulating layer 21a. The metal M and the metal thin film 21c remaining in the through-hole for a through-electrode (not shown) serve as a circuit pattern for the through-electrode, and are exposed on the surface 211a of the base insulating layer 21a. Moreover, the surface 211a of the base insulating layer 21a and the exposed surface 211b of the circuit pattern 21b can be formed flat (flush). That is, the first circuit pattern layer 21 can be formed flat. In addition, the cutting amount of the surface layer portion of the base insulating layer 21a can be obtained by removing the metal M and the metal thin film 21c from the surface 211a of the base insulating layer 21a except the inside of the plurality of grooves R, and removing the first circuit pattern layer 21 It is sufficient to form it flat, and it is ideal that as little as possible is better. This makes it possible to suppress the occurrence of abrasion or chipping on the tool 31 of the tool cutting device 30 due to the silica filler contained in the ABF, or on the exposed surface 211b of the circuit pattern 21b. A crack (smear) is generated. In addition, in the circuit pattern layer forming step ST6, similarly to the front and back planarization step ST2, the metal M and the base insulating layer 21a are cut to the base by using the grinding device 50 shown in FIG. 5 and the grinding stone 51. A step of forming a flat first circuit pattern layer 21 with the metal circuit pattern 21b exposed until the insulating layer 21a reaches a predetermined finished thickness.

After the first circuit pattern layer 21 is formed in the above-mentioned order, the processes from the base insulating layer step ST1 to the circuit pattern layer forming step ST6 are repeatedly performed again. That is, the ABF is fixed on the first circuit pattern layer 21 to form a base insulating layer 22a (base insulating layer forming step ST1), and the base insulating layer 22a is flattened using the cutter cutting device 30 (front and back flattening step ST2) . Next, a plurality of trenches R are formed in the base insulating layer 22a using the laser processing apparatus 40 (trench formation step ST3). Then, a metal thin film is formed on the base insulating layer 22a by sputtering or the like (metal thin film forming step ST4), and the metal M is coated on the surface of the base insulating layer 22a by using a metal thin film as an electrode by a plating process (metal coating). Step ST5). In addition, using the cutter cutting device 30, the metal M and the surface layer portion of the base insulating layer 22a are cut together with a cutter tool (or grinding stone 51) 31 to form a flat second circuit pattern with the second circuit pattern 22b exposed. Layer 22 (circuit pattern layer forming step ST6). Thereby, a flat second circuit pattern layer 22 can be formed on the flat first circuit pattern layer 21. In addition, a flat third circuit pattern layer 23 can be formed on the flat second circuit pattern layer 22 by the same procedure. As a result, the wiring substrate 1 having the flat circuit pattern layer 20 shown in FIG. 1 can be formed.

In addition, it includes a case where circuit patterns for through electrodes (not shown) are connected to each other, and when the circuit patterns are electrically connected to each other between the circuit pattern layers 20, in the processing sequence shown in FIG. In the forming step ST3, a trench R is formed where the circuit pattern reaching the lower layer side is exposed at the base insulating layer. Thereby, a metal thin film can be formed on the exposed surface of the circuit pattern on the lower layer side in the metal thin film forming step ST4, and the metal M can be filled in the groove R in the metal coating step ST5. In addition, a circuit pattern connected to the circuit pattern on the lower layer side can be formed in the circuit pattern layer forming step ST6. In the outermost layer of the wiring board 1, only the so-called electrode pad portion is exposed on the surface among the circuit patterns. The electrode pad portion is a portion for electrically connecting the wiring substrate 1 and a semiconductor wafer mounted on the wiring substrate 1 or another wiring substrate connected to the wiring substrate 1.

As described above, in the method of manufacturing a wiring substrate according to this embodiment, the base insulating layer 21a formed on the front surface 10a and the back surface 10b of the core substrate 10 is planarized (front surface back surface planarization step ST2). As a result, even if the core material substrate 10 itself is warped (bent) like the core material substrate 10 of the present embodiment, or the front surface 10a or the back surface 10b of the core material substrate 10 has unevenness, it can be a circuit pattern layer 21 later. The surface of the base insulating layer 21a is formed flat. In addition, since the metal M coated on the base insulating layer 21a is cut out together with the base insulating layer 21a to form the first circuit pattern layer 21 exposed by the circuit pattern 21b, the first circuit pattern layer 21 can be The surface is formed more flatly. Therefore, according to the method for manufacturing a wiring board according to this embodiment, it is possible to obtain a wiring board 1 having a higher flatness, which enables better connection with the electrodes of the mounted components.

Further, after the trench forming step ST3 and before the metal coating step ST5, the surface of the base insulating layer 21a is coated with a metal thin film 21c (metal thin film forming step ST4), and the metal thin film 21c is subjected to a plating treatment to the metal M An electrode when covering the surface of the base insulating layer 21a. Thereby, the metal M which becomes the circuit pattern 21b can be easily covered on the base insulating layer 21a.

Furthermore, the circuit pattern layer is further laminated on the circuit pattern layer to form a circuit pattern layer. That is, the processing sequence shown in FIG. 2 is repeatedly implemented to laminate and form a flat second circuit pattern layer 22 on the flat first circuit pattern layer 21, and on the flat second circuit pattern layer 22 A flat third circuit pattern layer 23 is laminated and formed. This makes it possible to satisfactorily suppress a decrease in flatness each time each layer is laminated. Accordingly, it is possible to more securely ensure the flatness of the third circuit pattern layer 23 located at the outermost layer, and to better connect the electrodes of the wiring substrate 1 and the electrodes of the components mounted on the wiring substrate 1. That is, the present invention is very suitable for manufacturing a multilayer wiring type wiring substrate such as the wiring substrate 1. In addition, by planarizing the surfaces of the circuit patterns 21b, 22b, and 23b, the interlayer distance (electrode height) of the circuit patterns 21b, 22b, and 23b can be fixed. As a result, it becomes possible to set the value of the resistance or the communication speed in each of the circuit patterns 21b, 22b, and 23b to be fixed.

In this embodiment, although the ABF made by Ajinomoto Fine-Techo is used to form the base insulating layers 21a, 22a, and 23a in the base insulating layer forming step ST1, and in the trench forming step ST3, The base insulating layers 21a, 22a, and 23a are irradiated with laser light to form a plurality of grooves R, but the formation method of the base insulating layers 21a, 22a, 23a and the plurality of grooves R is not limited to this. FIG. 12 is an explanatory diagram showing a state in which a groove formation step ST3 according to a modification is implemented.

The base insulating layer 21a formed on the core substrate 10 shown in FIG. 12 includes a photosensitive resin material that can be pattern-removed by photolithography (photolithography). For example, as the base insulating layer 21a, a dry film containing a photosensitive resin material is used, and in the base insulating layer forming step ST1, the dry film is fixed to the front surface 10a and the back surface 10b of the core substrate 10 by thermal compression bonding. . In addition, as the base insulating layer 21a, for example, a liquid resin having photosensitivity is used, and in the base insulating layer forming step ST1, the liquid resin is dropped onto the front surface of the core substrate 10 by a spin coat. 10a and the back surface 10b may be fixed by heating. The same applies when the base insulating layer 22 a of the second circuit pattern layer 22 and the base insulating layer 23 a of the third circuit pattern layer 23 are formed.

In the groove forming step ST3 of the modification shown in FIG. 12, as shown by the solid line arrows in the figure, the mask 60 having a pattern P along the plurality of grooves R formed in advance is transmitted for a predetermined period of time. The base insulating layer 21a is irradiated with light. Thereby, a part of the surface side of the exposed position of the base insulating layer 21a can be pattern-removed along the pattern P of the mask 60, and a plurality of grooves R can be formed in the base insulating layer 21a. In addition, in the case of performing photo-etching (lithography) to remove the pattern of the exposed position of the base insulating layer 21a, the pattern P of the mask 60 may be formed along a plurality of grooves R first. The shape of the other parts. The same applies when a plurality of grooves R are formed in the base insulating layer 22 a of the second circuit pattern layer 22 and the base insulating layer 23 a of the third circuit pattern layer 23.

In this manner, the base insulating layer 21a (22a, 23a) is formed by using a photosensitive resin material that can be pattern-removed by photoetching (lithography) without using ABF, and it becomes possible to suppress the circuit pattern layer. In the forming step ST6, abrasion or cracking of the cutting tool 31 or cracking of the surface of the circuit pattern 21b may be caused by cutting the ABF containing silicon dioxide filler.

Furthermore, in this embodiment, although the circuit pattern layer 20 is formed on both the front surface 10a and the back surface 10b of the core substrate 10, the present invention can also be applied to only one surface of the core substrate 10 The circuit pattern layer 20 is formed thereon.

1‧‧‧wiring board

10‧‧‧ core substrate

10a‧‧‧front

10b‧‧‧ back

20‧‧‧Circuit pattern layer

21‧‧‧The first circuit pattern layer

21a, 22a, 23a ‧‧‧ base insulating layer

211a‧‧‧ surface

211b‧‧‧ exposed

21b, 22b, 23b‧‧‧Circuit patterns

21c‧‧‧Metal film

22‧‧‧ 2nd circuit pattern layer

23‧‧‧3rd circuit pattern layer

30‧‧‧ Tool cutting device

31‧‧‧Tools

32, 41, 52‧‧‧ work clamps

32a, 41a, 52a‧‧‧

33‧‧‧Cutter wheel

40‧‧‧laser processing device

42‧‧‧Laser light irradiation section

50‧‧‧Grinding device

51‧‧‧grinding stone

53‧‧‧Grinding wheel

60‧‧‧Mask

L‧‧‧ laser light

M‧‧‧ Metal

P‧‧‧Pattern

R‧‧‧ trench

ST1 ~ ST6‧‧‧‧steps

FIG. 1 is a cross-sectional view showing a wiring substrate manufactured by a wiring substrate manufacturing method according to an embodiment. FIG. 2 is a flowchart showing a processing procedure for forming each circuit pattern layer as part of a flow of a method for manufacturing a wiring substrate according to an embodiment. FIG. 3 is an explanatory view showing a core substrate having a base insulating layer formed in a base insulating layer forming step. FIG. 4 is an explanatory view showing a state where the surface of the base insulating layer is flattened in the front-back planarization step. FIG. 5 is an explanatory diagram showing another example of a case where the surface of the base insulating layer is planarized in the front-back planarization step. FIG. 6 is an explanatory view showing a core material substrate having a planarized base insulating layer. FIG. 7 is an explanatory view showing a state where a plurality of grooves are formed on the surface of the base insulating layer in the groove forming step. FIG. 8 is an explanatory diagram showing a core material substrate having a metal thin film formed on a surface of a base insulating layer by a metal thin film forming step. FIG. 9 is an explanatory diagram showing a core material substrate coated with a metal on a base insulating layer by a metal coating step. FIG. 10 is an explanatory diagram showing a state where a part of a metal and a base insulating layer is cut in a circuit pattern layer forming step. FIG. 11 is an explanatory view showing a core material substrate on which a first circuit pattern layer has been formed. FIG. 12 is an explanatory diagram showing a state in which a groove formation step according to a modification is performed.

Claims (3)

A method for manufacturing a wiring board is a method for manufacturing a wiring board having a redistribution layer on the front and back sides, comprising: a base insulating layer forming step of forming a resin base insulating layer on the front and back sides of a substrate that becomes a core material ; Front and back flattening step, cutting and flattening the surface of the base insulating layer on the front and back with a cutter tool or a grinding stone; groove forming step, forming the base insulating layer by laser light or photoetching A groove forming a circuit pattern is formed thereon; a metal coating step, after the groove forming step, covering the surface of the base insulating layer with metal; and a circuit pattern layer forming step, cutting the metal and the base insulating layer with a cutter tool until the Until the base insulating layer reaches a predetermined finished thickness, a flat circuit pattern layer exposed by the circuit pattern of the metal is formed, and a flat wiring substrate is formed by the front and back planarization step and the circuit pattern layer forming step. The method of manufacturing a wiring substrate according to claim 1, wherein the surface of the base insulating layer is coated with a metal thin film after the groove forming step and before the metal coating step, and the metal thin film is treated by plating. An electrode when the metal covers the surface of the base insulating layer. The method for manufacturing a wiring substrate according to claim 1 or 2, wherein the circuit pattern layer is further laminated and formed on the circuit pattern layer.