CN100547741C - The formation method and the lining processor of semiconductor device, wiring substrate - Google Patents
The formation method and the lining processor of semiconductor device, wiring substrate Download PDFInfo
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- CN100547741C CN100547741C CNB2003801022826A CN200380102282A CN100547741C CN 100547741 C CN100547741 C CN 100547741C CN B2003801022826 A CNB2003801022826 A CN B2003801022826A CN 200380102282 A CN200380102282 A CN 200380102282A CN 100547741 C CN100547741 C CN 100547741C
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Abstract
Prepare to have made bearing-surface (201a) smooth substrate holder (201), with for example vacuum suction the formation face of wiring (1a) is adsorbed on this bearing-surface (201a), thereby Semiconductor substrate (1) is fixed on the substrate holder (201).At this moment, just make the enforceable planarization of wiring formation face (1a) to the absorption of bearing-surface (201a), like this, wiring formation face (1a) becomes the planarization datum level at the back side (1b).Under this state, (1b) carries out mechanical lapping to the back side, protuberance (12) grinding of the back side (1b) removed carry out planarization.Like this, just can make the discrete homogenization of thickness of substrate (particularly Semiconductor substrate), unsuitable situations such as concavo-convex distortion can not take place, can be easily and realize the high speed planarization that no wires design retrains at an easy rate.
Description
Technical field
The present invention relates to substrate, particularly electronic devices such as LSI with multilayer wiring be formed on method on the Semiconductor substrate, after forming multiple wiring layer on the support base that constitutes by metal material or insulating material, remove support base again and form the method for wiring multilayer film, semiconductor device and lining processor with multilayer wiring.
Background technology
Recently, the further miniaturization of semiconductor device, highly integrated demand are gradually high, just must make the wiring multiple stratification thereupon, therefore, need the high planarization technology.Mainly be to be suitable this planarization of Semiconductor substrate of representative with the silicon wafer, in addition, for example having of receiving much attention recently in addition is applicable to SiP (Siliconin Package: membranaceous multilayer wiring film encapsulation silicon).
In the past, as making the insulating barrier that is formed on the silicon semiconductor substrate or the method for wiring layer planarization, mainly adopted CMP (Chemical Mechanical Polishing:CMP) method.This method is to be pre-formed more smooth insulating barrier that becomes machined surface or wiring layer, gives as security and goes up smooth abrasive sheet, with mill base slurry (chemical grinding material) the meticulous smooth processing of chemical-mechanical is carried out on the surface.The hard insulating material face or the metal material face that set in advance constitute stop layer, finish CMP.CMP is TTV (the Total Thickness Variation: a kind of method total thickness variations) that does not depend on that the difference by the maximum ga(u)ge of the discrete or Semiconductor substrate of the thickness of Semiconductor substrate and minimum thickness defines.
Except that the CMP method, also propose to have several methods of for example using cutting tools to carry out planarization (for example with reference to patent documentation 1,2,3,4).But these methods all are the methods at the planarization of the sog film of the regional area on the LSI, and are the same with CMP, all are to be the benchmark cutting process to be cut face, do not depend on the TTV of Semiconductor substrate.
On the other hand, in order to form cheaply and easy, consider realizing only using the film wiring layer as interposer on the desired installation substrate of SiP.In the past, as the thin film multilayer wiring substrate of no through hole, developed a kind of preparation and on a resin molding, formed the multi-disc wiring substrate that is filled with conduction support holes of solder flux and wiring, in last operation, they substrates stacked together.Though this wiring substrate cost is very low, the support holes diameter is about 120 μ m～200 μ m, L/S (live width/at interval) is about about 100 μ m/100 μ m～200 μ m/200 μ m about, be difficult to do finely.Therefore, in order to realize miniaturization and low cost simultaneously, effective method is being formed on that multilayer wiring film on the substrate separates and as substrate.
If adopt the CMP method, though can realize exquisite planarization, processing unit (plant) costliness, productivity ratio are also low, are the high technology of manufacturing cost.Metal and insulant to copper and so on carries out under the situation of planarization at the same time, the hollow of " dishing " might occur being referred to as in the sparse part of figure.From the angle of the generation necessity of avoiding this dishing, because the size of the wiring figure in the LSI etc. is defined, so it will be disposed to such an extent that do not form the blank parts of figure.
On the other hand, when forming above-mentioned multilayer wiring film, must at first on support base, form the multilayer wiring film, again support substrate be peeled off or removed.A kind of method of peeling off is to utilize the insulating resin and the low characteristic of the tack between the support base of multilayer wiring film, only the peripheral part at substrate applies the good material of tack, after wiring layer forms end, the part of the material that the coating tack is good is opened with the part cutting of uncoated, and then the multilayer wiring film is separated from support base.We can say that this method of peeling off is the damage that is pulled away to film, probably has injury to circuit.In addition, the method for removing support base is, for example under the situation of support base as Semiconductor substrate, by grinding and corroding its method of removing.At the metal with aluminium or copper and so on is under the situation of support base, and it is eroded.
No matter which kind of method of employing, support base itself all will count cost, in addition, with the latter's method with under the situation of support base as Semiconductor substrate, because the residue former state of grind becomes rubbish,, the baneful influence of environment be can not be ignored so the rubbish that produces in handling is a lot.
Summary of the invention
In view of the above-mentioned problems, the object of the present invention is to provide a kind of formation method, semiconductor device and lining processor of the substrate that connects up.The formation method of this wiring substrate is considered the representational CMP main object of machining process conduct in addition as flattening method, make the discrete homogenization of thickness of substrate (particularly Semiconductor substrate or conductor, dielectric substrate), do not produce disadvantages such as dishing, thereby realize the high speed planarization of no wires design constraint easily and at an easy rate.In the end remove substrate and obtain under the situation of monomer multilayer wiring film, constitute the accurate control of thickness of each wiring layer of multilayer wiring film easily, simultaneously can remove copper coin easily in high-efficiency and low-cost ground, and realize having the wiring film of fine wire structures.
The formation method of wiring substrate of the present invention is that wiring is formed on method on the substrate, this method comprises following operation: the described wiring formation face with described substrate is a benchmark, the back side of described wiring formation face is carried out the operation of planarization by first machining; On described wiring formation face, form described wiring and cover the operation of the dielectric film of described wiring; With the described back side is benchmark, carries out planarization by second machining, so that the surface of the surface of described wiring and described dielectric film becomes the operation of continuous tabular surface.
The formation method of wiring substrate of the present invention comprises following operation: the operation that makes the thickness homogeneous of support base by first machining; On the surface of the described support base that thickness is crossed by homogeneous, form described wiring and cover the operation of the dielectric film of described wiring; Carry out planarization by second machining,, form the operation of the wiring layer that constitutes by described wiring and described dielectric film so that the surface of the surface of described wiring and described dielectric film becomes the operation of continuous tabular surface; Remove described support base, thereby form the operation of the wiring film of thickness homogeneous with described wiring layer.
Semiconductor device of the present invention includes Semiconductor substrate, be formed on semiconductor element on the described semiconductor substrate surface, in insulant, be the multilayer wiring that multilayer constitutes with described semiconductor element lamination; It is the machining of benchmark that the rear side on the described surface that the described semiconductor element of the formation of described Semiconductor substrate is formed is implemented with described surface, makes the smooth and substrate thickness homogeneous in the described back side.
Lining processor of the present invention is the lining processor when forming wiring on substrate, comprises substrate holder and planing tool; Substrate holder has smooth bearing-surface, and with the one side of substrate it is adsorbed on the described bearing-surface, the described one side of substrate is supported as datum level secure the above substrate by force; Planing tool is used for carrying out cut to being supported the another side that is fixed on the described substrate on the described substrate holder; With described planing tool the described wiring formation face of described substrate is carried out cut, and implements planarization, so that the surface of described wiring and dielectric film is surperficial continuous and smooth.
In addition, the invention provides a kind of formation method of the substrate that connects up, on an interarea of processed substrate, form wiring, it is characterized in that, comprise following operation: first operation, pass through vacuum suction, make an interarea of the described substrate that should form described wiring become smooth state forcibly, an interarea with described substrate under this state is a benchmark, another interarea to described substrate is implemented first machining, another interarea planarization with described substrate, second operation on an interarea of described substrate, forms described wiring and covers the dielectric film of described wiring, the 3rd operation, another interarea with described substrate is a benchmark, and an interarea of described substrate is implemented second machining, makes an interarea planarization of described substrate, so that the surface of described wiring and described dielectric film is surperficial continuous and smooth, described second machining is to use the cut of planing tool.
In addition, the invention provides a kind of formation method of the substrate that connects up, it is characterized in that, comprise following operation: first operation, pass through vacuum suction, make the surface of support base become smooth state forcibly, under this state, be benchmark with described surface, make the back side planarization of described support base by first machining, and make the thickness homogenization of support base, second operation, thickness by homogenization described surface on, form wiring and cover the dielectric film of described wiring, the 3rd operation, carry out planarization with second machining, make the surperficial continuous and smooth of the surface of described wiring and described dielectric film, form the wiring layer that constitutes by described wiring and described dielectric film, the 4th operation, remove described support base, form the wiring film of the thickness homogeneous with described wiring layer thus, described second machining is to use the cut of planing tool.
Description of drawings
Figure 1A～Fig. 1 E is the broad cross-section map of formation method of representing the multilayer wiring substrate of present embodiment by process sequence.
Fig. 2 A～Fig. 2 C is the broad cross-section map of formation method of representing the multilayer wiring substrate of first embodiment by process sequence.
Fig. 3 A～Fig. 3 C is the broad cross-section map of formation method of representing the multilayer wiring substrate of first embodiment by process sequence.
Fig. 4 A～Fig. 4 C is the broad cross-section map of formation method of representing the multilayer wiring substrate of first embodiment by process sequence.
Fig. 5 is the schematic diagram of concrete example of each planarization operation of Fig. 2 A, Fig. 3 A and Fig. 4 B.
Fig. 6 is the schematic diagram of other concrete example of each planarization operation of Fig. 2 A, Fig. 3 A and Fig. 4 B.
Fig. 7 is the broad cross-section map of the comparative example of first embodiment.
Fig. 8 A, Fig. 8 B are the pie graphs of abrasive working appts.
Fig. 9 is the formation block diagram of abrasive working appts.
Figure 10 A～Figure 10 G is the summary pie graph of the formation of expression cutting apparatus.
Figure 11 is the summary pie graph that the configuration of the each several part of expression cutting apparatus constitutes.
Figure 12 is the flow chart of cutting technology.
Figure 13 is the outward appearance approximate three-dimensional map that expression is suitable for semiconductor device of the present invention.
Figure 14 is the general view that expression is suitable for the outward appearance of the semiconductor device that present embodiment of the present invention shows.
Figure 15 A～Figure 15 D is the broad cross-section map of manufacture method of semiconductor device of representing to comprise the multilayer wiring substrate of second embodiment by process sequence.
Figure 16 A～Figure 16 C is the broad cross-section map of manufacture method of semiconductor device of representing to comprise the multilayer wiring substrate of second embodiment by process sequence.
Figure 17 A～Figure 17 C is the broad cross-section map of manufacture method of semiconductor device of representing to comprise the multilayer wiring substrate of second embodiment by process sequence.
Figure 18 A～Figure 18 C is the broad cross-section map of manufacture method of semiconductor device of representing to comprise the multilayer wiring substrate of second embodiment by process sequence.
Figure 19 A～Figure 19 C is the broad cross-section map of manufacture method of semiconductor device of representing to comprise the multilayer wiring substrate of second embodiment by process sequence.
Figure 20 A, Figure 20 B are the broad cross-section maps that MOS transistor is formed on the situation in the element region.
Figure 21 is the broad cross-section map of the master operation in the variation of manufacture method of semiconductor device of the expression multilayer wiring substrate that comprises second embodiment.
Figure 22 A～Figure 22 C is the broad cross-section map of formation method of representing the multilayer wiring substrate of the 3rd embodiment by process sequence.
Figure 23 A～Figure 23 C is the broad cross-section map of formation method of representing the multilayer wiring substrate of the 3rd embodiment by process sequence.
Figure 24 A～Figure 24 C is the broad cross-section map of formation method of representing the multilayer wiring substrate of the 4th embodiment by process sequence.
Figure 25 A, Figure 25 B are the broad cross-section maps of formation method of representing the multilayer wiring substrate of the 4th embodiment by process sequence.
Embodiment
-bare bones of the present invention-
Bare bones of the present invention at first is described.
In the present invention, prerequisite is to be main object with the cut of for example using planing tool as the machining process beyond the CMP of representative as flattening method.Insulating material such as metal such as copper, aluminium, nickel or polyimides are easily with the material of planing tool cutting, adopt the method for cutting can be easily and make wiring and the dielectric film planarization that is made of these materials at high speed on Semiconductor substrate.And, adopt the cutting means can not produce dishing.
Be to be that benchmark cuts with the back side (back side) of substrate in the problem that cut is used for the silicon wafer when being the planarization of Semiconductor substrate of representative.Generally, the TTV of silicon substrate is in 1 μ m～5 mu m ranges, and in the processing procedure of LSI, the TTV of about 5 μ m usually, does not go to consider to not influence of photoetching process.But under the situation of cut, the influence of the value of TTV is very big, the smooth precision of cutting does not reach below the TTV value, therefore, under the situation of the planarization that cut is used for Semiconductor substrate, at first must be controlled at the TTV of substrate below the cutting precision of target.
At above-mentioned situation, the present inventor expected before forming wiring and dielectric film, is that benchmark grinds its back side with the surface that constitutes wiring formation face at first, thereby the TTV of Semiconductor substrate is suppressed to below the target cutting precision.In this case, it is little to it is desirable to TTV, and the thickness of each Semiconductor substrate is discrete also can be suppressed to below the cutting precision.But, as long as TTV is little just passable, when cutting, can detect the thickness of each Semiconductor substrate, the thickness that can detect each Semiconductor substrate is controlled cutting output.
In addition, in the present invention, when forming membranaceous multilayer wiring film, use above-mentioned Machining Technology for Cutting, promptly, on the support base that constitutes by insulating material or electric conducting material, form after the multilayer wiring film wiring layer is stacked, remove support base, only the multilayer wiring film as using above-mentioned Machining Technology for Cutting under the situation of interposer (イ Application Port one ザ).In this case because metallic plate or insulation board as support base, so, can adopt cut to carry out planarization (thickness homogenization) as the corresponding support base of the preceding operation that forms wiring layer.And the planarization when carrying out each wiring layer formation with cut can also also be removed support base with cutting in removing the operation of support base.Like this, just can all adopt the cutting of using planing tool to carry out the planarization of support base, the planarization when each wiring layer forms and a series of cutting of support base, can be easily and realize that at high speed the high-precision planarization and the matrix of each wiring layer remove.
In addition, at support base is under the situation of insulation board, utilize that cut possesses easily, at a high speed, high-precision planarization is controlled, when removing support base, just support base can be stayed any thickness and planarization, it can be supplied with insulating barrier simultaneously.At support base is under the situation of metallic plate, and the cutting swarf that cutting is produced collects, and can also be used further to the formation of support base.
-the specific embodiment of the present invention-
Below, the bare bones according to above-mentioned illustrates specific embodiments of the invention with accompanying drawing.
(first embodiment)
Here example silicon semiconductor substrate (silicon wafer) is as substrate, shows to be formed on this Semiconductor substrate in the insulant each wiring laminated multilayer wiring that constitutes for multilayer.
Figure 1A～Fig. 1 E, Fig. 2 A～Fig. 2 C, Fig. 3 A～Fig. 3 C, Fig. 4 A～Fig. 4 C is the broad cross-section map of formation method of representing the multilayer wiring substrate of present embodiment by process sequence.
At first, shown in Figure 1A, prepared silicon Semiconductor substrate 1.Usually, silicon semiconductor substrate is as illustrated, and its thickness is different, and is with the state that rises and falls.
Therefore, as to an interarea of Semiconductor substrate 1 promptly the substrate surface (wiring formation face 1a) here implement preceding operation, i.e. (the wiring formation face 1a's) back side 1b planarization here of another interarea that makes Semiconductor substrate 1 with the cut of aftermentioned planing tool.
Specifically, shown in Figure 1B, prepare to have made bearing-surface 201a smooth substrate holder 201, for example wiring formation face 1a is adsorbed on this bearing-surface 201a by vacuum suction, Semiconductor substrate 1 is fixed on the substrate holder 201.At this moment, wiring formation face 1a is forced to planarization because of being adsorbed on the bearing-surface 201a, and like this, wiring formation face 1a just becomes the datum level of the planarization of back side 1b.Under this state, back side 1b being carried out machining, is to carry out attrition process here, and the protuberance 12 that grinds off back side 1b carries out planarization.At this moment, preferably according to the cutting output of controlling back side 1b apart from the distance of wiring formation face 1a.Like this, the thickness that just can make Semiconductor substrate 1 is for certain, specifically, TTV (maximum ga(u)ge of substrate and minimum thickness poor) is controlled at below the setting, more specifically, TTV is controlled at below the 1 μ m exactly.
Then, shown in Fig. 1 C, Semiconductor substrate 1 is taken off from substrate holder 201, on the wiring formation face 1a of Semiconductor substrate 1, apply for example photosensitive polyimide 13 then, process this photosensitive polyimide 13 with photoetching process again, form predetermined electrode pattern 13a thus.
Next, shown in Fig. 1 D, on wiring formation face 1a,, for example form metal, for example copper film, thereby form inculating crystal layer 2 with sputtering method to cover the mode of photosensitive polyimide 13.
Then, shown in Fig. 1 E, be electrode with inculating crystal layer 2, pile up copper with galvanoplastic, make its thickness bury photosensitive polyimide 13, thereby form ground connection (GND) electrode 3.
Next, the cut to wiring formation face 1a implements to use planing tool makes its planarization.
Specifically, shown in Fig. 2 A, the back side 1b with Semiconductor substrate 1 is adsorbed on the bearing-surface 11a of substrate holder 11 by vacuum suction, thereby Semiconductor substrate 1 is fixed on the substrate holder 11.At this moment, it is certain state that the planarization by Figure 1B makes the thickness of Semiconductor substrate 1, and in addition, the absorption of Fig. 2 A is enforceable to become it does not have the state that rises and falls etc., so back side 1b just becomes the datum level of the planarization of wiring formation face 1a.Under this state, machining is carried out on the top layer of the GND electrode 3 of wiring formation face 1a, be to use the planing tool 10 that constitutes by diamond etc. to carry out cut here, make its planarization.
Then, shown in Fig. 2 B, in planarization GND electrode 3 on coating photoresist 14, with photoetching process processing photoresist 14, opening forms predetermined pillar figure 14a.And with galvanoplastic copper etc. is imbedded in the peristome of pillar figure 14a and formed column sections 4.
Next, shown in Fig. 2 C, after for example photoresist 14 being peeled off, on wiring formation face 1a, form insulating resin 5, to cover column sections 4 and it is imbedded.
Then, again wiring formation face 1a is implemented to use the cut of planing tool, carry out planarization.
Specifically, as shown in Figure 3A, back side 1b is adsorbed on the bearing-surface 11a of substrate holder 11, Semiconductor substrate 1 is fixed on the substrate holder 11 by for example vacuum suction.With above-mentioned the same, at this moment, back side 1b just becomes the datum level of the planarization of wiring formation face 1a.Under this state, the column sections 4 on the wiring formation face 1a and the top layer of insulating resin 5 are carried out machining, be to make the rotating speed rotation of Semiconductor substrate 1 here with for example about 800rpm～1600rpm, with planing tool 10 it is carried out cut, make their planarizations.This planarization make column sections 4 above expose, form the entablature 21 that column sections 4 is embedded in the thickness homogenization in the insulating resin 5 simultaneously.
Next, shown in Fig. 3 B, on the surface of good column sections 4 of planarization and insulating resin 5, pile up copper film and form after the inculating crystal layer 6, apply first photoresist 15, process this first photoresist 15 with photoetching process and form predetermined wiring figure 15a with sputtering method.Be the electrode galvanoplastic with inculating crystal layer 6 then, the wiring figure 15a of first photoresist 15 is partly imbedded, form wiring 7.
Then, shown in Fig. 3 C, remove after first photoresist 15 with for example stripper of alkalescence, apply second photoresist 16 in the mode that it is imbedded in wiring 7, process this second photoresist 16 with photoetching process, opening forms predetermined pillar figure 16a.Then,, imbed pillar figure 16a, form column sections 8 with copper etc. by galvanoplastic.
Next, shown in Fig. 4 A, remove after second photoresist 16 and the inculating crystal layer 6, on wiring formation face 1a, form insulating resin 9, cover wiring 7 and column sections 8, they are imbedded with for example stripper of alkalescence.
Then, again wiring formation face 1a is implemented to use the cut of planing tool, carry out planarization.
Specifically, shown in Fig. 4 B, back side 1b is adsorbed on the bearing-surface 11a of substrate holder 11, Semiconductor substrate 1 is fixed on the substrate holder 11 by for example vacuum suction.With above-mentioned the same, at this moment, back side 1b just becomes the datum level of the planarization of wiring formation face 1a.Under this state, the column sections 8 on the wiring formation face 1a and the top layer of insulating resin 9 are carried out machining, make their planarizations.Here, the example as machining is to carry out cut with planing tool.By this planarization make column sections 8 above expose, form first wiring layer 22 that wiring 7 and connected column sections 8 are embedded in the thickness homogenization in the insulating resin 9 simultaneously.
Then, the same when forming first wiring layer 22 shown in Fig. 4 C, promptly through repeatedly with Fig. 3 B, Fig. 3 C, Fig. 4 A, series of processes that Fig. 4 B is the same, form that wiring and connected column sections are embedded in the insulating resin and the laminated construction of formation.In diagram, example goes out wiring 31 and connected column sections 32 is embedded in second wiring layer 23 of the thickness homogenization in the insulating resin 33, and is formed on the wiring 34 on this second wiring layer 23.
Then, Miltilayer wiring structure has just been finished in the formation of whole diaphragm (not shown) through covering Semiconductor substrate 1 etc. on Semiconductor substrate 1.
In the present embodiment, a slice Semiconductor substrate has been described, but for constituting multi-disc Semiconductor substrate in batches, also can have carried out each operation of present embodiment and make same ground of the thickness homogenization of each Semiconductor substrate.Processing such as like this, just can under identical conditions, cut to each substrate in the same batch for example.
At each planarization in-process of Fig. 2 A, Fig. 3 A and Fig. 4 B, be that benchmark carries out the parallel of Semiconductor substrate 1 and exposes with back side 1b, detect the position of wiring formation face 1a simultaneously, form face 1a from detected wiring again and calculate cutting output, control planing tool 10.
Specifically, as shown in Figure 5, carry out what is called " parallel exposing " like this, that is: when detecting the position of wiring formation face 1a, with a plurality of places at the peripheral position of 17 pairs of laser irradiation devices wiring formation face 1a for example at the insulating resin 5,9 and photosensitive polyimide 13 (according to circumstances being inculating crystal layer 2) the irradiating laser 17a at 3 local A, B, C place, they are added heat dissipation, thereby the part of wiring formation face 1a is exposed.
In this case, as shown in Figure 6, when detecting the position of wiring formation face 1a, also Semiconductor substrate 1 can be absorbed and fixed on the substrate holder 11 that has formed opening 11b, from opening 11b back side 1b is shone infrared laser with infrared laser irradiator 18 again, detect from the reverberation of the formation face 1a that connects up and also can with this infrared laser irradiator 18 (or setting laser determination device in its vicinity).
Here, the comparative example of present embodiment has been shown among Fig. 7, in this comparative example, institute's example be on Semiconductor substrate 201, to form Miltilayer wiring structure 202 and the planarization of not carrying out present embodiment.Like this, do not carrying out under the situation of planarization, along with the increase of the wiring number of plies, top concavo-convex will be remarkable, can harm the laminates linearize.
In contrast to this, in the present embodiment, the structure of being taked is, at first, being benchmark with wiring formation face 1a carries out after the planarization the back side 1b of Semiconductor substrate 1, is entablature 21 and each wiring layer 22,23 that benchmark order on wiring formation face 1a forms the thickness homogeneous with back side 1b on this basis, so, even stacked more multi-layered wiring layer can not damage flatness yet, can suppress concavo-convex generation and realize fine wire structures.
As above explanation, according to present embodiment, the homogenization of dispersing of the thickness of Semiconductor substrate 1, and disadvantages such as dishing can not take place.Its result can be easily and do not have the high speed planarization of the constraint of wires design at an easy rate.In addition, can also realize fine Miltilayer wiring structure easy and exquisitely.
[formation of abrasive working appts]
Here, the concrete device with the attrition process operation of Figure 1B explanation is constituted describe.
What Fig. 8 was represented is the formation of abrasive working appts, and Fig. 8 A is a plane graph, and Fig. 8 B is a side view.
This abrasive working appts have Semiconductor substrate of accommodating (semiconductor wafer) 1 resettlement section 202, Semiconductor substrate 1 is sent to the mechanical hand 203 of each handling part, the rotating disk 204 of Semiconductor substrate 1 when loading fixing grinding the and the grinder portion 205 of grinding semiconductor substrate 1.
Rotating disk 204 possesses, and a plurality of (being 3 here) are clamped on lip-deep chuck 213 with Semiconductor substrate 1, and rotating disk 204 for example can rotate freely along the direction shown in the arrow M of Fig. 8 B.
The following loading and unloading of grinder portion 205 are provided with sand sheet 214 freely, the surface of the Semiconductor substrate 1 on making sand sheet 214 and being clamped on chuck 213 contacts, for example grind,, use two kinds of different sand sheets of fineness degree for example here as sand sheet 214 along the direction shown in the arrow N of Fig. 8 B.
When using this abrasive working appts to carry out attrition process, at first 202 Semiconductor substrate 1 taken out from the resettlement section with the transmission hand 212 of mechanical hand 203, loading is fixed on the chuck 213 of rotating disk 204; Then, make the surface of the sand sheet 214 contact semiconductor substrates 1 of grinder portion 205, grind this surface.At this moment, at first use the coarse sand slice lapping, the sand sheet of the superfine degree of using with fine finishining grinds again.With transmitting hand 212 the ground Semiconductor substrate 1 of fine finishining is taken off from chuck 213 then, accommodated in the resettlement section 202.
[formation of cutting apparatus]
The concrete device formation of the cut operation of using Fig. 2 A, Fig. 3 A, Fig. 4 B explanation is described here.
Fig. 9 is the formation block diagram of cutting apparatus, and Figure 10 A～Figure 10 G is same summary pie graph
This cutting apparatus has resettlement section 101 (Fig. 9 of Semiconductor substrate of accommodating (semiconductor wafer) 1, Figure 10 A), Semiconductor substrate 1 is sent to mechanical hand 102 (Fig. 9 of each handling part, Figure 10 B, Figure 10 C), chuck segment 103 (Fig. 9 of Semiconductor substrate 1 during the chucking cutting, Figure 10 D), carry out detecting part 104 (Fig. 9 of the location of Semiconductor substrate 1, Figure 10 E), carry out cutting portion 105 (Fig. 9 of the planarization cutting of Semiconductor substrate 1, Figure 10 F), 106 (Fig. 9 of clean portion that clean after cutting, Figure 10 G), take 107 (Fig. 9 of optical sensor portion of cutting state, Figure 10 D) and the control part 108 (Fig. 9) that these parts are controlled.Figure 10 A～Figure 10 G is the component diagram of each one, and for simplicity, it is inaccurate that direction and reduced scale etc. are set.
Detecting part 104 has CCD camera 117, load fixing Semiconductor substrate 1 and make rotating disk 118 that Semiconductor substrate 1 rotates freely and the rotary driving part 119 that drives this rotating disk 118 with predetermined rotational speed; Take the periphery that is arranged on the Semiconductor substrate 1 on the rotating disk 118 with CCD camera 117.
Cutting portion 105 possesses the hard planing tool 10 as cutting tools that is made of diamond etc., and has the X-axis tool rest 120 that is provided with this planing tool 10 and Y-axis tool rest 121, drives the X-axis drive division 122 of planing tool 10, drives the Y-axis drive division 123 of planing tool 10 with Y-axis tool rest 121 along Y direction (direction shown in the arrow N among Figure 10 E) along directions X (direction shown in the arrow M among Figure 10 E) with X-axis tool rest 120.
Control part 108 has: drive control part 129, detect the projection light of optical sensor 107 and accept the master control part 132 of the test section 130, operational part 131 of light, overall controlling and driving control part 129, test section 130 and operational part 131, the display part 133 of state of a control that shows master control part 132 and the move portion 134 that master control part 132 is given all driving command; Drive control part 129 control respectively rotary driving part 119, the cutting portion 105 of rotary driving part 116, the detecting part 104 of 3 drive division 115a～115c of 1～Θ of Θ of Z axle drive division 113, mechanical hand 102 of resettlement section 101 and Z axle drive division 115d, chuck segment 103 X-axis drive division 122 and Y-axis drive division 123, clean the rotary driving part 125 of portion 106; The shooting results of the CCD camera 117 of operational part 131 usefulness detecting parts 104 calculates the center of Semiconductor substrate 1, measures and calculate the size of Semiconductor substrate 1 again with optical sensor 107.
With Figure 11 and Figure 12 cutting process is described.
Figure 11 is expression with the schematic diagram of the configuration status of mechanical hand 102 be the center resettlement section 101, chuck segment 103, detecting part 104, cutting portion 105 and clean portion 106.Here, omit diagram optical sensor 107 and control part 108.
Figure 12 is the process chart of this cut.
At first, the transmission hand 114 of mechanical hand 102 takes out (step S1) to Semiconductor substrate 1 from the accepting box 111 of the resettlement section 101 of accommodating Semiconductor substrate 1; Elevating mechanism 112 with resettlement section 101 is elevated to the height that takes out Semiconductor substrate 1 transmitting hand 114.
Then, transmit hand 114 vacuum suction Semiconductor substrate 1, and send it to detecting part 104; At detecting part 104, rotating disk 118 makes Semiconductor substrate 1 rotate 360 °, and with the periphery of CCD camera 112 these Semiconductor substrate 1 of shooting, the operational part 131 of control part 108 is handled its shooting results, calculates the center (step S2) of Semiconductor substrate 1.
Then, transmit the result of calculation correction center of hand 114 according to the center, and Semiconductor substrate 1 is sent to chuck segment 103, substrate holder 11 usefulness vacuum are fixed Semiconductor substrate 1 (step S3).This substrate holder 11 just becomes processing datum.Therefore, when being maintained fixed and add the plane precision in man-hour, clamping face preferably uses whole of porous material clamping Semiconductor substrate 1, adopts materials such as metal system, pottery system, resin system.The top and bottom of facing the Semiconductor substrate 1 that is held dispose light-projecting portion 114 and light accepting part 115 respectively, and measure and calculate the size of Semiconductor substrate 1 with control part 108, its result is fed back to the X-axis drive division 112 of cutting portion 105, and instruct and cut amount of movement.Here, be under the situation of wiring formation face, specifically in the cutting face, as shown in Figure 5, preferably irradiating laser heats photo etched mask and makes its dissipation, the surface is revealed, and come gauge position with the reflection sensor of as shown in Figure 6 the sort of employing infrared laser.In the metering of aforesaid position, also can use the infiltration type transducer.
On the direction of the arrow M identical, move the planing tool 10 that cuts according to above-mentioned operation result (substrate dimension) with X-axis tool rest 120 then, begin cutting (step S4) with Figure 10 F.Like this, if cutting output reaches set point, just finished the cutting (step S5) till setting size.
Next, transmit hand 114 and from substrate holder 11, Semiconductor substrate 1 is taken off (step S6), and be sent to the portion 106 that cleans.In clean portion 106, Semiconductor substrate 1 vacuum is fixed on the rotating disk 124, simultaneously rotation one side is used from the clean water of nozzle 126 ejections the remained on surface foreign substance cleaning of the Semiconductor substrate 1 after processing is fallen.Then, air blowing limit, limit high speed rotating dries clean water and makes it dry (step S7).After dry the end, transmit hand and again Semiconductor substrate 1 is taken out, accommodate the accepting box 111 interior (step S8) of resettlement section 101 at last.
In the present embodiment, use above-mentioned abrasive working appts, with after being formed with the wiring and the wiring formation face of dielectric film and being ground its back side of datum level, use above-mentioned abrasive working appts again, be that benchmark carries out planarization to the surface of each wiring and the surface of dielectric film with the back side.
(second embodiment)
Here institute's example be with silicon semiconductor substrate as substrate, be formed on the wiring layer that lamination multilayer in the insulant is made of each wiring when making LSI and the situation of the multiple wiring layer that constitutes.
As the semiconductor device that comprises multiple wiring layer, the device of Figure 13 and the sort of form shown in Figure 14 is arranged.The semiconductor device of Figure 13 is formed with electrode 63a in silicon semiconductor substrate 301, electrode 63a be trapped among the element region 302 that is formed with a plurality of semiconductor elements (MOS transistor etc.) around, each semiconductor element and electrode 63a are electrically connected.On the other hand, the semiconductor device of Figure 14 forms a plurality of electrode 63a rectangular in silicon semiconductor substrate 301, forms a plurality of semiconductor elements between each electrode 63a.That is, under the situation of Figure 14, the zone between the electrode 63a becomes element region 303.The present invention is applicable to the semiconductor device both sides of Figure 13 and Figure 14, but in the following description, for simplicity, example goes out the semiconductor device of form shown in Figure 14, for example, illustrates later on along the summary section of the chain-dotted line I-I of Figure 14 at Figure 15.
Figure 15 A～Figure 15 D, Figure 16 A～Figure 16 C, Figure 17 A～Figure 17 C, Figure 18 A～Figure 18 C, Figure 19 A～Figure 19 C represents broad cross-section map according to the manufacture method of the semiconductor device that comprises multilayer wiring of present embodiment by process sequence.
Shown in Figure 15 A; at first the prepared silicon Semiconductor substrate 1, go up impurity diffusion zone 61 that order forms the impurity diffusion layer that constitutes semiconductor element at substrate surface (wiring formation face 1a), on impurity diffusion zone 61, imbed the insulating barrier 62 that for example constitutes in by inorganic matter LSI wiring 63 and in LSI wiring 63 to expose the connect up mode diaphragm 64 on surface of 63 electrode 63a of LSI.In illustrated embodiment, the zone between the adjacent electrode 63a (and LSI wiring 63) constitutes the element region 303 of Figure 14.In this case, element region 303 always closes the zone between the electrode 63a of each adjacency.
Here, for simplicity, omitted the diagram of each semiconductor element among Figure 15.Shown in Figure 20 A, in element region 303, be formed with a plurality of semiconductor elements more accurately, be formed with MOS transistor 304 here.Shown in Figure 20 B, each MOS transistor 304 forms grid 112 on the surface of element region 303 through gate insulating film 311 figures, and impurity is imported the impurity diffusion zone 61 of these grid 112 both sides, forms a pair of impurity diffusion layer 113 that constitutes source/drain.In addition, on the surface of element region 303, wiring 114 figures are formed, couple together with each impurity diffusion layer 113, these wirings 114 constitute the part of LSI wiring 63.Impurity diffusion zone 61 is the zones that form the multilayer impurity diffusion layer of a plurality of MOS transistor, and in fact place that has impurity diffusion layer and the place that does not have impurity diffusion layer are arranged, but for simplicity, all is the zone that is rendered as impurity diffusion zone in the lump.
Even the only zone between the electrode 63a of adjacency also forms very many MOS transistor 304, so, for simplicity, in Figure 15 and following each figure thereof, all omit the diagram of MOS transistor 304.
And, as mentioned above, implement preceding operation with the cut of planing tool described later as the wiring that has formed MOS transistor 304 or LSI wiring 63, diaphragm 64 etc. being formed face 1a, the back side 1b of the formation face 1a that connects up is carried out planarization.
Specifically, shown in Figure 15 B, prepare to have made bearing-surface 201a smooth substrate holder 201, the formation face 1a that will connect up is adsorbed on this bearing-surface 201a, for example hold wiring formation face 1a, thereby Semiconductor substrate 1 is fixed on the substrate holder 201 by vacuum suction.At this moment, to the absorption of the bearing-surface 201a formation face 1a planarization by force of will connecting up, like this, wiring formation face 1a just becomes the planarization datum level of back side 1b, under this state, back side 1b is carried out machining, here, be to carry out attrition process, grind the protuberance 12 of removing back side 1b, make back side 1b planarization.In this case, preferably according to the cutting output of controlling back side 1b apart from the distance of this back side 1b.Like this, just be certain with the THICKNESS CONTROL of Semiconductor substrate 1, specifically, TTV (maximum ga(u)ge of substrate and minimum thickness poor) is controlled at below the 1 μ m.
Then, shown in Figure 15 C, Semiconductor substrate 1 is taken off from substrate holder 201, on the wiring formation face 1a of Semiconductor substrate 1, apply for example photosensitive polyimide 13 of photoresist, with photoetching process this photosensitive polyimide 13 is processed, formed the wiring figure 13b of the electrode 63a shape of exposing several LSI wirings 63.
Then, shown in Figure 15 D, on wiring formation face 1a, form metal such as copper film (golden film etc. are also passable, below be that example illustrated with copper), cover photosensitive polyimide 13, form inculating crystal layer 2 with sputtering method for example.
Then, shown in Figure 16 A, coating photoresist 92 on wiring formation face 1a is processed photoresist 92 with photoetching process, makes on photoresist 92 after the figure opening of regulation, piles up copper with inculating crystal layer 2 as electrode plating.
Then, shown in Figure 16 B, after photoresist 92 stripped down, be mask etching inculating crystal layer 2 with the copper of piling up, it is removed.
Next, shown in Figure 16 C, apply and solidify insulating resin 42 to bury wiring 41 mode.Also can when forming insulating resin 42, remove the inculating crystal layer 2 that exposes.
Then, to the cut that wiring formation face 1a implements to use planing tool, carry out planarization.
Specifically, shown in Figure 17 A, back side 1b is adsorbed on the bearing-surface 11a of substrate holder 11, Semiconductor substrate 1 is fixed on the substrate holder 11 with for example vacuum suction.At this moment, make the thickness of Semiconductor substrate 1 become certain state, back side 1b is become do not have the state that rises and falls etc. to the absorption of bearing-surface 11a the planarization of Figure 15 B of back side 1b.Like this, back side 1b just becomes the datum level of the planarization of wiring formation face 1a.Under this state, machining is carried out in the wiring 41 in the wiring formation face 1a and the top layer of insulating resin 42, here, be the rotary speed rotation about making Semiconductor substrate 1 with revolution 800rpm～1600rpm, carry out cut with planing tool 10, make its planarization.With this planarization wiring 41 is exposed above it, form first wiring layer 51 that is embedded in the insulating resin 42.And for simplicity, what go out illustrated in Figure 17 A is that top layer with wiring 41 and insulating resin 42 makes continuous tabular surface.
Then, shown in Figure 17 B, sputter forms after the inculating crystal layer 19 that constitutes electroplated electrode on first wiring layer 51 that has been flattened, and coating photoresist 14 is processed photoresist 14 with photoetching process, makes the pillar figure 14a of regulation form opening.Then, imbed pillar figure 14a with copper etc., form column sections 4 with galvanoplastic.
Then, shown in Figure 17 C, after photoresist 14 stripped down,, on wiring formation face 1a, form insulating resin 5 in the mode that column sections 4 is covered and imbeds with for example adopting the wet etching of fluoric acid that inculating crystal layer 19 is removed.
Then, again wiring formation face 1a is implemented to use the cut of planing tool, carry out planarization.
Specifically, shown in Figure 18 A, back side 1b is adsorbed on the bearing-surface 11a of substrate holder 11, Semiconductor substrate 1 is fixed on the substrate holder 11 with for example vacuum suction.At this moment, with above-mentioned the same, back side 1b becomes the datum level of the planarization of wiring formation face 1a.Under this state, the column sections 4 in the wiring formation face 1a and the top layer of insulating resin 5 are carried out machining,, carry out cut here with planing tool 10, make its planarization.With this planarization column sections 4 is exposed above it, form the thickness that is embedded in the insulating resin 5 by homogenization entablature 21.In fact, though begin to make the top layer planarization of column sections 4 and insulating resin 5 from cutting with planing tool, but what go out illustrated in for simplicity, in Figure 18 A is also the top layer of also unsanctioned column sections 4 of planing tool 10 and insulating resin 5 to be made continuous tabular surface.
Then, shown in Figure 18 B, electroplate on the surface of column sections 4 that has been flattened and insulating resin 5 and pile up copper film and form after the inculating crystal layer 6, coating photoresist 15 is processed this photoresist 15 with photoetching process, forms the wiring figure 15a of regulation.Then, form the wiring 7 of the wiring figure 15a that imbeds photoresist 15 with galvanoplastic as electrode with inculating crystal layer 6.
Then, shown in Figure 18 C, after for example alkaline stripper was removed photoresist 15, coating photoresist 16 was imbedded it in wiring 7, with photoetching process this photoresist 16 is processed again, made the pillar figure 16a of regulation form opening.Then, bury pillar figure 16a with copper etc., form column sections 8 with galvanoplastic.
Then, shown in Figure 19 A, after photoresist 16 stripped down,, on wiring formation face 1a, form insulating resin 9, wiring 7 and pillar 8 coverings and imbed with for example adopting the wet etching of fluoric acid that inculating crystal layer 6 is removed.
Then, again wiring formation face 1a is implemented to use the cut of planing tool, carry out planarization.
Specifically, shown in Figure 19 B, back side 1b is adsorbed on the bearing-surface 11a of substrate holder 11, Semiconductor substrate 1 is fixed on the substrate holder 11 with for example vacuum suction.At this moment, with above-mentioned the same, back side 1b becomes the datum level of the planarization of wiring formation face 1a.Under this state, the column sections 8 in the wiring formation face 1a and the top layer of insulating resin 9 are carried out machining,, carry out cut here with planing tool 10, make its planarization.With this planarization make column sections 8 above expose, form wiring 7 and the column sections 8 that is connected with this wiring 7 be embedded in the interior thickness of insulating resin 9 by homogenization second wiring layer 52.What go out illustrated in for simplicity, in Figure 19 B is as continuous tabular surface the top layer of column sections 8 and dielectric film 9.
Then, shown in Figure 19 C, the same when forming with second wiring layer 52, promptly, through repeatedly with Figure 18 B, Figure 18 C, Figure 19 A, series of processes that Figure 19 B is the same, form that wiring and connected column sections are embedded in the insulating resin and the laminated construction of formation.In diagram, example goes out wiring 31 and connected column sections 32 is embedded in the 3rd wiring layer 53 of the thickness homogenization in the insulating resin 33, and is formed on the wiring 34 on the 3rd wiring layer 53.
Then, the semiconductor device of have element region 303 on Semiconductor substrate 1 (comprising a plurality of MOS transistor 304) and Miltilayer wiring structure has just been finished in the formation of whole diaphragm (not shown) through covering Semiconductor substrate 1 etc.
In the present embodiment, being benchmark with wiring cambium layer 1a at first carries out planarization to the back side 1b of Semiconductor substrate 1, afterwards, on this basis, be benchmark forms the thickness homogeneous in turn on wiring cambium layer 1a entablature 21 and wiring layer 51～53 with back side 1b.Because adopt such structure, thus even the more multi-layered wiring layer of lamination can not damage flatness yet, and can suppress the generation of convex-concave pattern, realize fine wire structures.
Picture is discussed above, according to present embodiment, can make the discrete homogenization of thickness of Semiconductor substrate 1, uncomfortable situations such as dishing do not take place, can be easily and do not have the high speed planarization of wires design constraint at an easy rate, thus realize possessing the semiconductor device of fine Miltilayer wiring structure easy and exquisitely.
In the present embodiment, a slice Semiconductor substrate has been described, but for constituting multi-disc Semiconductor substrate in batches, also can have carried out each operation of present embodiment and make same ground of the thickness homogenization of each Semiconductor substrate.Processing such as like this, just can under identical conditions, cut to each substrate in the same batch for example.
(variation)
The variation of present embodiment below is described.
In this variation, the bits of sweeping with the cut in-process attached cutting face of planing tool that illustrated are in a second embodiment handled, and below illustrate on Figure 21 and originally sweep the summary that bits are handled.
In the usefulness cut of planing tool, can carry out the cutting of wide region with low-cost short time very high degree of precision ground (with the smooth fineness degree of nanometer scale) according to second embodiment.
, in this case, follow cut to produce cutting swarf, this cutting swarf might be attached on the cutting face.Because static is attached on the cutting face, so can after cutting it be removed the cutting swarf of insulating barrier that becomes the cutting object and the insulating material in the wiring (comprising column sections).With respect to this, in case wiring material particularly the cutting swarf of Au can combine with the cutting face attached on the cutting face, just be not easy it is removed with method such as clean.As a result, just become the surface configuration of adhering to the cutting swarf of several μ m～tens μ m sizes on the high cutting face of the flatness of fineness degree of nanometer scale, may harm planarization.As mentioned above, wiring material is that this phenomenon is remarkable especially under the situation of Au, still, even Cu or its alloy etc. also have same problem.
In this variation, in using the cut operation of planing tool, form after the smooth cutting face by cutting, use this planing tool bits are swept in the cutting face again with described cutting co-located (zero bite).Because be zero bite, thus new cutting swarf can be produced hardly, but can positively remove attached to the cutting swarf on the cutting face.
But, consider sweep bits handle the cutting swarf remove can be once more attached on the cutting face, in order to prevent this situation, carrying out this when sweeping bits and handling, spray air or water or machining fluid are effective methods on the feeding direction of planing tool.Here, because planing tool contacts whole cutting face, so the feed rate of planing tool must be identical with when cutting or below it.
Specifically, in the cut operation shown in Figure 17 A, use the wiring 41 of 10 pairs of wirings of planing tool formation face and the top layer of insulating resin 42 to carry out cut, after the planarization, as shown in figure 21, under the state that Semiconductor substrate 1 is fixed on the substrate holder 11, bits are swept with planing tool 10 in identical planing tool position (zero bite), the bite position with planarization fine finishining the time.At this moment the amount of feeding is identical during with fine finishining, for example gets 10 μ m/ and changes.At this moment, blow in 93 pairs of cutting faces along the direction identical with the direction of feed of planing tool 10 from the air unloading part, prevents adhering to once more of cutting swarf 94.Here, particularly under the situation that cutting swarf adheres to easily, also can spray water with high pressure or machining fluid replaces air.
The bits processing of sweeping of this variation equally also goes for the cut operation of Figure 18 A and the cut operation of Figure 19 B.
According to this variation, when making the discrete homogenization of the thickness of Semiconductor substrate 1, prevented to rise and fall or crooked generation, disadvantages such as dishing can not take place, and can be easily and do not have the planarization of the high speed exquisiteness of wires design constraint at an easy rate, and the cutting swarf can positively remove planarization the time, keep the flatness in cutting face, can realize possessing the semiconductor device of fine Miltilayer wiring structure easy and exquisitely.
(the 3rd embodiment)
Here shown is with support base as substrate, specifically use copper coin as substrate, form situation as the membranaceous multilayer wiring film of interposer etc.
Figure 22 A～Figure 22 C and Figure 23 A～Figure 23 C are the broad cross-section maps of formation method of representing the multilayer wiring substrate of present embodiment by process sequence.
At first, shown in Figure 22 A, the copper coin 71 that for example thickness is slightly larger than 8 inches of 1mm, diameter is adsorbed on the chuck 305 of for example above-mentioned cutting apparatus, cut with adamantine planing tool 10, touch up to planing tool 10 till the whole surface of copper coin 71, make the thickness homogenization of copper coin 71.Reclaim the cutting swarf that is at this moment produced, be used for the regeneration of copper coin.
Then, shown in Figure 22 B, photoresist is coated in the surface of copper coin 71, processes, form the ground floor wiring figure with photoetching process.The L/S of wiring figure at this moment is 5 μ m/5 μ m for example.Then, be that inculating crystal layer forms wiring 72 with the electrolysis plating with copper coin 71.Here, the diaphragm (not shown) is attached to the back side of copper coin 71, prevents to electroplate and adhere to, remove photoresist then.
Next, forming the pillar figure with photoresist, with above-mentioned the same, is inculating crystal layer forms the about 12 μ m of for example highly about 12 μ m diameters with the electrolysis plating support column 73 with copper coin 71.At this moment, also stick the diaphragm (not shown) at the back side of copper coin 71 and prevent to electroplate and adhere to, remove photoresist then.
Then, so that wiring 72 and support column 73 are imbedded, then, in for example 370 ℃ of following heat hardenings, form resin molding 74 with spin-coating method coating polyimide precursor (the ProductName P12611 that HD マ イ Network ロ シ ス テ system company produces) with 2 ℃/min programming rate.After this, on the part of resin molding 74, leave the hole that arrives copper coin 71 surfaces with laser.
Next, the back side of copper coin 71 is contained on the chuck 305 down, measure the degree of depth in described hole, begin to carry out cut till about 10 μ m height from the surface of copper coin 71 with planing tool 10, make its planarization, on the resin molding 74 of thickness homogeneous, form buried wiring 72 and support column 73 and the ground floor wiring layer 81 of formation.Here, expose on the top surface from wiring layer 81 of support column 73.At this moment machining condition is that for example revolution is that 1000rpm, feed speed are that the anterior angle of 3mm/min, planing tool 10 is that 10 °, bite are 1 μ m.
Then, form inculating crystal layer (Cr/Cu stack membrane, thickness 100nm/300nm) afterwards with the splatter method, shown in Figure 22 C, with above-mentioned the same, figure forms wiring 75 and support column 76.Remove after the photoresist, inculating crystal layer is removed in corrosion again.
Next, same, with the above-mentioned polyimide precursor of spin-coating method coating, wiring 75 and support column 76 are imbedded, then, in for example 370 ℃ of following heat hardenings, form resin molding 77 with 2 ℃/min programming rate.After this, on the part of resin molding 77, leave the hole that arrives copper coin 71 surfaces with laser.
Then, the back side of copper coin 71 is contained on the chuck 305 down, measure the degree of depth in described hole, begin to carry out cut till about 10 μ m height from the surface of copper coin 71 with planing tool 10, make its planarization, on the resin molding 77 of thickness homogeneous, form buried wiring 75 and support column 76 and the second layer wiring layer 82 of formation.Here, expose on the top surface from wiring layer 82 of support column 76.
Shown in Figure 23 A, repeat the formation operation of above-mentioned wiring layer, form the multilayer wiring film that the wiring layer by the desirable number of plies constitutes.Then, form the protective layer of the thick about 13 μ m that constitute by polyimides.After the place forms pillar 78 arbitrarily, reach about 10 μ m thickness with laser, make its planarization with planing tool cut protective layer.In illustrated embodiment, the multilayer wiring film 80 of institute's example is made of 4 layers of wiring layer, on the wiring layer of the superiors, only forms pillar 78 by the above-mentioned cut with planing tool 10.In illustrated embodiment, dot the protective layer part that cutting reaches about 10 μ m thickness.
Then, shown in Figure 23 B, protective layer is contained on the chuck 305 down, removes copper coin 71 with planing tool 10 cuttings, only it stays the thickness of for example about 0.5 μ m.At this moment, reclaim the cutting swarf that is produced, be used for the regeneration of copper coin.
Shown in Figure 23 C, residual copper coin 71 is removed in corrosion, thereby makes membranaceous multilayer wiring film 80.
In the present embodiment, before the cutting copper coin 71, also can make the wiring layer chipization in advance from wiring layer cutting appropriate depth.
As described above, according to present embodiment, in the end remove under the situation that support base obtains monomer multilayer wiring film, constitute the control of exquisiteness of thickness of each wiring layer of multilayer wiring film 80 easily, while can be effectively and removes copper coin 71 at low cost easily, and the about 5 μ m of strut diameter～10 μ m, L/S is the multilayer wiring film of the fine wire structures of 5 μ m/5 μ m～20 μ m/20 μ m thereby for example can realize having.
[the 4th embodiment]
Here, the same with the 3rd embodiment, what showed is to be substrate with support base, specifically is substrate with the copper coin, forms the membranaceous multilayer wiring film as switching piece etc., but the formation method difference of each wiring layer.
Figure 24 A～Figure 24 C and Figure 25 A～Figure 25 C are the broad cross-section maps of formation method of representing the multilayer wiring substrate of present embodiment by process sequence.
At first, shown in Figure 24 A, the copper coin 71 that for example thickness is slightly larger than 8 inches of 1mm, diameter is adsorbed on the chuck 305 of for example above-mentioned cutting apparatus, cut with adamantine planing tool 10, touch up to planing tool 10 till the whole surface of copper coin 71, make the thickness homogenization of copper coin 71.At this moment, reclaim the cutting swarf that is produced, be used for the regeneration of copper coin.
Then, shown in Figure 24 B, on the surface of copper coin 71, form the stack membrane 83 of the about 20 μ m of thickness that constitute by photonasty epoxy resin, the pillar hole 84 of exposure, the about 20 μ m of formation diameter that develop.Make with oxidant after the surface coarsening of stack membrane 83, form inculating crystal layer with electroless plating.
Next, the photoresist with the about 10 μ m of thickness forms wiring figure (about L/S=10 μ m/10 μ m).When forming wiring layer 85, fill pillar hole 84 with galvanoplastic.At this moment, plating also can extend on the photoresist outward.
Next, the back side of copper coin 71 is contained on the chuck 305 down, begin to carry out cut till highly being about 5 μ m from the surface of stack membrane 83 with planing tool 10, make its planarization, on the stack membrane 83 of thickness homogeneous, form and imbed the ground floor wiring layer 91 of being electroplated the pillar hole 84 of filling and wiring layer 85 and constituting.At this moment machining condition is that for example revolution is that 1000rpm, feed speed are that the anterior angle of 3mm/min, planing tool 10 is that 0 °, bite are 1 μ m.Then, remove photoresist, inculating crystal layer is removed in corrosion again.
Shown in Figure 24 C, repeat the formation operation of above-mentioned wiring layer, form the multilayer wiring film that the wiring layer by the desirable number of plies constitutes.Then, form the protective layer of the thick about 13 μ m that constitute by polyimides.After the place forms pillar 78 arbitrarily, reach about 10 μ m thickness with laser, make its planarization with planing tool 10 cut protective layers.In illustrated embodiment, the multilayer wiring film 90 of institute's example is made of 3 layers of wiring layer, and the wiring layer in the superiors only forms pillar 78 by the above-mentioned cut surface with planing tool 10.In illustrated embodiment, dot the protective layer part that cutting reaches about 10 μ m thickness.
Then, shown in Figure 25 A, protective layer is contained on the chuck 305 down, removes copper coin 71, only stay the thickness of for example about 5 μ m with planing tool 10 cuttings.At this moment, reclaim the cutting swarf that is produced, be used for the regeneration of copper coin.
Shown in Figure 25 B, residual copper coin 71 is made figure, form the wiring 82 of regulation, thereby make membranaceous multilayer wiring film 90.
As described above, according to present embodiment, in the end remove under the situation that support base obtains monomer multilayer wiring film, constitute the control of exquisiteness of thickness of each wiring layer of multilayer wiring film easily, while can be effectively and removes copper coin 71 at low cost easily, and the about 5 μ m of strut diameter～10 μ m, L/S is the multilayer wiring film of the fine wire structures of 5 μ m/5 μ m～20 μ m/20 μ m thereby for example can realize having.
In present embodiment and variation, example goes out electric conductor substrate (copper coin) as support base, but also can constitute support base with dielectric substrate such as resins.In this case, the same with present embodiment, make after the thickness homogeneous of support base by the cut of using planing tool, make the homogenization of wiring layer planarization thickness with cut, lamination gets up to form the multilayer wiring film simultaneously, carries out cut again from the back side and removes support base.When this cut, also can make support base stay any thickness and make its planarization, as insulating barrier.
Under the big situation of degree of crook, the so-called toughness of as described above the resin that becomes processing object, preferably the anterior angle with planing tool is taken as more than 5 °, so just can reduce the rugosity of polished surface.
According to the present invention, as flattening method, consideration is that the CMP machining process in addition of representative is main object with the cut, make the discrete homogenization of thickness of substrate (particularly Semiconductor substrate), disadvantages such as dishing can not take place, can be easily and realize the high speed planarization that no wires design retrains at an easy rate.
According to the present invention, in the end remove support base and obtain under the situation of monomer multilayer wiring film, constitute the control of exquisiteness of thickness of each wiring layer of multilayer wiring film easily, simultaneously can be effectively, low cost easily removes copper coin, and realization has the multilayer wiring film of fine wire structures.
Claims (19)
1. the formation method of the substrate that connects up forms wiring on an interarea of processed substrate, it is characterized in that, comprises following operation:
First operation, pass through vacuum suction, make an interarea of the described substrate that should form described wiring become smooth state forcibly, an interarea with described substrate under this state is a benchmark, another interarea to described substrate is implemented first machining, another interarea planarization with described substrate
Second operation on an interarea of described substrate, forms described wiring and covers the dielectric film of described wiring,
The 3rd operation is a benchmark with another interarea of described substrate, and an interarea of described substrate is implemented second machining, makes an interarea planarization of described substrate, so that the surface of described wiring and described dielectric film is surperficial continuous and smooth,
Described second machining is to use the cut of planing tool.
2. the formation method of wiring substrate according to claim 1 is characterized in that described substrate is a Semiconductor substrate.
3. the formation method of wiring substrate according to claim 2 is characterized in that, before described first operation, is included on the described interarea of described Semiconductor substrate, forms the operation of semiconductor element.
4. the formation method of wiring substrate according to claim 1, it is characterized in that, by the series of processes that repeatedly repeats to constitute, in described dielectric film, form each described wiring lamination multilayer and the multilayer wiring that constitutes by described second operation and described the 3rd operation.
5. the formation method of wiring substrate according to claim 1 is characterized in that, described first machining is attrition process.
6. the formation method of wiring substrate according to claim 2 is characterized in that, by described first machining, the difference of the maximum ga(u)ge of described Semiconductor substrate and minimum thickness is controlled at 1 μ m or below it.
7. the formation method of wiring substrate according to claim 2 is characterized in that, the described Semiconductor substrate of multi-disc is carried out each described operation, makes the thickness homogeneous of each described Semiconductor substrate turn to same thickness.
8. the formation method of wiring substrate according to claim 2, it is characterized in that, in described the 3rd operation, with described another interarea is benchmark, carrying out the parallel of described Semiconductor substrate exposes, detect the position of a described interarea simultaneously, calculate and the control cutting output from a detected described interarea.
9. the formation method of wiring substrate according to claim 8, it is characterized in that, when detecting the position of a described interarea, many places irradiating laser to the peripheral position of a described interarea upper nonconductive Film, make the insulant of described dielectric film add heat dissipation, thereby expose the part of a described interarea.
10. the formation method of wiring substrate according to claim 8 is characterized in that, when detecting the position of a described interarea, to described another interarea irradiation infrared laser, and mensuration is from the reverberation of a described interarea.
11. the formation method of wiring substrate according to claim 1 is characterized in that, the wiring that a described interarea is described substrate forms face; Described another interarea is the back side of described substrate.
12. the formation method of the substrate that connects up is characterized in that, comprises following operation:
First operation by vacuum suction, makes the surface of support base become smooth state forcibly, is benchmark with described surface under this state, and make the back side planarization of described support base by first machining, and make the thickness homogenization of support base,
Second operation, thickness by homogenization described surface on, form wiring and cover the dielectric film of described wiring,
The 3rd operation is carried out planarization with second machining, makes the surperficial continuous and smooth of the surface of described wiring and described dielectric film, forms the wiring layer that is made of described wiring and described dielectric film,
The 4th operation is removed described support base, forms the wiring film of the thickness homogeneous with described wiring layer thus,
Described second machining is to use the cut of planing tool.
13. the formation method of wiring substrate according to claim 12, it is characterized in that, when carrying out described planarization by described second machining, make the integral thickness homogeneous of described support base and each described wiring layer, repeatedly repeat simultaneously the series of processes that constitutes by described second operation and described the 3rd operation, form the described wiring film of the thickness homogeneous that the described wiring layer of multilayer is laminated thus.
14. the formation method of wiring substrate according to claim 12 is characterized in that, after the described cut, uses described planing tool, on the planing tool position identical with described planarization, bits is swept in the cutting face that described planarization is crossed again.
15. the formation method of wiring substrate according to claim 12 is characterized in that described first machining is to use the cut of planing tool.
16. the formation method of wiring substrate according to claim 12 is characterized in that, in described the 4th operation, carries out cut with planing tool from the back side to described support base, removes described support base.
17. the formation method of wiring substrate according to claim 12 is characterized in that, described support base is the matrix that is made of electric conducting material.
18. the formation method of wiring substrate according to claim 17 is characterized in that, the cutting swarf that produces when reclaiming the described support base of cutting with described the 4th operation is used for forming described support base again.
19. the formation method of wiring substrate according to claim 18, it is characterized in that, in described the 4th operation, with the residual any thickness of described support base and make it also to comprise the 5th operation that the described support base that will left behind as conductive layer is processed into arbitrary graphic after the planarization.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
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| US11145521B2 (en) * | 2017-09-28 | 2021-10-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for cleaning a semiconductor substrate |
| CN110625460B (en) * | 2019-09-18 | 2021-04-13 | 北京遥测技术研究所 | Planarization process method for wafer-level heterostructure |
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