WO2004051745A3 - Elektronisches bauelement mit mehreren chips und verfahren zur herstellung - Google Patents

Elektronisches bauelement mit mehreren chips und verfahren zur herstellung Download PDF

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Publication number
WO2004051745A3
WO2004051745A3 PCT/DE2003/003769 DE0303769W WO2004051745A3 WO 2004051745 A3 WO2004051745 A3 WO 2004051745A3 DE 0303769 W DE0303769 W DE 0303769W WO 2004051745 A3 WO2004051745 A3 WO 2004051745A3
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WO
WIPO (PCT)
Prior art keywords
chips
electronic component
same
producing
relates
Prior art date
Application number
PCT/DE2003/003769
Other languages
English (en)
French (fr)
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WO2004051745A2 (de
Inventor
Ulrich Bauernschmitt
Veit Meister
Original Assignee
Epcos Ag
Ulrich Bauernschmitt
Veit Meister
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Epcos Ag, Ulrich Bauernschmitt, Veit Meister filed Critical Epcos Ag
Publication of WO2004051745A2 publication Critical patent/WO2004051745A2/de
Publication of WO2004051745A3 publication Critical patent/WO2004051745A3/de

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222Integrating an electronic processing unit with a micromechanical structure
    • B81C1/0023Packaging together an electronic processing unit die and a micromechanical structure die
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Wire Bonding (AREA)

Abstract

Die Erfindung betrifft ein elektronisches Bauelement mit mehreren Chips (CH1, CH2), die auf einer Basisplatte (BP) angeordnet sind und mit dieser mittels unterschiedlicher Verbindungstechniken, z. B. Flip-Chip-Technik, Surface Mounted Design oder Drahtbondtechnik elektrisch verbunden sind. Die Erfindung schlägt eine Verkapselung der Chips (individuell oder als Gruppe aus zumindest zwei Chips) mit einer Abdeckung (AB) sowie ein Verfahren zur Herstellung vor.
PCT/DE2003/003769 2002-12-05 2003-11-13 Elektronisches bauelement mit mehreren chips und verfahren zur herstellung WO2004051745A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10256945A DE10256945A1 (de) 2002-12-05 2002-12-05 Elektronisches Bauelement mit mehreren Chips und Verfahren zur Herstellung
DE10256945.2 2002-12-05

Publications (2)

Publication Number Publication Date
WO2004051745A2 WO2004051745A2 (de) 2004-06-17
WO2004051745A3 true WO2004051745A3 (de) 2005-02-24

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PCT/DE2003/003769 WO2004051745A2 (de) 2002-12-05 2003-11-13 Elektronisches bauelement mit mehreren chips und verfahren zur herstellung

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DE102005063640B3 (de) * 2005-11-10 2019-11-21 Tdk Corporation MEMS-Package und Verfahren zur Herstellung
DE102008028757B4 (de) 2008-06-17 2017-03-16 Epcos Ag Verfahren zur Herstellung einer Halbleiterchipanordnung
DE102012218561A1 (de) * 2012-10-11 2014-04-17 Siemens Aktiengesellschaft Elektronikmodul, Mehrfachmodul und Verfahren zum Herstellen eines Elektronikmoduls
CN113555493B (zh) * 2021-07-20 2024-09-03 甬矽电子(宁波)股份有限公司 半导体封装结构和半导体封装方法

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