WO2004040623A3 - Couche de barriere amelioree pour une couche de metallisation de cuivre comprenant un dielectrique a faible valeur k - Google Patents

Couche de barriere amelioree pour une couche de metallisation de cuivre comprenant un dielectrique a faible valeur k Download PDF

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Publication number
WO2004040623A3
WO2004040623A3 PCT/US2003/035433 US0335433W WO2004040623A3 WO 2004040623 A3 WO2004040623 A3 WO 2004040623A3 US 0335433 W US0335433 W US 0335433W WO 2004040623 A3 WO2004040623 A3 WO 2004040623A3
Authority
WO
WIPO (PCT)
Prior art keywords
low
nitrogen
dielectric
improved barrier
copper metallization
Prior art date
Application number
PCT/US2003/035433
Other languages
English (en)
Other versions
WO2004040623A2 (fr
Inventor
Hartmut Ruelke
Joerg Hohage
Thomas Werner
Massud Aminpur
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10250889A external-priority patent/DE10250889B4/de
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to AU2003291348A priority Critical patent/AU2003291348A1/en
Publication of WO2004040623A2 publication Critical patent/WO2004040623A2/fr
Publication of WO2004040623A3 publication Critical patent/WO2004040623A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'effet d'empoisonnement de resist peut être éliminé ou au moins sensiblement réduit dans la formation d'une couche de métallisation à faible valeur k, de sorte qu'une couche d'arrêt de gravure/barrière contenant de l'azote (250) présente une concentration en azote significativement réduite au niveau d'une interface (251) en contact avec ladite matière diélectrique à faible valeur k (206). Par conséquent, la diffusion de l'azote et de composés d'azote dans des trous formés dans ladite couche diélectrique à faible valeur k (206) est considérablement réduite, de sorte que, dans une étape de photolithographie ultérieure, une interaction entre l'azote et des composés d'azote, et le photoresist, est remarquablement réduite.
PCT/US2003/035433 2002-10-31 2003-10-27 Couche de barriere amelioree pour une couche de metallisation de cuivre comprenant un dielectrique a faible valeur k WO2004040623A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003291348A AU2003291348A1 (en) 2002-10-31 2003-10-27 An improved barrier layer for a copper metallization layer including a low k dielectric

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10250889.5 2002-10-31
DE10250889A DE10250889B4 (de) 2002-10-31 2002-10-31 Verbesserte SiC-Barrierenschicht für eine Kupfermetallisierungsschicht mit einem Dielektrikum mit kleinem ε und Verfahren zur Herstellung derselben
US10/403,483 2003-03-31
US10/403,483 US6893956B2 (en) 2002-10-31 2003-03-31 Barrier layer for a copper metallization layer including a low-k dielectric

Publications (2)

Publication Number Publication Date
WO2004040623A2 WO2004040623A2 (fr) 2004-05-13
WO2004040623A3 true WO2004040623A3 (fr) 2004-07-15

Family

ID=32231869

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/035433 WO2004040623A2 (fr) 2002-10-31 2003-10-27 Couche de barriere amelioree pour une couche de metallisation de cuivre comprenant un dielectrique a faible valeur k

Country Status (2)

Country Link
AU (1) AU2003291348A1 (fr)
WO (1) WO2004040623A2 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6306758B1 (en) * 1998-08-14 2001-10-23 Advanced Micro Devices, Inc. Multipurpose graded silicon oxynitride cap layer
GB2365216A (en) * 2000-02-11 2002-02-13 Ibm Diffusion barrier layer for a semiconductor device
US6455417B1 (en) * 2001-07-05 2002-09-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming damascene structure employing bi-layer carbon doped silicon nitride/carbon doped silicon oxide etch stop layer
US20030003765A1 (en) * 2001-06-28 2003-01-02 Gibson Gerald W. Split barrier layer including nitrogen-containing portion and oxygen-containing portion
EP1284500A2 (fr) * 2001-08-17 2003-02-19 Canon Sales Co., Inc. Dispositif semiconducteur et procédé de sa fabrication
US20030102491A1 (en) * 2001-12-05 2003-06-05 Neng-Hui Yang Bilayer silicon carbide based barrier

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6306758B1 (en) * 1998-08-14 2001-10-23 Advanced Micro Devices, Inc. Multipurpose graded silicon oxynitride cap layer
GB2365216A (en) * 2000-02-11 2002-02-13 Ibm Diffusion barrier layer for a semiconductor device
US20030003765A1 (en) * 2001-06-28 2003-01-02 Gibson Gerald W. Split barrier layer including nitrogen-containing portion and oxygen-containing portion
US6455417B1 (en) * 2001-07-05 2002-09-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming damascene structure employing bi-layer carbon doped silicon nitride/carbon doped silicon oxide etch stop layer
EP1284500A2 (fr) * 2001-08-17 2003-02-19 Canon Sales Co., Inc. Dispositif semiconducteur et procédé de sa fabrication
US20030102491A1 (en) * 2001-12-05 2003-06-05 Neng-Hui Yang Bilayer silicon carbide based barrier

Also Published As

Publication number Publication date
AU2003291348A8 (en) 2004-05-25
AU2003291348A1 (en) 2004-05-25
WO2004040623A2 (fr) 2004-05-13

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