WO2004040623A2 - Couche de barriere amelioree pour une couche de metallisation de cuivre comprenant un dielectrique a faible valeur k - Google Patents

Couche de barriere amelioree pour une couche de metallisation de cuivre comprenant un dielectrique a faible valeur k Download PDF

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Publication number
WO2004040623A2
WO2004040623A2 PCT/US2003/035433 US0335433W WO2004040623A2 WO 2004040623 A2 WO2004040623 A2 WO 2004040623A2 US 0335433 W US0335433 W US 0335433W WO 2004040623 A2 WO2004040623 A2 WO 2004040623A2
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Prior art keywords
layer
nitrogen
low
metallization
barrier layer
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PCT/US2003/035433
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English (en)
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WO2004040623A3 (fr
Inventor
Hartmut Ruelke
Joerg Hohage
Thomas Werner
Massud Aminpur
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Advanced Micro Devices, Inc.
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Priority claimed from DE10250889A external-priority patent/DE10250889B4/de
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to AU2003291348A priority Critical patent/AU2003291348A1/en
Publication of WO2004040623A2 publication Critical patent/WO2004040623A2/fr
Publication of WO2004040623A3 publication Critical patent/WO2004040623A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas

Definitions

  • the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of metallization layers including highly conductive metals, such as copper, embedded into a dielectric material having low permittivity to enhance device performance.
  • metallization layers are formed by a dielectric layer stack including, for example, silicon dioxide and/or silicon nitride with aluminum as the typical metal. Since aluminum exhibits significant electromigration at higher current densities than may be necessary in integrated circuits having extremely scaled feature sizes, aluminum is being replaced by copper, which has a significantly lower electrical resistance and a higher resistivity against electromigration. For devices having feature sizes of 0.13 ⁇ m and less, it turns out that simply replacing aluminum with copper does not provide the required decrease of the parasitic RC time constants, and, therefore, the well-established and well-known dielectric materials, silicon dioxide (k approximately 4.2) and silicon nitride (k > 5), are increasingly replaced by so-called low-k dielectric materials.
  • damascene technique is employed in forming metallization layers including copper lines.
  • the dielectric layer is deposited and then patterned with trenches and vias that are subsequently filled with copper by plating methods, such as electroplating or electroless plating.
  • the damascene technique is presently a well-established technique for forming copper metallization layers in standard dielectric materials, such as silicon dioxide
  • standard dielectric materials such as silicon dioxide
  • the employment of low-k dielectrics requires the development of new dielectric diffusion barrier layers so as to avoid copper contamination of adjacent material layers, as copper readily diffuses in a plurality of dielectrics.
  • silicon nitride is known as an effective copper diffusion barrier
  • silicon nitride may not be considered appropriate in low-k dielectric layer stacks owing to its high permittivity. Therefore, silicon carbide is presently considered as a viable candidate for a copper diffusion barrier.
  • FIG. 100 shows a cross-sectional view of a semiconductor structure 100, in which a low-k dielectric material is to be patterned in accordance with a so-called via first/trench last process sequence, which is presently considered the most promising process scheme in patterning low-k dielectrics.
  • the semiconductor structure 100 comprises a substrate 101 that may include circuit elements, such as transistors, resistors, capacitors and the like, and which may include a lower metallization layer 102 including a metal region 103 embedded in a dielectric material 104.
  • the metal region 103 may comprise copper and the dielectric 104 may be a low-k dielectric, such as hydrogen- containing silicon oxycarbide (SiCOH).
  • a barrier layer 105 is formed of nitrogen containing silicon carbide (SiCN) which also serves as an etch stop layer in the following etch procedure for patterning an overlying low-k dielectric layer 106.
  • the low-k dielectric layer 106 may comprise, depending on the process sequence used, an intermediate silicon carbide etch stop layer 107, which in many applications may, however, be omitted for the benefit of a reduced total permittivity.
  • the low-k dielectric material in the layer 106 may comprise SiCOH.
  • a cap layer 108 for example comprised of oxide or provided as an anti-reflective coating (ARC), may optionally be located on the low-k dielectric layer 106 and may then serve as a stop layer in removing excess copper in a subsequent chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • a resist mask 109 including an opening 110 is formed above the optional cap layer 108.
  • a typical process flow for forming the semiconductor structure 100 may comprise the following steps. After planarizing the lower metallization layer 102, the barrier/etch stop layer 105 is deposited by, for example, a plasma enhanced chemical vapor deposition (PECVD) from trimethyl silane (3MS) and ammonia (NH 3 ) as precursor gases. Then, the hydrogen-containing silicon oxycarbide is deposited, wherein, if required, the silicon carbide layer 107 is formed when a first required thickness of the dielectric layer 106 is obtained. Thereafter, the residual layer 106 is deposited to achieve the required overall thickness of the layer 106.
  • PECVD plasma enhanced chemical vapor deposition
  • NH 3 ammonia
  • the cap layer 108 is deposited with a required thickness.
  • the cap layer 108 may help to substantially avoid any interaction of the low-k dielectric of the layer 106 with the overlying resist mask 109 and may serve as a CMP stop layer.
  • the resist mask 109 is patterned in accordance with well- established deep UV lithography techniques to form the opening 110 determining the dimensions of the vias to be formed within the dielectric layer 106.
  • Figure lb schematically shows the semiconductor structure 100 after an anisotropic etch process for forming a via 111 in the cap layer 108 and the dielectric layer 106.
  • the barrier/etch stop layer 105 exhibits a significantly lower etch rate than the surrounding dielectric layer 106, so that the etch process may be stopped in or on the layer 105.
  • the remaining photoresist not consumed during the anisotropic etch process is removed by an etch step in an oxygen-containing plasma ambient.
  • the nitrogen contained in the barrier/etch stop layer 105 may readily diffuse into the low-k dielectric of the layer 106 due to the desired porosity of this material. Since the cap layer 108 substantially prevents any diffusion from nitrogen or nitrogen-containing compounds into the overlying resist mask 109, the patterning of the opening 110 and the subsequent patterning of the via 111 is substantially not affected by any resist poisoning effects.
  • FIG. lc schematically shows the semiconductor structure 100 in an advanced manufacturing stage.
  • the via 111 is filled with an organic anti-reflective coating material so as to include a via plug 114, whereas the organic material is provided at the remaining surface of the structure 100 so as to form an anti-reflective coating layer 112 for the subsequent photolithography.
  • the plug 114 and the anti-reflective coating 112 serve to planarize the topography of the semiconductor structure 100 prior to the formation of a further photoresist mask
  • the photoresist mask 113 includes a trench opening 115 at the bottom of which resist residuals 116 are maintained.
  • the via plug 114 and the anti-reflective coating 112 may be formed by spin-on techniques and the like, and the photoresist mask 113 may be formed by sophisticated lithography methods, as are well known in the art. Contrary to the formation of the resist mask 109, nitrogen or nitrogen compounds may readily diffuse in the organic anti-reflective coating material and may now come into contact with the overlying photoresist 113, since the protecting cap layer 108 is open at the via 111. The interaction of nitrogen and compounds thereof with the photoresist may deteriorate the light sensitivity of the resist. Consequently, upon exposure and development of the photoresist 113 in forming the trench opening 115, the resist residuals 116 remain and significantly affect the following anisotropic etch step for forming a trench in the upper portion of the dielectric layer 106.
  • Figure Id schematically shows the semiconductor structure 100 after completion of the trench forming step.
  • the trench 117 that should have been formed in the dielectric layer 106 is substantially not transferred from the photoresist mask 113 to the underlying cap layer 108 and the upper portion of the dielectric layer 106.
  • the cap layer 108 and the dielectric layer 106 comprise substantially the via 111 without any trench in the upper portion of the layer 106.
  • a so-called bi-layer is commonly used for the photoresist mask 113, wherein a lower portion of the bi-layer may comprise silicon so as to reduce the interaction of the photoresist with up- diffusing nitrogen and nitrogen compounds.
  • Figure le schematically shows the semiconductor structure 100 after completion of the metallization layer 130, including a barrier metal layer 118 on inner sidewalls and the bottom of the via 111, which is filled with copper 119. Moreover, a surface 120 of the metallization layer 130 is planarized to allow the formation of a further metallization layer.
  • the barrier metal layer 118 may be deposited by physical vapor deposition, such as sputter deposition, with a thickness that insures sufficient protection against copper out-diffusion and at the same time provides a required adhesion to the surrounding low-k dielectric material.
  • a barrier metal layer 118 may be deposited by physical vapor deposition, such as sputter deposition, with a thickness that insures sufficient protection against copper out-diffusion and at the same time provides a required adhesion to the surrounding low-k dielectric material.
  • tantalum or tantalum nitride may be used as the material for the barrier metal layer 118.
  • a copper seed layer is deposited to promote the subsequent deposition of the bulk copper by electroplating.
  • the excess copper is removed by chemical mechanical polishing, wherein the cap layer 108 is also removed and acts as a stop layer to reliably control the CMP process.
  • the present invention is directed to a semiconductor device and a method that provides the required nitrogen concentration at a lower portion of a dielectric barrier/etch stop layer so as to provide for the advantageous electromigration behavior of an adjacent copper material, while an upper portion of the barrier/etch stop layer has a significantly reduced nitrogen concentration, wherein in some embodiments an upper surface of the etch stop layer may be substantially completely depleted from nitrogen.
  • a semiconductor structure comprises a low-k dielectric layer and a metal-containing region that is at least partially formed in the low-k dielectric layer. Moreover, a nitrogen-containing dielectric barrier layer having a first surface in contact with the low-k dielectric layer and a second surface partially in contact with the metal-containing region is provided, wherein a nitrogen concentration at the first surface is less than a nitrogen concentration at the second surface.
  • a metallization structure of an integrated circuit comprises a first metallization layer and a second metallization layer formed over the first metallization layer and including a low-k dielectric material.
  • a dielectric barrier layer containing nitrogen and located between the first and the second metallization layers is provided, wherein the dielectric barrier layer has a first interface in contact with the first metallization layer, and a second interface in contact with the second metallization layer, whereby a concentration of nitrogen decreases from the first interface towards the second interface.
  • a method of forming a metallization layer comprises depositing a low-k barrier layer over a substrate having formed thereon a metal region.
  • an incorporation of a diffusion barrier component into the low-k barrier layer is controlled such that a concentration of the diffusion barrier component is highest at a first surface of the low-k barrier layer, which faces the metal region, and is lowest at the second surface opposite to the first surface.
  • a low-k dielectric layer is deposited over the low-k barrier layer wherein a diffusion of the diffusion barrier component through the second surface is reduced.
  • a method of forming a low-k dielectric barrier layer over a metal region in a metallization structure comprises the deposition of a nitrogen-containing silicon carbide layer from silicon, carbon and nitrogen-containing precursor gases over a substrate having formed thereon the metal region. The feeding of the nitrogen-containing precursor gas is then discontinued to reduce the nitrogen concentration while depositing silicon carbide.
  • a method of forming a low-k dielectric barrier layer over a metal region in a metallization structure comprises depositing a first silicon carbide layer from silicon and carbon-containing precursor gases. Then, a nitrogen-containing plasma ambient is established to introduce nitrogen into the first silicon carbide layer. Thereafter, a second silicon carbide layer is deposited on the first silicon carbide layer.
  • Figures la-le schematically show cross-sectional views of a semiconductor structure including a low-k metallization layer, wherein trenches in the low-k dielectric are substantially not formed owing to resist poisoning in the dual damascene process;
  • Figure 2a schematically shows a semiconductor structure including a dielectric barrier/etch stop layer in accordance with one illustrative embodiment of the present invention
  • Figure 2b shows a diagram illustrating a nitrogen concentration in the barrier/etch stop layer of Figure 2a according to representative examples of the present invention
  • Figures 2c and 2d illustrate a barrier/etch stop layer in accordance with still other illustrative embodiments of the present invention
  • Figures 2e-2j depict a semiconductor structure during further process stages, wherein resist poisoning is significantly reduced due to the reduced or even substantially nitrogen-free interface between the barrier/etch stop layer according to the present invention and an overlying low-k dielectric material.
  • the present invention is based on investigations the inventors have performed in order to clarify the reasons for resist poisoning in a typical dual damascene process sequence.
  • the inventors confirmed that a reaction of amine species, that is, nitrogen hydrogen compounds (N-H ), created by diffusion of nitrogen into the overlying low-k dielectric, interact with the low-k dielectric and upon up-diffusion with the photoresist, even if provided as a bi-layer.
  • N-H nitrogen hydrogen compounds
  • the nitrogen in the barrier/etch stop layer is substantially confined to a region of the barrier/etch stop layer being in contact with underlying copper, thereby maintaining the superior barrier and adhesion characteristics, whereas an interface of the barrier/etch stop layer with the overlying low-k dielectric contains a minimum nitrogen concentration or is even substantially completely free of nitrogen.
  • a semiconductor structure 200 comprises a substrate 201 over which a first metallization layer 202 is formed.
  • the substrate 201 may include many circuit elements, such as transistors, resistors, capacitors and the like, wherein the first metallization layer 202 provides electrical contact to at least some of the circuit elements.
  • the first metallization layer 202 may represent the very first metallization layer or may represent any intermediate metallization layer over which one or more additional metallization layers are to be formed.
  • the first metalliza- tion layer 202 may include a first dielectric layer 204 with a first metal region 203 contained therein.
  • the first metal region 203 may be comprised of copper including a barrier diffusion layer provided between the dielectric material 204 and the copper of the first metal region 203.
  • a barrier/etch stop layer 250 has a first surface 251 and a second surface 252 in contact with the first metallization layer 202.
  • the barrier/etch stop layer 250 is comprised of silicon carbide that contains nitrogen, the concentration of which varies along a depth 253 of the layer 250.
  • the nitrogen concentration is highest at the surface 252 with a concentration of approximately 15-30% with respect to the silicon carbide, and then gradually, or step-wise, decreases in the direction 253, wherein a nitrogen concentration at the first surface 251 is significantly reduced and is less than approximately 1% or, in other embodiments, even less than approximately 0.1%.
  • Figure 2b schematically shows a graph illustrating the nitrogen concentration along the depth direction
  • Curve A represents the progression of the nitrogen concentration starting at approximately 20% at the second surface 252 and maintaining a relatively high level up to an intermediate thickness 254. The nitrogen concentration then rapidly drops to an insignificant amount before the first surface 251.
  • Curve B represents a gradual decrease of the nitrogen concentration, again starting at approximately 20%, with a substantially linear drop of the concentration to an amount of approximately 0.1% in the vicinity of the first surface 251.
  • Curve C represents a nitrogen concentration exhibiting a more rapid decrease in the first portion of the barrier/etch stop layer 250 so that a substantially lower nitrogen amount is prevailing in the upper portion of the layer 250 compared to curves A and B. It should be noted, however, that the progression of the nitrogen concentration may be adjusted according to a plurality of different profiles, as are considered appropriate for the specific application.
  • a typical process flow for manufacturing the semiconductor structure 200, as shown in Figure 2a, with the barrier/etch stop layer 250 having a varying concentration of a diffusion barrier component, such as nitrogen, may include the following steps.
  • the substrate 201 may be provided having already formed thereon the first metallization layer 202.
  • the formation of the first metallization layer 202 may comprise substantially the same steps as used for the formation of a subsequent metallization layer, as will be described in more detail later in this application and thus description thereof will be omitted here.
  • the barrier/etch stop layer 250 is deposited by, for example, plasma-enhanced CVD with a required thickness, for example, in the range of approximately 10-100 nm.
  • the amount of a nitrogen-containing precursor gas may be controlled so as to obtain a varying nitrogen concentration in the deposition ambient and, thus, in the deposited layer 250, as is for example shown in Figure 2b.
  • precursor gases trimethyl silane (3MS) and ammonia (NH 3 ) are used in combination with an inert gas, such as helium, to establish a reactive ambient for the deposition of a nitrogen- containing silicon carbide layer.
  • an inert gas such as helium
  • the ratio between trimethyl silane and ammonia substantially determines the amount of nitrogen incorporated into the silicon carbide layer 250.
  • the deposition may take place in any appropriate CVD process tool (not shown), which additionally allows the establishment of a plasma ambient.
  • the supply of ammonia may be reduced or may be discontinued so as to gradually decrease the amount of nitrogen incorporated into the remaining portion of the barrier/etch stop layer 250.
  • approximately 20-30 nm of silicon carbide including approximately 15-30% or even more nitrogen may be deposited, when the ammonia supply is discontinued, wherein approximately 20-30 nm of silicon carbide are further deposited, while only a reduced amount of nitrogen is incorporated due to residual, steadily dropping nitrogen level in the deposition ambient.
  • the remaining nitrogen is substantially completely consumed, an extremely low nitrogen concentration is obtained at the end of the deposition process, thereby leading to a very low nitrogen concentration at the first surface 251 or even a substantially nitrogen-free surface 251.
  • the time of reducing or discontinuing the ammonia supply a variety of different concentration profiles may be obtained.
  • the process parameters may be as follows: Gas flow of 3MS: Approximately 100-300 seem Gas flow of ammonia (NH 3 ): Approximately 200-500 seem
  • Temperature of the substrate 201 Approximately 320-360°C Pressure of the deposition ambient: Approximately 2-5 Torr
  • a silicon carbide film with a total thickness of approximately 40-80 nm and having a varying nitrogen concentration may be formed with a deposition time of approximately 10-30 seconds.
  • the JRF power during the deposition may be in the range from approximately 200-400 watts.
  • a helium plasma treatment may be carried out after completion of the deposition in order to density the first surface 251 of the barrier/etch stop layer 250.
  • the helium plasma treatment may be carried out at a temperature in the range of approximately 300-400°C for a duration of approximately 15-60 seconds.
  • the deposition of the layer 250 with a first portion of increased nitrogen concentration and a second portion with a decreased nitrogen concentration including the helium treatment may be carried out in the same process chamber without breaking the vacuum.
  • the barrier/etch stop layer 250 may be deposited to the intermediate thickness 254 and subsequently the deposition may be discontinued, for example, by interrupting the trimethyl silane and the ammonia supply, and a pump and purge step may be carried out to remove the precursor gases.
  • the silicon carbide deposition may be continued with trimethyl silane but without ammonia, so as to obtain a steeper decrease of the nitrogen concentration at the intermediate thickness 254.
  • the barrier/etch stop layer 250 may be considered as comprising two sub-layers having significantly differing nitrogen concentrations at the first and second surfaces 251 and 252.
  • the ammonia supply may be gradually reduced or step-wise reduced during the deposition so as to obtain a profile that is more like the profile represented by curve B in Figure 2b.
  • FIG. 2c a first portion of the barrier/etch stop layer 250, indicated as 250a, has been formed, whereas, contrary to the embodiments as described with reference to Figures 2a and 2b, the first portion 250a is deposited as a silicon carbide layer substantially without any nitrogen. During deposition of the first portion 250a, a thickness thereof may be controlled in accordance with design requirements for the barrier/etch stop layer 250.
  • a low power nitrogen plasma ambient 260 is established to incorporate nitrogen into the first portion 250a.
  • any appropriate process tool having the ability to generate a plasma ambient may be used.
  • the same deposition tool used for the plasma-enhanced deposition of the first portion 250a may be employed for generating the nitrogen plasma ambient 260.
  • a relatively low bias voltage may be applied between the plasma ambient 260 and the substrate 202, so that nitrogen ions impinge on the first portion 250a with relatively low kinetic energy, thereby substantially avoiding the penetration of nitrogen into the materials of the first metallization layer 202.
  • the incorporation of nitrogen into the first portion 250a is caused by a weak implantation and by the interaction of nitrogen radicals with the silicon and carbon in the first portion 250a.
  • a bias voltage in the range of approximately 5-100 volts, the penetration depth of nitrogen, and hence the concentration thereof, may be adjusted to any desired value.
  • the first portion 250a may be provided with a thickness in the range of 10-20 nm and a concentration of approximately 15-30% or more nitrogen may be incorporated by the nitrogen plasma ambient 260 so as to obtain a thickness of the first portion 250a of the barrier/etch stop layer 250 having the required electromigration and adhesion characteristics in conjunction with the underlying metal region 203.
  • the deposition of silicon carbide may be continued, for example, in the same process chamber or in a different chamber to form the barrier/etch stop layer 250 with the required final thickness. Since the penetration depth of nitrogen as substantially confined to surface portions of the first portion 250a, this embodiment is advantageous when a thin nitrogen-containing layer 250a is to be formed. Otherwise, a plurality of thin sub-layers 250a may be formed in accordance with the above-described process.
  • Figure 2d schematically shows the semiconductor structure 200 with the barrier/etch stop layer 250 having a second portion 250b in which a nitrogen concentration is minimal, as the deposition has been carried out substantially without any nitrogen-containing precursor gases.
  • the semiconductor structure 200 comprises a low-k dielectric layer 206 that may be comprised of a first layer and a second layer with an etch stop layer 207, for example formed of silicon carbide, interposed therebetween, whereas, in other embodiments, the etch stop layer 207 is omitted.
  • the low-k dielectric layer 206 is comprised of any appropriate dielectric material, such as silicon oxycarbide, and the like.
  • a cap layer 208 may optionally be formed over the dielectric layer 206 and a resist mask 209 having formed therein an opening 210 is formed over the cap layer 208.
  • the same processes may be employed as previously explained with reference to Figure la. It should be noted, however, that, due to the reduced nitrogen concentration at the first surface 251, the diffusion of nitrogen into the overlying low-k dielectric is significantly lower than in the corresponding prior art process flow. Thus, the dielecfric layer 206 comprises only a minimum amount of nitrogen and nifrogen compounds.
  • Figure 2g shows the semiconductor structure 200 after the anisotropic etch procedure for forming a via
  • the nifrogen concentration in the barrier/etch stop layer 250 is adjusted such that the concenfration essentially drops to the desired low value of approximately 1% or less within the remaining thickness 255. In this way, liberation of nitrogen during the etch process or in a subsequent fill process is suppressed.
  • a "localized" nitrogen concentration may be obtained by some of the embodiments described with reference to Figures 2b-2e. The process flow may be carried out similarly as already described with reference to Figure lb.
  • Figure 2h schematically depicts an advanced manufacturing stage, wherein the via 211 is filled with an organic anti-reflective coating material 214 to form a via plug and a corresponding anti-reflective layer 212 is formed on the dielectric layer 206.
  • a photoresist mask 213 having a trench opening 215 is formed over the anti-reflective layer 212, wherein, as previously noted, the photoresist mask 213 may be comprised of a bi-layer resist.
  • the small amounts of nitrogen and nitrogen compounds in the dielectric layer 206 diffusing up to the photoresist mask 213 may not be sufficient to cause any resist poisoning. Therefore, the trench opening 215 is substantially completely open and includes only an insignificant amount of resist residuals or is even substantially free of resist residuals.
  • Figure 2i shows the semiconductor structure 200 after anisotropically etching the upper portion of the dielectric layer 206 to form a trench 217 that substantially corresponds to the dimensions of the trench opening 215 in the photoresist mask 213. Etching the trench 217 and subsequently removing the anti-reflective coating
  • the barrier/etch stop layer 250 may be completely opened to provide a connection to the underlying metal region 203.
  • Figure 2j schematically shows the semiconductor structure 200 with a second metallization layer 230 formed over the first metallization layer 202 and partially separated therefrom by the barrier/etch stop layer 250.
  • a barrier metal layer 218 is formed inside the trench opening 217 and the via opening 211, wherein these openings are now filled with copper 219 so that an electrical connection is provided between the first metal region 203 and the trench 217.
  • the cap layer 208 is removed so that a substantially planar surface 220 is provided that may receive a further metallization layer, such as the second metallization layer
  • interface portions 221 of the barrier/etch stop layer 250 that are in contact with the first metal region 203 exhibit a sufficiently high nifrogen concenfration to provide for the required electromigration and adhesion characteristics, whereas, at the opposing first surface 251, a significantly reduced nifrogen concentration is still maintained.
  • metallization layers including low-k dielecfric materials and copper may be provided, wherein a significantly reduced nitrogen concentration of a barrier/etch stop layer required at an interface between two adjacent metallization layers ensures a minimal up-diffusion of nifrogen and nitrogen compounds so that resist poisoning may be efficiently reduced. Consequently, the formation of highly-scaled dual damascene metallization layers including copper may be achieved, without unduly decreasing production yield and device reliability.
  • the particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order.
  • no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention.

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Abstract

L'effet d'empoisonnement de resist peut être éliminé ou au moins sensiblement réduit dans la formation d'une couche de métallisation à faible valeur k, de sorte qu'une couche d'arrêt de gravure/barrière contenant de l'azote (250) présente une concentration en azote significativement réduite au niveau d'une interface (251) en contact avec ladite matière diélectrique à faible valeur k (206). Par conséquent, la diffusion de l'azote et de composés d'azote dans des trous formés dans ladite couche diélectrique à faible valeur k (206) est considérablement réduite, de sorte que, dans une étape de photolithographie ultérieure, une interaction entre l'azote et des composés d'azote, et le photoresist, est remarquablement réduite.
PCT/US2003/035433 2002-10-31 2003-10-27 Couche de barriere amelioree pour une couche de metallisation de cuivre comprenant un dielectrique a faible valeur k WO2004040623A2 (fr)

Priority Applications (1)

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AU2003291348A AU2003291348A1 (en) 2002-10-31 2003-10-27 An improved barrier layer for a copper metallization layer including a low k dielectric

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10250889.5 2002-10-31
DE10250889A DE10250889B4 (de) 2002-10-31 2002-10-31 Verbesserte SiC-Barrierenschicht für eine Kupfermetallisierungsschicht mit einem Dielektrikum mit kleinem ε und Verfahren zur Herstellung derselben
US10/403,483 2003-03-31
US10/403,483 US6893956B2 (en) 2002-10-31 2003-03-31 Barrier layer for a copper metallization layer including a low-k dielectric

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WO2004040623A2 true WO2004040623A2 (fr) 2004-05-13
WO2004040623A3 WO2004040623A3 (fr) 2004-07-15

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6306758B1 (en) * 1998-08-14 2001-10-23 Advanced Micro Devices, Inc. Multipurpose graded silicon oxynitride cap layer
GB2365216A (en) * 2000-02-11 2002-02-13 Ibm Diffusion barrier layer for a semiconductor device
US6455417B1 (en) * 2001-07-05 2002-09-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming damascene structure employing bi-layer carbon doped silicon nitride/carbon doped silicon oxide etch stop layer
US20030003765A1 (en) * 2001-06-28 2003-01-02 Gibson Gerald W. Split barrier layer including nitrogen-containing portion and oxygen-containing portion
EP1284500A2 (fr) * 2001-08-17 2003-02-19 Canon Sales Co., Inc. Dispositif semiconducteur et procédé de sa fabrication
US20030102491A1 (en) * 2001-12-05 2003-06-05 Neng-Hui Yang Bilayer silicon carbide based barrier

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6306758B1 (en) * 1998-08-14 2001-10-23 Advanced Micro Devices, Inc. Multipurpose graded silicon oxynitride cap layer
GB2365216A (en) * 2000-02-11 2002-02-13 Ibm Diffusion barrier layer for a semiconductor device
US20030003765A1 (en) * 2001-06-28 2003-01-02 Gibson Gerald W. Split barrier layer including nitrogen-containing portion and oxygen-containing portion
US6455417B1 (en) * 2001-07-05 2002-09-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming damascene structure employing bi-layer carbon doped silicon nitride/carbon doped silicon oxide etch stop layer
EP1284500A2 (fr) * 2001-08-17 2003-02-19 Canon Sales Co., Inc. Dispositif semiconducteur et procédé de sa fabrication
US20030102491A1 (en) * 2001-12-05 2003-06-05 Neng-Hui Yang Bilayer silicon carbide based barrier

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AU2003291348A8 (en) 2004-05-25
AU2003291348A1 (en) 2004-05-25
WO2004040623A3 (fr) 2004-07-15

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