WO2004038785A1 - Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor - Google Patents

Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor Download PDF

Info

Publication number
WO2004038785A1
WO2004038785A1 PCT/US2003/032687 US0332687W WO2004038785A1 WO 2004038785 A1 WO2004038785 A1 WO 2004038785A1 US 0332687 W US0332687 W US 0332687W WO 2004038785 A1 WO2004038785 A1 WO 2004038785A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
etch
band gap
contact
wide band
Prior art date
Application number
PCT/US2003/032687
Other languages
French (fr)
Other versions
WO2004038785A8 (en
Inventor
Colin S. Whelan
Elsa K. Tong
Original Assignee
Raytheon Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Company filed Critical Raytheon Company
Priority to EP03770763A priority Critical patent/EP1556889A1/en
Priority to JP2004546877A priority patent/JP4143068B2/en
Publication of WO2004038785A1 publication Critical patent/WO2004038785A1/en
Publication of WO2004038785A8 publication Critical patent/WO2004038785A8/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H01L29/7785—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with more than one donor layer

Definitions

  • This invention relates to high electron mobility transistors (HEMTs) and more particularly to self-aligned, double recess gate HEMTs.
  • HEMTs high electron mobility transistors
  • HEMT high electron mobility transistor
  • GaAs gallium arsenide
  • InP indium phosphide
  • One device which has been found to provide good device characteristics such as breakdown voltage, output currents, and pinch-off voltage is a double recessed HEMT. Such a device is fabricated with two aligned recesses in which the gate is formed.
  • the recesses are typically formed by wet etching the device.
  • the etching process is periodically interrupted and the device is tested for certain characteristics, e.g., current. If the characteristics meet the desired criteria, then etching for that recess is terminated. Otherwise, the etching continues. This process continues until both recesses meet the established criteria. This process takes time and money to repeatedly stop the etching and test the device. Also, the etching is not uniform across the wafer, resulting in inconsistent device characteristics across the wafer and low yield of acceptable devices on the wafer.
  • HEMTs High Electron Mobility Transistors
  • a single-beam write process is described in an article by Grundbacher et al, published in IEEE Electron Devices, Vol. 44, No. 12, Dec. 1997, pg. 2136-2142.
  • This process provides two recesses with a single-beam write.
  • the process uses a four-layer polymethylmethacrylate (PMMA) resist process with electron-beam written with two patterns on top of each other (i.e., the first recess and gate).
  • PMMA polymethylmethacrylate
  • the process requires a high density, low bias etcher (ECR, TCP, ICP) to minimize the damage to the Schottky layer by the accelerated ions used in the etching process.
  • ECR high density, low bias etcher
  • TCP low bias etcher
  • ICP accelerated ions used in the etching process.
  • the process has the disadvantage in that there must be concern of the erosion of the thin layers of PMMA used in their resist structure from ion bombardment.
  • liftoff of the PMMA (and therefore the gate metal on the resist) is relatively difficult after it has been hardened in the high temperature plasma.
  • a method for forming a double recess high electron mobility transistor.
  • the method includes providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer over the substrate; a relatively small band gap channel layer deposited on the relatively wide band gap layer; a second relatively wide band gap Schottky layer over the channel layer; an etch stop layer over the Schottky layer; a third relatively wide band gap layer disposed on the etch stop layer; and a doped ohmic contact layer disposed over the third relatively wide band gap layer.
  • a mask is provided having a gate contact aperture to expose a gate region of the contact layer.
  • a first wet chemical etch is brought into contact with portions of the contact layer exposed by the gate contact aperture.
  • the first wet chemical selectively removes exposed portions of the contact layer and underlying portions of the third relatively wide band gap layer.
  • the etch stop layer inhibits the first wet chemical etch from removing portions of such etch stop layer.
  • a second wet chemical etch is brought into contact with structure etched by the first wet chemical etch.
  • the second wet chemical etch selectively removes exposed portions of the contact layer while leaving substantially un-etched exposed portions of the third relatively wide band gap layer, and the etch stop layer.
  • a third wet chemical selectively removes the etch stop layer while leaving un-etched the donor layer and ohmic contact layer.
  • Metal is deposited over the mask and through gate aperture therein onto, and in Schottky contact with, the Schottky layer.
  • the etch stop layer comprises AlAs.
  • the channel layer comprises In x Ga ⁇ . x As (0 ⁇ X ⁇ 25%), or In x GaAs (30 ⁇ x ⁇ 70%).
  • the third relatively wide band gap layer comprises AIGaAs, InAlGaAs, or AlAs.
  • the Schottky contact layer comprises InAlAs, AIGaAs or InAlGaAs.
  • the ohmic contact layer comprises doped InGaAs or GaAs.
  • the first wet chemical etch is substantially 2.5pH citric acid: H 2 0 2 . In one embodiment, the first wet chemical etch is substantially 4.2 pH succinic acid: H 0 .
  • the second wet chemical etch is substantially 5.3 pH Succinic acid: H 2 0 2 .
  • the second wet chemical etch is substantially 6.4 pH citric acid: H 2 0 .
  • both the gate and first recess pattern By selectively etching both the gate and first recess pattern, non-uniformities are greatly diminished. Both the first recess and gate recess etches are performed using only one electron-beam pattern, such pattern being used to form the mask, thereby significantly reducing the cost and manufacturing time of the product. Finally, since both etches are performed using a single resist pattern provided in the mask, the gate recess is perfectly aligned (i.e., self -aligned) within the center of the first recess.
  • FIGS. 1A-1F are cross sectional drawings of a self-aligned, double recess gate GaAs pseudomorphic HEMT at various stages in the fabrication thereof; and Like reference symbols in the various drawings indicate like elements. DETAILED DESCRIPTION
  • a semiconductor structure 10 having a bottom, III-V, substrate, 12, here gallium arsenide.
  • a first relatively wide band gap layer 14, here AIGaAs is on the substrate 12.
  • an ultra thin silicon doped (pulse) layer 16 is formed in layer 14.
  • a 10-25 Angstrom thick AIGaAs spacer layer 18 is on layer 16.
  • a 75-400 Angstrom thick In x GaAs (0 ⁇ x ⁇ 25%) relatively small band gap channel layer 20 is on the layer 18.
  • a 10-25 Angstrom thick AIGaAs spacer layer 22 is on the layer 20.
  • an ultra thin silicon doped (pulse) layer 24 is formed in layer 22.
  • a 100-300 Angstrom thick AIGaAs relatively wide band gap Schottky layer 25 is on the layer 24.
  • a 10- 30 Angstrom thick AlAs etch stop layer 26 is on layer 25.
  • a 100-500 Angstrom thick layer relatively wide band gap layer 28 of AIGaAs is on the etch stop layer 26.
  • a 100-500 Angstrom thick, n+ doped, (here 10 17 to 8xlO I9 per cm 3 ) GaAs ohmic contact layer 30 is on layer 28.
  • a heterojunction is formed between the wide band gap Schottky layer 25 and the small band gap undoped channel layer 20. Due to the conduction band discontinuity at the heterojunction, electrons are injected from the Schottky /undoped spacer layer 25/22 into the undoped channel layer 20.
  • the surface of layer 33 (FIG. 1A) is coated with a sacrificial masking layer 34, here a three-layer PMMA resist or multiple optical resist layers.
  • the photoresist layer 34 has a lower portion 36 with the gate contact aperture 38 to expose a gate region 40 of the ohmic contact layer 30.
  • An upper portion 42 of layer 34 is vertically spaced from the lower portion 36 and has a gate electrode metalization aperture 44. Edges 46, 48, of the gate electrode metalization aperture 44 terminate in overhangs 50, 52 which expose the gate contact aperture 38 and surface portions 54, 56 of the lower portion 36 of the photoresist layer 34 adjacent to the gate contact aperture 38 for a metal liftoff profile.
  • the gate contact aperture 38 is here smaller than the gate electrode metalization aperture 44, so that a large, low resistance, metal layer can be added to the small, higher resistance, metal gate stem to be formed.
  • the shaped of layer 34 is formed in one of two ways: (1) When the three layer PMMA resist is used (i.e., a tri-level e-beam resist), such is exposed and developed to produce the shape shown in FIG. IB; or (2) when multiple optical resists is used, a thin single layer e-beam resist, followed by coating, exposing and developing an optical resist on top. Exposure of layer is peformed using electron-beam lithography or optical lithography tool. Development of exposed resist to form ⁇ 0.15 micrometer gate contact aperture 38. See for example: K. Alavi, D.
  • a selective wet chemical gate etch is applied to the surface of the structure shown in FIG. IB.
  • the wet chemical etch is 2.5 pH Citric Acid :H 2 0 2 (98:2) or alternatively 4.2 pH Succinic Acid: H 2 0 2 (15:1).
  • the etch isotropically removes exposed portions of layers 32 and 28 and continues down to the AlAs etch stop layer 26.
  • the resulting structure is shown in FIG. lC. '
  • a second selective wet chemical gate etch is applied to the surface of the structure shown in FIG. 1C.
  • the second wet gate etch is 5.3 pH Succinic Acid
  • a blanket of metal here thin Ti/Pt and then thick gold, is deposited, here evaporated, uniformly over the surface of the sacrificial layer 34 to form metal layer 60. It is noted that because of the vertical spacing between the lower and upper portions 36, 42 portions of the metal 60 on lower surface portions 36 of the sacrificial layer 34 are separated from the portions of the metal 60 on the upper portions 42 of the sacrificial layer 34, as shown in FIG. IE.
  • the PMMA or strip of conventional optical resist providing sacrificial layer 34 is lifted off, along with portion of the metal 60 thereon, leaving a double selectively etched, self-aligned double recess using only one resist pattern, as shown in FIG IF.
  • the remaining metal 60 shown in FIG. IF provides a gate electrode in Schottky contact with the Schottky contact layer 26.
  • Source and drain electrodes 62, 64 are formed in ohmic contact with layers 32 before or after the selective recess process, to complete the device pHEMT device.
  • MHEMT metamorphic high electron mobility transistor
  • the starting structure is a semiconductor structure having a bottom, III-V substrate, of GaAs for a metamorphic HEMT or InP for an InP HEMT.
  • a wide band gap layer of InAlAs or InAlGaAs is then grown.
  • a small band gap channel layer, here 150-Angstrom thick In x GaAs (30 ⁇ x ⁇ 70%) is disposed over and spaced from, the wide band gap layer.
  • a 10-30 Angstrom InAlAs or InAlGaAs spacer layer is disposed over, and spaced from, the channel layer.
  • a silicon pulse doping is disposed over such spacer layer.
  • a 100-300 Angstrom thick InAlAs or InAlGaAs wide band gap Schottky contact layer is disposed over, and spaced from, the Si pulse layer. Then a 10-30- Angstrom thick layer III-V etch stop layer of AlAs is disposed on the Schottky contact layer.
  • a 100-300 InAlAs or InAlGaAs wide band gap layer is disposed on the etch stop layer.
  • a 50-500 Angstrom thick n+ doped In x GaAs ohmic contact layer is disposed on layer.
  • the surface of the ohmic contact layer is coated with a sacrificial masking layer as layer 34 in FIG. IB.
  • a selective wet chemical gate etch is applied to the surface of the structure.
  • the wet chemical etch is 4.2 pH Succinic acid :H 2 0 2 (15: 1).
  • the etch isotropically removes exposed portions of the I ⁇ i ⁇ GaAs ohmic contact layer and the InAlAs or InAlGaAs layer and continues down to, but stops at, the AlAs etch stop layer.
  • a second selective wet chemical gate etch is applied to the surface of the structure.
  • the second wet gate etch is 5.3 pH Succinic Acid (SA): H 2 0 2 (6:1).
  • SA pH Succinic Acid
  • H 2 0 2 6:1
  • This second etch only removes exposed portions of the In x GaAs ohmic contact layer without etching the InAlAs or InAlGaAs donor layer or the etch stop layer. This is etched until the proper ( ⁇ - 0.4 - 1.0 micrometer) dimension, d, is achieved, as shown in FIG. 2D.
  • the stop layer is removed with dilute NFLiOH or HC1.
  • a blanket of metal is deposited, here evaporated, uniformly over the surface of the sacrificial layer as shown in FIG. IE.
  • the PMMA or strip of conventional optical resist providing sacrificial layer is lifted off, along with portion of the metal thereon, leaving a double selectively etched, self- aligned double recess using only one resist pattern.
  • the remaining metal provides a gate electrode in Schottky contact with the InAlAs or InAlGaAs Schottky layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Weting (AREA)

Abstract

A method is provided for forming a self-aligned, selectively etched, double recess high electron mobility transistor. The method includes providing a semiconductor structure having a III-V substrate (12); a first relatively wide band gap layer (14,18), a channel layer (20), a second relatively wide band gap Schottky layer (22,25) , an etch stop layer(26); a III-V third wide band gap layer (28) on etch stop layer; and an ohmic contact layer (30) on the third relatively wide band gap layer.

Description

METHOD OF FORMING A SELF-ALIGNED, SELECTIVELY ETCHED, DOUBLE RECESS HIGH ELECTRON MOBILITY TRANSISTOR
TECHNICAL FIELD
This invention relates to high electron mobility transistors (HEMTs) and more particularly to self-aligned, double recess gate HEMTs.
BACKGROUND As is known in the art, there are several types of active devices used at microwave and millimeter frequencies to provide amplification of radio frequency signals. In general, one of the more common semiconductor devices used at these frequencies is the high electron mobility transistor (HEMT). Typically, HEMTs are formed from Group III-V materials such as gallium arsenide (GaAs) or indium phosphide (InP). In a HEMT there is a doped donor/undoped spacer layer of one material and an undoped channel layer of a different material. A heterojunction is formed between the doped donor/undoped spacer layer and the undoped channel layer. Due to the conduction band discontinuity at the heterojunction, electrons are injected from the doped donor/undoped spacer layer into the undoped channel layer. Thus, electrons from the large bandgap donor layer are transferred into the narrow bandgap channel layer where they are confined to move only in a plane parallel to the heterojunction. Consequently, there is spatial separation between the donor atoms in the donor layer and the electrons in the channel layer resulting in low impurity scattering and good electron mobility. One device which has been found to provide good device characteristics such as breakdown voltage, output currents, and pinch-off voltage is a double recessed HEMT. Such a device is fabricated with two aligned recesses in which the gate is formed. The recesses are typically formed by wet etching the device. The etching process is periodically interrupted and the device is tested for certain characteristics, e.g., current. If the characteristics meet the desired criteria, then etching for that recess is terminated. Otherwise, the etching continues. This process continues until both recesses meet the established criteria. This process takes time and money to repeatedly stop the etching and test the device. Also, the etching is not uniform across the wafer, resulting in inconsistent device characteristics across the wafer and low yield of acceptable devices on the wafer.
Presently, there are other major problems impeding the fabrication of double recess High Electron Mobility Transistors (HEMTs). As the technology moves towards smaller dimensions for improved performance, the ability to place a 0.15 micron gate recess pattern within a 0.6 micron first recess pattern is becoming extremely difficult, if not impossible, due to the alignment capability certain electron beam lithography tools. If a tool has an alignment accuracy of 0.15 micrometers, then the overlay accuracy of two layers (first recess pattern and gate pattern) on top of one another is square root of (0.152+0.152) = 0.21 micrometers. Another e-beam lithography system has a better overlay accuracy of square root of (0.12+0.12) = 0.14 micrometers. These misalignments of a 0.15 micrometer gate recess pattern within the 0.6 micrometer first recess, often result in placement of the edge of the gate within 0.015-0.085 micrometer of the highly doped cap layer defined by the first recess. This results in very low device and circuit yields due to shorting. One solution would be to use extremely expensive optical steppers, which could place the gate pattern with a maximum misalignment of .04 microns. Secondly, the cost of 2 separate electron- beam writes (first recess and gate) results in a costly product, since these are the most expensive and time consuming steps of the entire process. Finally, the current gate etch technology is non-selective. The devices are gate etched and re-etched repeatedly until a desired current is met, resulting in non-uniformities across the wafer.
A single-beam write process is described in an article by Grundbacher et al, published in IEEE Electron Devices, Vol. 44, No. 12, Dec. 1997, pg. 2136-2142. This process provides two recesses with a single-beam write. However, the process uses a four-layer polymethylmethacrylate (PMMA) resist process with electron-beam written with two patterns on top of each other (i.e., the first recess and gate). The process would be very difficult to reproduce across a four-inch wafer and would require a relatively long writing time in order to pattern the wide first recess dimension. First the process requires a high density, low bias etcher (ECR, TCP, ICP) to minimize the damage to the Schottky layer by the accelerated ions used in the etching process. Secondly, the process has the disadvantage in that there must be concern of the erosion of the thin layers of PMMA used in their resist structure from ion bombardment. Finally, liftoff of the PMMA (and therefore the gate metal on the resist) is relatively difficult after it has been hardened in the high temperature plasma.
Other processes are described in U. S. Patent Nos. 4,616,400, 5,364,816, and 5,556,797 all of which describe processes where a single or multiples layers of resist are patterned a first wet or dry chemical etch is used. The resist layer(s) is then "pulled back" via non-directional plasma etching or redeveloping of the resist to increase it's original dimension. A second etch is then required.
SUMMARY
In accordance with the present invention, a method is provided for forming a double recess high electron mobility transistor. The method includes providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer over the substrate; a relatively small band gap channel layer deposited on the relatively wide band gap layer; a second relatively wide band gap Schottky layer over the channel layer; an etch stop layer over the Schottky layer; a third relatively wide band gap layer disposed on the etch stop layer; and a doped ohmic contact layer disposed over the third relatively wide band gap layer. A mask is provided having a gate contact aperture to expose a gate region of the contact layer. A first wet chemical etch is brought into contact with portions of the contact layer exposed by the gate contact aperture. The first wet chemical selectively removes exposed portions of the contact layer and underlying portions of the third relatively wide band gap layer. The etch stop layer inhibits the first wet chemical etch from removing portions of such etch stop layer. Next, a second wet chemical etch is brought into contact with structure etched by the first wet chemical etch. The second wet chemical etch selectively removes exposed portions of the contact layer while leaving substantially un-etched exposed portions of the third relatively wide band gap layer, and the etch stop layer. A third wet chemical selectively removes the etch stop layer while leaving un-etched the donor layer and ohmic contact layer. Metal is deposited over the mask and through gate aperture therein onto, and in Schottky contact with, the Schottky layer.
In one embodiment, the etch stop layer comprises AlAs. In one embodiment, the channel layer comprises InxGaι.xAs (0<X< 25%), or InxGaAs (30<x< 70%).
In one embodiment, the third relatively wide band gap layer comprises AIGaAs, InAlGaAs, or AlAs. In one embodiment, the Schottky contact layer comprises InAlAs, AIGaAs or InAlGaAs. In one embodiment, the ohmic contact layer comprises doped InGaAs or GaAs.
In one embodiment, the first wet chemical etch is substantially 2.5pH citric acid: H202. In one embodiment, the first wet chemical etch is substantially 4.2 pH succinic acid: H 0 .
In one embodiment, the second wet chemical etch is substantially 5.3 pH Succinic acid: H202.
In one embodiment, the second wet chemical etch is substantially 6.4 pH citric acid: H20 .
By selectively etching both the gate and first recess pattern, non-uniformities are greatly diminished. Both the first recess and gate recess etches are performed using only one electron-beam pattern, such pattern being used to form the mask, thereby significantly reducing the cost and manufacturing time of the product. Finally, since both etches are performed using a single resist pattern provided in the mask, the gate recess is perfectly aligned (i.e., self -aligned) within the center of the first recess.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
DESCRIPTION OF DRAWINGS
FIGS. 1A-1F are cross sectional drawings of a self-aligned, double recess gate GaAs pseudomorphic HEMT at various stages in the fabrication thereof; and Like reference symbols in the various drawings indicate like elements. DETAILED DESCRIPTION
Referring now to FIG. 1 A, a semiconductor structure 10 is shown having a bottom, III-V, substrate, 12, here gallium arsenide. A first relatively wide band gap layer 14, here AIGaAs is on the substrate 12. Here, an ultra thin silicon doped (pulse) layer 16 is formed in layer 14. A 10-25 Angstrom thick AIGaAs spacer layer 18 is on layer 16. A 75-400 Angstrom thick InxGaAs (0<x<25%) relatively small band gap channel layer 20 is on the layer 18. A 10-25 Angstrom thick AIGaAs spacer layer 22 is on the layer 20. Here, an ultra thin silicon doped (pulse) layer 24 is formed in layer 22. A 100-300 Angstrom thick AIGaAs relatively wide band gap Schottky layer 25 is on the layer 24. A 10- 30 Angstrom thick AlAs etch stop layer 26 is on layer 25. A 100-500 Angstrom thick layer relatively wide band gap layer 28 of AIGaAs is on the etch stop layer 26. A 100-500 Angstrom thick, n+ doped, (here 1017 to 8xlOI9per cm3) GaAs ohmic contact layer 30 is on layer 28. A heterojunction is formed between the wide band gap Schottky layer 25 and the small band gap undoped channel layer 20. Due to the conduction band discontinuity at the heterojunction, electrons are injected from the Schottky /undoped spacer layer 25/22 into the undoped channel layer 20.
Next, referring to FIG. IB, the surface of layer 33 (FIG. 1A) is coated with a sacrificial masking layer 34, here a three-layer PMMA resist or multiple optical resist layers. The photoresist layer 34 has a lower portion 36 with the gate contact aperture 38 to expose a gate region 40 of the ohmic contact layer 30. An upper portion 42 of layer 34 is vertically spaced from the lower portion 36 and has a gate electrode metalization aperture 44. Edges 46, 48, of the gate electrode metalization aperture 44 terminate in overhangs 50, 52 which expose the gate contact aperture 38 and surface portions 54, 56 of the lower portion 36 of the photoresist layer 34 adjacent to the gate contact aperture 38 for a metal liftoff profile. The gate contact aperture 38 is here smaller than the gate electrode metalization aperture 44, so that a large, low resistance, metal layer can be added to the small, higher resistance, metal gate stem to be formed. The shaped of layer 34 is formed in one of two ways: (1) When the three layer PMMA resist is used (i.e., a tri-level e-beam resist), such is exposed and developed to produce the shape shown in FIG. IB; or (2) when multiple optical resists is used, a thin single layer e-beam resist, followed by coating, exposing and developing an optical resist on top. Exposure of layer is peformed using electron-beam lithography or optical lithography tool. Development of exposed resist to form ~0.15 micrometer gate contact aperture 38. See for example: K. Alavi, D. Shaw, A. Platzker, B. Rizzi, S. Ogut, and R. Puente, "A very high performance, high yield, and high throughput millimeter wave power pHEMT process technology," published in GaAs MANTECH Technical Digest, May 2001, pp. 105-107.
After forming the layer 34 as shown in FIG. IB, a selective wet chemical gate etch is applied to the surface of the structure shown in FIG. IB. Here, the wet chemical etch is 2.5 pH Citric Acid :H202 (98:2) or alternatively 4.2 pH Succinic Acid: H202 (15:1). The etch isotropically removes exposed portions of layers 32 and 28 and continues down to the AlAs etch stop layer 26. The resulting structure is shown in FIG. lC. '
Next, a second selective wet chemical gate etch is applied to the surface of the structure shown in FIG. 1C. Here, the second wet gate etch is 5.3 pH Succinic Acid
(SA): H202 (6:1) or 6.4 pH citric acid: H20 . This second etch only removes exposed portions of the GaAs layer 30 without etching AIGaAs layer 28 or AlAs layer 26. This is etched until the proper (~ 0.4 - 1.0 micrometer) dimension, d, is achieved, as shown in FIG. ID. Finally, dilute (5%) NH OH or HC1 is used to remove exposed portions of the AlAs etch stop layer 26, such wet etch leaving substantially un-etched layers 28 and 30 as shown in FIG. IE.
Next, a blanket of metal, here thin Ti/Pt and then thick gold, is deposited, here evaporated, uniformly over the surface of the sacrificial layer 34 to form metal layer 60. It is noted that because of the vertical spacing between the lower and upper portions 36, 42 portions of the metal 60 on lower surface portions 36 of the sacrificial layer 34 are separated from the portions of the metal 60 on the upper portions 42 of the sacrificial layer 34, as shown in FIG. IE.
After the metal deposition, the PMMA or strip of conventional optical resist providing sacrificial layer 34 is lifted off, along with portion of the metal 60 thereon, leaving a double selectively etched, self-aligned double recess using only one resist pattern, as shown in FIG IF. Thus, the remaining metal 60 shown in FIG. IF provides a gate electrode in Schottky contact with the Schottky contact layer 26. Source and drain electrodes 62, 64 are formed in ohmic contact with layers 32 before or after the selective recess process, to complete the device pHEMT device.
It is to be noted that the identical process can be applied, with the exception of using only succinic acid, to another layer structure. For example, formation of a metamorphic high electron mobility transistor (MHEMT) layer structure or an InP
HEMT. Thus, here the starting structure is a semiconductor structure having a bottom, III-V substrate, of GaAs for a metamorphic HEMT or InP for an InP HEMT. A wide band gap layer of InAlAs or InAlGaAs is then grown. A small band gap channel layer, here 150-Angstrom thick InxGaAs (30<x<70%) is disposed over and spaced from, the wide band gap layer. A 10-30 Angstrom InAlAs or InAlGaAs spacer layer is disposed over, and spaced from, the channel layer. A silicon pulse doping is disposed over such spacer layer. A 100-300 Angstrom thick InAlAs or InAlGaAs wide band gap Schottky contact layer is disposed over, and spaced from, the Si pulse layer. Then a 10-30- Angstrom thick layer III-V etch stop layer of AlAs is disposed on the Schottky contact layer. A 100-300 InAlAs or InAlGaAs wide band gap layer is disposed on the etch stop layer. A 50-500 Angstrom thick n+ doped InxGaAs ohmic contact layer is disposed on layer.
Again, the surface of the ohmic contact layer is coated with a sacrificial masking layer as layer 34 in FIG. IB. After forming the sacrificial masking layer, a selective wet chemical gate etch is applied to the surface of the structure. Here, the wet chemical etch is 4.2 pH Succinic acid :H202 (15: 1). The etch isotropically removes exposed portions of the IιiχGaAs ohmic contact layer and the InAlAs or InAlGaAs layer and continues down to, but stops at, the AlAs etch stop layer. Next, a second selective wet chemical gate etch is applied to the surface of the structure. Here, the second wet gate etch is 5.3 pH Succinic Acid (SA): H202 (6:1). This second etch only removes exposed portions of the InxGaAs ohmic contact layer without etching the InAlAs or InAlGaAs donor layer or the etch stop layer. This is etched until the proper (~- 0.4 - 1.0 micrometer) dimension, d, is achieved, as shown in FIG. 2D. Finally, the stop layer is removed with dilute NFLiOH or HC1.
Next, a blanket of metal is deposited, here evaporated, uniformly over the surface of the sacrificial layer as shown in FIG. IE. After the metal deposition, the PMMA or strip of conventional optical resist providing sacrificial layer is lifted off, along with portion of the metal thereon, leaving a double selectively etched, self- aligned double recess using only one resist pattern. Thus, the remaining metal provides a gate electrode in Schottky contact with the InAlAs or InAlGaAs Schottky layer.
A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.

Claims

WHAT IS CLAIMED IS:
1. A method for forming a double recess high electron mobility transistor, comprising: providing a semiconductor structure having a III-V substrate; a wide band gap layer; a small band gap channel layer; a wideband gap Schottky layer; an etch stop layer; a wide band gap layer; and a contact layer. providing a mask, such mask having a gate contact aperture to expose a gate region of the contact layer; bringing a first wet chemical etch into contact with portions of the contact layer exposed by the gate contact aperture, such etch selectively removing exposed portions of the contact layer and underlying portions of the top wide band gap layer, such etch stop layer inhibiting such etch from removing portions of such etch stop layer; bringing a second wet chemical etch into contact with structure etched by the first wet etch, such second etch selectively removing exposed portions of the contact layer while leaving substantially un-etched exposed portions of the wide band gap and the etch stop layer; and removing the etch stop layer; depositing a metal layer over the mask and through gate aperture therein onto, and in Schottky contact with the Schottky contact layer.
2. The method recited in claim 1 wherein the etch stop layer comprises an AlAs.
3. The method recited in claim 2 wherein the channel layer comprises InGaAs.
4. The method recited in claim 3 wherein the third relatively wide band gap layer comprises AIGaAs, InAlAs or InAlGaAs.
5. The method recited in claim 2 wherein the Schottky contact layer comprises InAlAs, InAlGaAs or AIGaAs.
6. The method recited in claim 5 wherein the ohmic contact layer is InGaAs or GaAs.
7. The method recited in claim 5 wherein the first wet chemical etch is substantially
2.5pH acid:H202 or 4.2 pH succinic acid: H202.
8. The method recited in claim 5 wherein the second wet chemical etch is substantially 5.3 pH Succinic acid: H202 or 6.4 pH citric acid: H202
9. A method for forming a double recess high electron mobility transistor, comprising: providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer; a relatively small band gap channel layer, a second relatively wide band gap layer, an etch stop layer over the substrate; a III-V Schottky layer on etch stop layer; a third relatively wide band gap layer on the etch stop layer; and an ohmic contact layer on the third relatively wide band gap layer; providing a mask on over the ohmic contact layer, such mask having a lower portion with a gate contact aperture exposing a gate region of the channel layer; an upper portion vertically spaced from the lower portion and having a gate electrode metalization aperture; edges of the gate electrode metalization aperture terminating in overhangs which expose the gate contact aperture; surface portions of the lower portion of the mask being disposed adjacent to the gate contact aperture; bringing a first wet chemical etch into contact with portions of the ohmic contact layer exposed by the gate contact aperture, such etch selectively removing exposed portions of the ohmic contact layer and underlying portions of the third relatively wide band gap layer, such etch stop layer inhibiting such etch from removing portions of such etch stop layer; bringing a second wet chemical etch into contact with structure etched by the first wet etch, such second etch selectively removing exposed portions of the ohmic contact layer while leaving substantially un-etched exposed portions of the third wide band gap layer and the etch stop layer; removing the etch stop layer; depositing a metal layer over the mask, such metal being deposited on the upper portion thereof, through the gate electrode metalization aperture, through the gate contact aperture, and through gate aperture onto, and in Schottky contact with, the Schottky contact layer; and lifting portions mask to remove portions of the metal disposed onto the upper surface of the mask while leaving portions of the deposited metal to provide a gate electrode for the transistor.
10. The method recited in claim 9 wherein the etch stop layer comprises AlAs.
11. The method recited in claim 10 wherein the channel layer comprises InGaAs.
12. The method recited in claim 11 wherein the wide band gap layer comprises AIGaAs, InAlGaAs, InAlAs.
13. The method recited in claim 10 wherein the channel layer Schottky contact layer comprises InAlGaAs, InAlAs or AIGaAs .
14. The method recited in claim 13 wherein the ohmic contact layer comprises InGaAs or GaAs.
15. The method recited in claim 14 wherein the first wet chemical etch is substantially 2.5pH citric acid: H202.
16. The method recited in claim 14 wherein the second wet chemical etch is substantially 5.3 pH Succinic acid: H20 .
17. The method recited in claim 13 wherein the first wet chemical etch is substantially 4.2 pH succinic acid: H20 .
18. The method recited in claim 17 wherein the second wet chemical etch is substantially 6.4 pH citric acid: H20 .
PCT/US2003/032687 2002-10-24 2003-10-14 Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor WO2004038785A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP03770763A EP1556889A1 (en) 2002-10-24 2003-10-14 Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor
JP2004546877A JP4143068B2 (en) 2002-10-24 2003-10-14 Method of manufacturing selectively etched self-aligned double recess high electron mobility transistors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/279,358 US6838325B2 (en) 2002-10-24 2002-10-24 Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor
US10/279,358 2002-10-24

Publications (2)

Publication Number Publication Date
WO2004038785A1 true WO2004038785A1 (en) 2004-05-06
WO2004038785A8 WO2004038785A8 (en) 2005-04-07

Family

ID=32106687

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/032687 WO2004038785A1 (en) 2002-10-24 2003-10-14 Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor

Country Status (6)

Country Link
US (1) US6838325B2 (en)
EP (1) EP1556889A1 (en)
JP (1) JP4143068B2 (en)
KR (1) KR100985214B1 (en)
TW (1) TWI277145B (en)
WO (1) WO2004038785A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100418199C (en) * 2004-07-28 2008-09-10 中国科学院半导体研究所 Method for fabricating transistor of aluminum-gallium-nitrogen/gallium nitride with high electron mobility

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7501669B2 (en) 2003-09-09 2009-03-10 Cree, Inc. Wide bandgap transistor devices with field plates
US7573078B2 (en) * 2004-05-11 2009-08-11 Cree, Inc. Wide bandgap transistors with multiple field plates
US7550783B2 (en) * 2004-05-11 2009-06-23 Cree, Inc. Wide bandgap HEMTs with source connected field plates
US9773877B2 (en) * 2004-05-13 2017-09-26 Cree, Inc. Wide bandgap field effect transistors with source connected field plates
US7229903B2 (en) * 2004-08-25 2007-06-12 Freescale Semiconductor, Inc. Recessed semiconductor device
WO2006083383A2 (en) * 2004-12-01 2006-08-10 Bae Systems Information And Electronic Systems Integration, Inc. Low temperature grown insulated gate phemt device
US11791385B2 (en) * 2005-03-11 2023-10-17 Wolfspeed, Inc. Wide bandgap transistors with gate-source field plates
KR100631051B1 (en) * 2005-09-12 2006-10-04 한국전자통신연구원 Method for fabricating a pseudomorphic high electron mobility transistor
KR100695670B1 (en) * 2005-12-06 2007-03-16 재단법인서울대학교산학협력재단 Method for offset wide-recess of High electron mobility transistors
DE102005059231B4 (en) * 2005-12-12 2011-01-13 Infineon Technologies Ag A method of fabricating a compound semiconductor field effect transistor having a fin structure and compound semiconductor field effect transistor having a fin structure
TWI288979B (en) * 2006-02-23 2007-10-21 Arima Optoelectronics Corp Light emitting diode bonded with metal diffusion and manufacturing method thereof
DE102006022508A1 (en) 2006-05-15 2007-11-22 United Monolithic Semiconductors Gmbh A method of manufacturing a semiconductor device having a metallic gate electrode arranged in a double trench structure
DE102006022507A1 (en) * 2006-05-15 2007-11-22 United Monolithic Semiconductors Gmbh A method of manufacturing a semiconductor device having a metallic gate electrode arranged in a double trench structure
US7534672B1 (en) 2006-09-08 2009-05-19 Hrl Laboratories, Llc Tiered gate device with source and drain extensions
US7608497B1 (en) 2006-09-08 2009-10-27 Ivan Milosavljevic Passivated tiered gate structure transistor and fabrication method
US8283699B2 (en) * 2006-11-13 2012-10-09 Cree, Inc. GaN based HEMTs with buried field plates
KR100853166B1 (en) * 2007-01-30 2008-08-20 포항공과대학교 산학협력단 A method for the fabrication of field effect type compound semiconductor
JP2010050204A (en) * 2008-08-20 2010-03-04 Oki Semiconductor Co Ltd Method of manufacturing semiconductor element
KR101243836B1 (en) * 2009-09-04 2013-03-20 한국전자통신연구원 Semiconductor devices and methods forming thereof
JP2013131650A (en) * 2011-12-21 2013-07-04 Fujitsu Ltd Semiconductor device and method of manufacturing the same
KR101903509B1 (en) * 2012-07-11 2018-10-05 한국전자통신연구원 Method of making field effect type compound semiconductor device
US9679981B2 (en) 2013-06-09 2017-06-13 Cree, Inc. Cascode structures for GaN HEMTs
US9847411B2 (en) 2013-06-09 2017-12-19 Cree, Inc. Recessed field plate transistor structures
US9583589B1 (en) 2015-10-14 2017-02-28 Northrop Grumman Systems Corporation Self-aligned double gate recess for semiconductor field effect transistors
US9461159B1 (en) 2016-01-14 2016-10-04 Northrop Grumman Systems Corporation Self-stop gate recess etching process for semiconductor field effect transistors
US20190267480A1 (en) * 2018-02-26 2019-08-29 Duet Microelectronics Inc. Anti-barrier-conduction (abc) spacers for high electron-mobility transistors (hemts)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504353A (en) * 1994-06-06 1996-04-02 Nec Corporation Field effect transistor
JPH0945894A (en) * 1995-07-27 1997-02-14 Nec Corp Manufacture of field-effect transistor
EP0855748A1 (en) * 1997-01-23 1998-07-29 Nippon Telegraph And Telephone Corporation Heterojunction field effect transistor and method of fabricating the same
DE19827901A1 (en) * 1997-07-18 1999-01-28 Mitsubishi Electric Corp Recessed gate semiconductor device production
US6180968B1 (en) * 1996-05-31 2001-01-30 Nec Corporation Compound semiconductor device and method of manufacturing the same
US6242293B1 (en) * 1998-06-30 2001-06-05 The Whitaker Corporation Process for fabricating double recess pseudomorphic high electron mobility transistor structures

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4616400A (en) * 1984-12-21 1986-10-14 Texas Instruments Incorporated Process for fabricating a double recess channel field effect transistor
US4908325A (en) * 1985-09-15 1990-03-13 Trw Inc. Method of making heterojunction transistors with wide band-gap stop etch layer
US4839310A (en) * 1988-01-27 1989-06-13 Massachusetts Institute Of Technology High mobility transistor with opposed-gates
JPH02148740A (en) * 1988-11-29 1990-06-07 Fujitsu Ltd Semiconductor device and manufacture thereof
JPH04260338A (en) 1991-02-14 1992-09-16 Mitsubishi Electric Corp Manufacture of semiconductor device
US5140386A (en) * 1991-05-09 1992-08-18 Raytheon Company High electron mobility transistor
US5364816A (en) * 1993-01-29 1994-11-15 The United States Of America As Represented By The Secretary Of The Navy Fabrication method for III-V heterostructure field-effect transistors
DE69511958T2 (en) * 1994-06-29 2000-03-30 Koninkl Philips Electronics Nv Method for producing a semiconductor device with at least two field effect transistors with different pinch-off voltages
US5556797A (en) 1995-05-30 1996-09-17 Hughes Aircraft Company Method of fabricating a self-aligned double recess gate profile
US6194747B1 (en) 1997-09-29 2001-02-27 Nec Corporation Field effect transistor
US6060402A (en) * 1998-07-23 2000-05-09 The Whitaker Corporation Process for selective recess etching of epitaxial field effect transistors with a novel etch-stop layer
US6258639B1 (en) * 1999-05-21 2001-07-10 Agilent Technologies, Inc. Sintered gate schottky barrier fet passivated by a degradation-stop layer
JP3371871B2 (en) * 1999-11-16 2003-01-27 日本電気株式会社 Method for manufacturing semiconductor device
US6797994B1 (en) * 2000-02-14 2004-09-28 Raytheon Company Double recessed transistor
US6586113B1 (en) * 2000-07-19 2003-07-01 Agilent Technologies, Inc. Etching heterojunction interfaces
US6524899B1 (en) * 2000-09-21 2003-02-25 Trw Inc. Process for forming a large area, high gate current HEMT diode

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504353A (en) * 1994-06-06 1996-04-02 Nec Corporation Field effect transistor
JPH0945894A (en) * 1995-07-27 1997-02-14 Nec Corp Manufacture of field-effect transistor
US6180968B1 (en) * 1996-05-31 2001-01-30 Nec Corporation Compound semiconductor device and method of manufacturing the same
EP0855748A1 (en) * 1997-01-23 1998-07-29 Nippon Telegraph And Telephone Corporation Heterojunction field effect transistor and method of fabricating the same
DE19827901A1 (en) * 1997-07-18 1999-01-28 Mitsubishi Electric Corp Recessed gate semiconductor device production
US6242293B1 (en) * 1998-06-30 2001-06-05 The Whitaker Corporation Process for fabricating double recess pseudomorphic high electron mobility transistor structures

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 06 30 June 1997 (1997-06-30) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100418199C (en) * 2004-07-28 2008-09-10 中国科学院半导体研究所 Method for fabricating transistor of aluminum-gallium-nitrogen/gallium nitride with high electron mobility

Also Published As

Publication number Publication date
EP1556889A1 (en) 2005-07-27
US20040082158A1 (en) 2004-04-29
JP2006504269A (en) 2006-02-02
WO2004038785A8 (en) 2005-04-07
KR20050051650A (en) 2005-06-01
TWI277145B (en) 2007-03-21
US6838325B2 (en) 2005-01-04
KR100985214B1 (en) 2010-10-05
TW200414325A (en) 2004-08-01
JP4143068B2 (en) 2008-09-03

Similar Documents

Publication Publication Date Title
US6838325B2 (en) Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor
US5698870A (en) High electron mobility transistor (HEMT) and pseudomorphic high electron mobility transistor (PHEMT) devices with single layer integrated metal
US7183149B2 (en) Method of manufacturing field effect transistor
US5856217A (en) Modulation-doped field-effect transistors and fabrication processes
US4679311A (en) Method of fabricating self-aligned field-effect transistor having t-shaped gate electrode, sub-micron gate length and variable drain to gate spacing
US5976920A (en) Single layer integrated metal process for high electron mobility transistor (HEMT) and pseudomorphic high electron mobility transistor (PHEMT)
US20080124852A1 (en) Method of forming T- or gamma-shaped electrode
US8304332B2 (en) Structure and method for fabrication of field effect transistor gates with or without field plates
WO2008057179A2 (en) Atomic layer deposition in the formation of gate structures for iii-v semiconductor
US6087207A (en) Method of making pseudomorphic high electron mobility transistors
JP3233207B2 (en) Method for manufacturing field effect transistor
US4616400A (en) Process for fabricating a double recess channel field effect transistor
EP0892441B1 (en) Method for manufacturing a field effect transistor with recessed gate
US5231040A (en) Method of making a field effect transistor
JPS59205765A (en) Manufacture of semiconductor device
KR100264532B1 (en) Method for forming fets having their respective mode or threshold voltage
JPS6323669B2 (en)
Wakejima et al. A High Gain and High Yield 0.14 μm Au/WSi Buried Gate HJFET Technology with Directly Dry-etched SiO2 Openings
JPS62115782A (en) Manufacture of semiconductor device
EP0613174A2 (en) Method for making fine-line semiconductor devices
KR19990075338A (en) T-gate fabrication method of a water-doped high electron mobility transistor
JPH05326564A (en) Field effect transistor and manufacture thereof
JPH10209180A (en) Manufacture of semiconductor device
JPH0217933B2 (en)
JPH01225172A (en) Semiconductor device and manufacture thereof

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1020057003258

Country of ref document: KR

CFP Corrected version of a pamphlet front page
CR1 Correction of entry in section i

Free format text: IN PCT GAZETTE 19/2004 ADD "DECLARATION UNDER RULE 4.17: - AS TO THE APPLICANT S ENTITLEMENT TO CLAIM THE PRIORITY OF THE EARLIER APPLICATION (RULE 4.17(III)) FOR ALL DESIGNATIONS."

WWE Wipo information: entry into national phase

Ref document number: 2004546877

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 2003770763

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1020057003258

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2003770763

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 2003770763

Country of ref document: EP