WO2004027866A3 - Procede d'etablissement d'une liaison dans un substrat metallique integre - Google Patents

Procede d'etablissement d'une liaison dans un substrat metallique integre Download PDF

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Publication number
WO2004027866A3
WO2004027866A3 PCT/FR2003/002599 FR0302599W WO2004027866A3 WO 2004027866 A3 WO2004027866 A3 WO 2004027866A3 FR 0302599 W FR0302599 W FR 0302599W WO 2004027866 A3 WO2004027866 A3 WO 2004027866A3
Authority
WO
WIPO (PCT)
Prior art keywords
creating
link
metal substrate
integrated metal
metallic layer
Prior art date
Application number
PCT/FR2003/002599
Other languages
English (en)
Other versions
WO2004027866A8 (fr
WO2004027866A2 (fr
Inventor
Michel Hernandez
Daniel Marteau
Original Assignee
Johnson Controls Tech Co
Michel Hernandez
Daniel Marteau
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Johnson Controls Tech Co, Michel Hernandez, Daniel Marteau filed Critical Johnson Controls Tech Co
Publication of WO2004027866A2 publication Critical patent/WO2004027866A2/fr
Publication of WO2004027866A3 publication Critical patent/WO2004027866A3/fr
Publication of WO2004027866A8 publication Critical patent/WO2004027866A8/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0305—Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0382—Continuously deformed conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0385—Displaced conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09554—Via connected to metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0195—Tool for a process not provided for in H05K3/00, e.g. tool for handling objects using suction, for deforming objects, for applying local pressure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections

Abstract

L'invention concerne un procédé d'établissement d'une liaison dans un substrat métallique intégré comportant une première couche métallique (300) et une deuxième couche métallique (100) séparées par une couche isolante (200), comportant l'étape de découper une portion (22) de la première couche métallique (300) et une portion correspondante de la couche isolante (23) et à enfoncer ces portions dans la seconde couche métallique (100).
PCT/FR2003/002599 2002-09-23 2003-08-28 Procede d'etablissement d'une liaison dans un substrat metallique integre WO2004027866A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0211728 2002-09-23
FR0211728 2002-09-23

Publications (3)

Publication Number Publication Date
WO2004027866A2 WO2004027866A2 (fr) 2004-04-01
WO2004027866A3 true WO2004027866A3 (fr) 2004-08-19
WO2004027866A8 WO2004027866A8 (fr) 2005-04-28

Family

ID=32011319

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2003/002599 WO2004027866A2 (fr) 2002-09-23 2003-08-28 Procede d'etablissement d'une liaison dans un substrat metallique integre

Country Status (1)

Country Link
WO (1) WO2004027866A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5430422B2 (ja) * 2010-01-27 2014-02-26 日本発條株式会社 金属ベース回路基板の製造方法及び金属ベース回路基板

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1483563A (fr) * 1965-06-16 1967-06-02 Ibm Procédé de réalisation de connexions électriques au moyen de perforations
DE2734461A1 (de) * 1977-07-30 1979-02-08 Grundig Emv Verfahren zur gleichzeitigen herstellung einer vielzahl elektrischer kontaktstellen
WO1993026144A1 (fr) * 1992-06-15 1993-12-23 Dyconex Patente Ag Procede pour la production de points de contact ulterieurement conditionnables sur des supports de circuit, ainsi que supports de circuit pourvus de tels points de contact.
JPH0851267A (ja) * 1994-08-08 1996-02-20 Sankyo Seiki Mfg Co Ltd 回路基板及びその製造方法
JPH08228056A (ja) * 1995-02-21 1996-09-03 Denki Kagaku Kogyo Kk 金属ベース回路基板
DE19522338A1 (de) * 1995-06-20 1997-01-02 Fraunhofer Ges Forschung Verfahren zur Herstellung einer Durchkontaktierung sowie Chipträger und Chipträgeranordnung mit einer Durchkontaktierung
EP1107654A1 (fr) * 1999-05-25 2001-06-13 Mitsui Mining & Smelting Co., Ltd. Feuille pour carte de circuits imprimes, procede de formation de trou d'interconnexion, feuille de resine a trou d'interconnexion charge, carte de circuits imprimes et procede de fabrication associe
US20010022236A1 (en) * 2000-02-18 2001-09-20 Thilo Stolze Substrate for power semiconductor modules with through-plating of solder and method for its production

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1483563A (fr) * 1965-06-16 1967-06-02 Ibm Procédé de réalisation de connexions électriques au moyen de perforations
DE2734461A1 (de) * 1977-07-30 1979-02-08 Grundig Emv Verfahren zur gleichzeitigen herstellung einer vielzahl elektrischer kontaktstellen
WO1993026144A1 (fr) * 1992-06-15 1993-12-23 Dyconex Patente Ag Procede pour la production de points de contact ulterieurement conditionnables sur des supports de circuit, ainsi que supports de circuit pourvus de tels points de contact.
JPH0851267A (ja) * 1994-08-08 1996-02-20 Sankyo Seiki Mfg Co Ltd 回路基板及びその製造方法
JPH08228056A (ja) * 1995-02-21 1996-09-03 Denki Kagaku Kogyo Kk 金属ベース回路基板
DE19522338A1 (de) * 1995-06-20 1997-01-02 Fraunhofer Ges Forschung Verfahren zur Herstellung einer Durchkontaktierung sowie Chipträger und Chipträgeranordnung mit einer Durchkontaktierung
EP1107654A1 (fr) * 1999-05-25 2001-06-13 Mitsui Mining & Smelting Co., Ltd. Feuille pour carte de circuits imprimes, procede de formation de trou d'interconnexion, feuille de resine a trou d'interconnexion charge, carte de circuits imprimes et procede de fabrication associe
US20010022236A1 (en) * 2000-02-18 2001-09-20 Thilo Stolze Substrate for power semiconductor modules with through-plating of solder and method for its production

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 06 28 June 1996 (1996-06-28) *
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 01 31 January 1997 (1997-01-31) *

Also Published As

Publication number Publication date
WO2004027866A8 (fr) 2005-04-28
WO2004027866A2 (fr) 2004-04-01

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