WO2004025720A1 - Manufacturing an ic - Google Patents

Manufacturing an ic Download PDF

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Publication number
WO2004025720A1
WO2004025720A1 PCT/IB2003/003770 IB0303770W WO2004025720A1 WO 2004025720 A1 WO2004025720 A1 WO 2004025720A1 IB 0303770 W IB0303770 W IB 0303770W WO 2004025720 A1 WO2004025720 A1 WO 2004025720A1
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WO
WIPO (PCT)
Prior art keywords
chemical mechanical
polishing
metal
mechanical polishing
barrier layer
Prior art date
Application number
PCT/IB2003/003770
Other languages
French (fr)
Inventor
Viet Nguyen Hoang
Roel Daamen
Original Assignee
Koninklijke Philips Electronics N.V.
Interuniversitair Micro-Electronica Centrum Vzw
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V., Interuniversitair Micro-Electronica Centrum Vzw filed Critical Koninklijke Philips Electronics N.V.
Priority to AU2003255986A priority Critical patent/AU2003255986A1/en
Publication of WO2004025720A1 publication Critical patent/WO2004025720A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation

Definitions

  • the invention relates to a method of manufacturing an integrated circuit (IC), comprising the steps of providing a pre- fabricated integrated circuit comprising an electrical device and having a surface coated with a dielectric material, a barrier layer and a metal, in that order, the dielectric material and the metal being separated by the barrier layer, the dielectric material having an opening, the metal extending into the opening, thereby electrically contacting the electrical device, removing portions of the metal outside the opening by a first chemical mechanical polishing step using a first polishing liquid until the barrier layer is locally exposed, and removing portions of the locally exposed barrier layer by a second chemical mechanical polishing step using a second polishing liquid.
  • IC integrated circuit
  • the invention also relates to a chemical mechanical polishing apparatus comprising a polishing station with a polishing member having a polishing surface, a polishing liquid supply means for independently supplying a first polishing liquid and a second polishing liquid to the polishing surface, a system control means for enabling the polishing station and the polishing liquid supply means to carry out such a method for manufacturing an integrated circuit (IC).
  • a chemical mechanical polishing apparatus comprising a polishing station with a polishing member having a polishing surface, a polishing liquid supply means for independently supplying a first polishing liquid and a second polishing liquid to the polishing surface, a system control means for enabling the polishing station and the polishing liquid supply means to carry out such a method for manufacturing an integrated circuit (IC).
  • IC integrated circuit
  • the invention also relates to a computer program for enabling a chemical mechanical polishing apparatus to carry out such a method for manufacturing an integrated circuit (IC).
  • IC integrated circuit
  • US-Al-2002/0,019,202 discloses an embodiment of a method described in the opening paragraph.
  • ICs are equipped with at least one electrical device and an in-laid metal structure which connects the electrical device with terminals at the outer surface of the IC and with other electrical devices, if present.
  • the terminals can be used to provide the electrical input signals and output signals to the IC.
  • the shape of the in-laid metal structure determines which functions can be performed by the IC.
  • the in-laid metal structure may comprise several levels of metal lines and vias which connect metal lines of, e.g. adjacent levels.
  • the metal lines are mutually electrically insulated by a dielectric material.
  • the metal cannot be deposited directly onto the dielectric material because of the risk of diffusion of the metal into the dielectric material. Therefore, often a barrier layer is put between these two materials, which counteracts diffusion.
  • a layer of the dielectric material is deposited and one or more openings are made in the dielectric material.
  • the openings may be made at the positions of the in-laid metal structure or of the electrical device by means of, e.g. photolithography and etching.
  • the barrier layer and, on top of it, the metal are deposited. After these depositions, the barrier layer covers the dielectric material, also in the opening or the openings, and the metal layer covers the barrier layer and fills the opening or the openings. Therefore, the metal and the barrier layer are present also outside this opening.
  • the metal and the barrier layer outside the opening may cause short circuits between metal lines, they need to be removed before new parts of the in-laid metal structure can be manufactured.
  • the pre-fabricated IC provided with the metal is polished after depositing the metal.
  • the dielectric material, and the metal and the barrier layer inside the opening form a smooth surface on which the next level of the in-laid metal structure can be deposited.
  • metal particles may be left outside the opening after polishing. Some of these particles may create electrical contacts between two metal lines, which, according to the IC design, should be mutually insulated, leading to a malfunctioning IC. Others of these particles maybe electrically connected to only one metal line, but are so close to another metal line that during operation of the IC electrical breakdown occurs between these two metal lines at the position of the metal particle.
  • the size of the metal particles remaining after polishing is considerably smaller than the distance between the metal lines.
  • the known method attempts to achieve this goal by executing a first chemical mechanical polishing step, which preferentially removes the metal, and subsequently a second chemical mechanical polishing step, which preferentially removes the barrier layer. In this way, it is possible to reduce over-polishing and thereby damage to the metal when removing the barrier layer.
  • low-k dielectrics i.e. materials with a dielectric constant smaller than that of silicon dioxide, such as, e.g. parylene or SiLKTM which is marketed by Dow Chemical from Midland, Michigan, USA, are used as the dielectric material, and copper is chosen as the metal, because the in-laid metal structures then have excellent high frequency behavior allowing for faster operation of the IC.
  • copper mechanically strong barrier layers comprising, e.g. tantalum nitride and tantalum, are used. In particular when using these materials, it is hard to effectively remove substantially all the metal outside the opening.
  • the first object is achieved according to the invention by repeating the first chemical mechanical polishing step after having performed the second chemical mechanical polishing step.
  • the invention is based on the insight that interactions between the metal and the barrier layer counteract the removal of the metal outside the opening, in particular when only small amounts of metal are left outside the opening. It is hard then to remove the remaining metal outside the opening. The interactions between the metal and the barrier layer can be reduced by removing portions of the barrier layer. This allows for a more efficient removal of the metal outside the opening when repeating the first chemical mechanical polishing step. It is advantageous if the second chemical mechanical polishing step is repeated after having repeated the first chemical mechanical polishing step. By repeating the first chemical mechanical polishing step, portions of the barrier layer outside the opening that were previously covered by the metal are no longer covered and can be removed by repeating the second chemical mechanical polishing step.
  • the chance that the barrier layer causes a short-circuit is reduced and the product has become planar to a larger extent.
  • the first chemical mechanical polishing step and the second chemical mechanical polishing step are alternately repeated until substantially all metal outside the opening is removed. After removing portions of the barrier layer outside the opening by repeating the second chemical mechanical polishing step, the interaction between the metal and the barrier layer is further reduced. It is therefore possible to again remove metal outside the opening and thereby expose portions of the barrier layer, which are at least partly removed by once more repeating the second chemical mechanical polishing step. By alternately repeating the first chemical mechanical polishing step and the second chemical mechanical polishing step a few times, all metal outside the opening is removed.
  • a material comprising copper may e.g. be used as the metal. This material has a relatively low electric resistivity and therefore the IC can be operated at high frequencies.
  • a substantially abrasive-free polishing liquid is used as the first polishing liquid.
  • This type of polishing liquid which contains no or only a small amount of abrasive particles, is very suited for the removal of relatively soft metals such as copper because it results in a smooth polished surface.
  • relatively soft metals such as copper
  • dishing the excessive removal of metal from the openings, known in the field of chemical mechanical polishing as dishing, is reduced.
  • a material comprising tantalum is used as the barrier layer.
  • This material is very capable of preventing the diffusion of metal, in particular of copper, and it hardly diffuses itself into the dielectric material. Often it is supplied in a double layer of tantalum and tantalum nitride because the former material adheres well to the dielectric material, metals, in particular copper, adhere well to the latter, and tantalum adheres well to tantalum nitride.
  • a polishing liquid comprising abrasive particles is used as the second polishing liquid.
  • the abrasive particles which may comprise, e.g. silica, aluminum, zirconium oxide, titanium oxide, cerium oxide, or any other abrasives known in the art, and are used in conventional chemical mechanical polishing, make the removal of a hard barrier layer relatively easy.
  • a dielectric having a dielectric constant smaller than silicon dioxide is used as the dielectric material. Due to the relatively low dielectric constant the IC can be operated at high frequencies.
  • the second object is achieved according to the invention in that the system control means enables the polishing station and the polishing liquid supply means to repeat the first chemical mechanical polishing step after having performed the second chemical mechanical polishing step.
  • the third object is achieved according to the invention by the computer program enabling the polishing apparatus to repeat the first chemical mechanical polishing step after having performed the second chemical mechanical polishing step.
  • Figs. 1A- IF are cross-section al views of the IC at various steps of the method.
  • Fig. 2 is a schematic drawing of the chemical mechanical polishing apparatus. The Figures are not drawn to scale. In the Figures, like reference numerals generally refer to like parts.
  • the method for manufacturing an IC comprises the step of providing the prefabricated IC 10 shown in Fig. 1 A.
  • the pre-fabricated integrated circuit 10 comprises an electrical device 2 which may be any type of transistor such as, e.g., a metal oxide semiconductor field effect transistor (MOSFET), or any type of diode or any other electrical device, which can be integrated in an IC.
  • MOSFET metal oxide semiconductor field effect transistor
  • the pre-fabricated integrated circuit 10 has a surface 11 which is coated with, in succession, a dielectric material 12, a barrier layer 14 and a metal 15.
  • the dielectric material 12 and the metal 15 are separated by the barrier layer 14.
  • the dielectric material 12 has an opening 13.
  • the metal 15 extends into the opening 13, thereby electrically contacting the electrical device 2.
  • the barrier layer 14 and the metal 15 inside the opening 13 are parts of the in-laid metal structure.
  • the barrier layer 14 is electrically conducting , but its relatively low electric conductivity prevents its use as a conductor other than for a relatively small resistance, i.e. the thickness of the layer effective as a metal diffusion barrier.
  • the pre-fabricated IC further comprises a substrate 4, which may be of monocrystalline silicon or gallium arsenic. Alternatively, it may be of any other material on which an IC can be suitably manufactured such as, e.g. glass.
  • first chemical mechanical polishing step using a first polishing liquid 24, thereby locally exposing the barrier layer 14.
  • the first chemical mechanical polishing step preferentially removes the metal 15.
  • the pre-fabricated IC obtained after execution of the first chemical mechanical polishing step is shown in Fig. IB.
  • portions of the locally exposed barrier layer 14 are removed by a second chemical mechanical polishing step using a second polishing liquid 25.
  • the second chemical mechanical polishing step preferentially removes the barrier layer 14.
  • the prefabricated IC obtained after execution of the second chemical mechanical polishing step is shown in Fig. IC.
  • the dielectric material 12 in Figs. 1 A-1F is a dielectric which has a dielectric constant smaller than silicon dioxide.
  • the first chemical mechanical polishing step is repeated after having performed the second chemical mechanical polishing step.
  • the amount of the metal 15 outside the opening 13 is further reduced.
  • the pre-fabricated IC obtained after repeating the first chemical mechanical polishing step is shown in Fig. ID.
  • the second chemical mechanical polishing step is repeated after repetition of the first chemical mechanical polishing step, thereby removing portions of the barrier layer 14 which have been exposed by the previous step.
  • the pre-fabricated IC obtained after repeating the second chemical mechanical polishing step is shown in Fig. IE.
  • the first chemical mechanical polishing step and the second chemical mechanical polishing step are alternately repeated a few times until substantially all metal 15 outside the opening 13 is removed.
  • the pre-fabricated integrated circuit 10 shown in Fig. IF then has a smooth surface 11', which can be further processed to make additional layers of the in-laid metal structure, if desired.
  • the surface 11' shown in Fig. IF, is coated with additional dielectric material, in which one or more openings are made. Then the dielectric material and the opening are coated with an additional barrier layer and additional metal analogous to the coating described above. Subsequently, the above-mentioned method is executed once more to further manufacture the in-laid metal structure.
  • a chemical mechanical polishing apparatus 20 which comprises a polishing station 21 with a polishing member 27 having a polishing surface 22.
  • the polishing station 21 comprise a first polishing station 21a with a first polishing member 27a having a first polishing surface 22a and a second polishing station 21b with a second member 27b having a second polishing surface 22b.
  • the polishing members 27a, 27b are each a substantially flat disk.
  • the first polishing surface 22a and/or the second polishing surface 22b may comprise abrasive particles, fixed to the first polishing surface 22a and/or the second polishing surface 22b.
  • first polishing surface 22a and/or the second polishing surface 22b may alternatively be free of abrasive particles or may comprise abrasive particles which are not fixed to the first polishing surface 22a and/or the second polishing surface 22b, but which are supplied to the first polishing surface 22a and/or the second polishing surface 22b as part of the first polishing liquid 24 and/or the second polishing liquid 25 by a polishing liquid supply unit 23.
  • the polishing liquid supply unit 23 is able to independently supply the first polishing liquid 24 and the second polishing liquid 25 to the polishing surface 22.
  • the polishing liquid supply unit 23 comprises a first nozzle 30a for dispensing the first polishing liquid 24 contained in a first reservoir 31 a to the first polishing surface 22a and a second nozzle 30b for dispensing the second polishing liquid 25 contained in a second reservoir 31b to the second polishing surface 22b.
  • the polishing station 21 further comprises a workpiece holder 40 able to hold the pre-fabricated IC 10 and press the pre-fabricated IC 10 against the polishing surface 22.
  • the workpiece holder 40 can be translated parallel to the polishing surface 22 to move the pre-fabricated IC 10 from the first polishing station 21a to the second polishing station 21b, and from the second polishing station 21b to the first polishing station 21a, and it can translated in a direction perpendicular to the polishing surface 22 by means of a workpiece holder arm 41.
  • the polishing tool 20 further comprises a system control unit 26 for enabling the polishing station 21 and the polishing liquid supply unit 23 to carry out the method described above.
  • the system control unit 26 is a computer which is provided with an information carrier 28 on which a computer program is present.
  • the computer program comprises instructions by which the computer controls the position of the workpiece holder arm 41 and the dispensing of the first polishing liquid 24 and the second polishing liquid 25.
  • the invention relates to a method for manufacturing an integrated circuit according to the invention, which starts with providing a pre-fabricated integrated circuit 10 having a surface 11 coated with a dielectric material 12, a barrier layer 14 and a metal 15.
  • the dielectric material 12, which is separated from the metal 15 by the barrier layer 14, has an opening 13, which is filled by the metal 15.
  • Portions of the metal 15 outside the opening 13 are removed by a first chemical mechanical polishing step, which preferentially removes the metal 15, to locally expose the barrier layer 14. Portions of the locally exposed barrier layer 14 are removed by a second chemical mechanical polishing step, which preferentially removes the barrier layer 14.
  • the first chemical mechanical polishing step is repeated after having performed the second chemical mechanical polishing step.
  • the apparatus is able to perform the method.
  • the computer program is able to control the method.
  • electrical device 2 in-laid metal structure 3 substrate 4 pre-fabricated integrated circuit 10 surface 11 dielectric material 12 opening 13 barrier layer 14 metal 15 chemical mechanical polishing apparatus 20 polishing station 21, 21a, 21b polishing surface 22, 22a, 22b polishing liquid supply means 23 first polishing liquid 24 second polishing liquid 25 system control means 26 polishing member 27, 27a, 27b information carrier 28 first/second nozzle 30a, 30b first/second reservoir 31 a, 3 lb workpiece holder 40 workpiece holder arm 41

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The method for manufacturing an integrated circuit according to the invention starts with providing a pre-fabricated integrated circuit (10) having a surface (11) coated with a dielectric material (12), a barrier layer (14) and a metal (15). The dielectric material (12), which is separated from the metal (15) by the barrier layer (14), has an opening (13), which is filled with the metal (15). Portions of the metal (15) outside the opening (13) are removed by a first chemical mechanical polishing step, which preferentially removes the metal (15) to locally expose the barrier layer (14). Portions of the locally exposed barrier layer (14) are removed by a second chemical mechanical polishing step, which preferentially removes the barrier layer (14). According to the invention, the first chemical mechanical polishing step is repeated after the second chemical mechanical polishing step has been carried out. The apparatus is able to perform the method. The computer program is able to control the method.

Description

Manufacturing an IC
The invention relates to a method of manufacturing an integrated circuit (IC), comprising the steps of providing a pre- fabricated integrated circuit comprising an electrical device and having a surface coated with a dielectric material, a barrier layer and a metal, in that order, the dielectric material and the metal being separated by the barrier layer, the dielectric material having an opening, the metal extending into the opening, thereby electrically contacting the electrical device, removing portions of the metal outside the opening by a first chemical mechanical polishing step using a first polishing liquid until the barrier layer is locally exposed, and removing portions of the locally exposed barrier layer by a second chemical mechanical polishing step using a second polishing liquid. The invention also relates to a chemical mechanical polishing apparatus comprising a polishing station with a polishing member having a polishing surface, a polishing liquid supply means for independently supplying a first polishing liquid and a second polishing liquid to the polishing surface, a system control means for enabling the polishing station and the polishing liquid supply means to carry out such a method for manufacturing an integrated circuit (IC).
The invention also relates to a computer program for enabling a chemical mechanical polishing apparatus to carry out such a method for manufacturing an integrated circuit (IC).
US-Al-2002/0,019,202 discloses an embodiment of a method described in the opening paragraph.
Usually, ICs are equipped with at least one electrical device and an in-laid metal structure which connects the electrical device with terminals at the outer surface of the IC and with other electrical devices, if present. The terminals can be used to provide the electrical input signals and output signals to the IC. The shape of the in-laid metal structure determines which functions can be performed by the IC.
The in-laid metal structure may comprise several levels of metal lines and vias which connect metal lines of, e.g. adjacent levels. The metal lines are mutually electrically insulated by a dielectric material. In many cases the metal cannot be deposited directly onto the dielectric material because of the risk of diffusion of the metal into the dielectric material. Therefore, often a barrier layer is put between these two materials, which counteracts diffusion. When manufacturing the in-laid metal structure of an IC, first a layer of the dielectric material is deposited and one or more openings are made in the dielectric material. The openings may be made at the positions of the in-laid metal structure or of the electrical device by means of, e.g. photolithography and etching. Subsequently, the barrier layer and, on top of it, the metal are deposited. After these depositions, the barrier layer covers the dielectric material, also in the opening or the openings, and the metal layer covers the barrier layer and fills the opening or the openings. Therefore, the metal and the barrier layer are present also outside this opening.
Because the metal and the barrier layer outside the opening may cause short circuits between metal lines, they need to be removed before new parts of the in-laid metal structure can be manufactured. To this end the pre-fabricated IC provided with the metal is polished after depositing the metal. For further processing it is normally also required that the dielectric material, and the metal and the barrier layer inside the opening form a smooth surface on which the next level of the in-laid metal structure can be deposited.
Ideally, the metal and the barrier layer outside the opening are removed completely by polishing. However, metal particles may be left outside the opening after polishing. Some of these particles may create electrical contacts between two metal lines, which, according to the IC design, should be mutually insulated, leading to a malfunctioning IC. Others of these particles maybe electrically connected to only one metal line, but are so close to another metal line that during operation of the IC electrical breakdown occurs between these two metal lines at the position of the metal particle. In order not to deteriorate the yield of the IC manufacturing it is required that the size of the metal particles remaining after polishing is considerably smaller than the distance between the metal lines. By continuous improvements in the art of IC manufacturing the dimensions of structures in ICs and, in particular, of the metal lines become smaller and smaller. Hence, the size of the metal particles which may incidentally be left outside the opening without deteriorating the yield is getting smaller as well. Therefore, it is required to remove the metal outside the opening to a larger extent.
The known method attempts to achieve this goal by executing a first chemical mechanical polishing step, which preferentially removes the metal, and subsequently a second chemical mechanical polishing step, which preferentially removes the barrier layer. In this way, it is possible to reduce over-polishing and thereby damage to the metal when removing the barrier layer.
In recent years, low-k dielectrics, i.e. materials with a dielectric constant smaller than that of silicon dioxide, such as, e.g. parylene or SiLK™ which is marketed by Dow Chemical from Midland, Michigan, USA, are used as the dielectric material, and copper is chosen as the metal, because the in-laid metal structures then have excellent high frequency behavior allowing for faster operation of the IC. Because of the high diffusivity of copper mechanically strong barrier layers comprising, e.g. tantalum nitride and tantalum, are used. In particular when using these materials, it is hard to effectively remove substantially all the metal outside the opening.
It is a disadvantage of the known method that a relatively large amount of metal is left outside the opening, thereby reducing the yield of the IC manufacturing. The known techniques for further removal of the metal comprise pressing the polished surface against the polishing surface with a high mechanical force and polishing for a long time, respectively. These techniques, however, both reduce the yield of the IC manufacturing because the dielectric material is damaged.
It is a first object of the invention to provide a method of the kind described in the opening paragraph in which the metal left outside the opening is removed to a large extent.
It is a second object of the invention to provide a chemical mechanical polishing apparatus of the kind described in the opening paragraph which is able to remove metal outside the opening to a large extent.
It is a third object of the invention to provide a computer program of the kind described in the opening paragraph which enables the chemical mechanical polishing apparatus to remove metal outside the opening to a large extent.
The first object is achieved according to the invention by repeating the first chemical mechanical polishing step after having performed the second chemical mechanical polishing step.
The invention is based on the insight that interactions between the metal and the barrier layer counteract the removal of the metal outside the opening, in particular when only small amounts of metal are left outside the opening. It is hard then to remove the remaining metal outside the opening. The interactions between the metal and the barrier layer can be reduced by removing portions of the barrier layer. This allows for a more efficient removal of the metal outside the opening when repeating the first chemical mechanical polishing step. It is advantageous if the second chemical mechanical polishing step is repeated after having repeated the first chemical mechanical polishing step. By repeating the first chemical mechanical polishing step, portions of the barrier layer outside the opening that were previously covered by the metal are no longer covered and can be removed by repeating the second chemical mechanical polishing step. Therefore, the chance that the barrier layer causes a short-circuit is reduced and the product has become planar to a larger extent. In this case, it is further advantageous if the first chemical mechanical polishing step and the second chemical mechanical polishing step are alternately repeated until substantially all metal outside the opening is removed. After removing portions of the barrier layer outside the opening by repeating the second chemical mechanical polishing step, the interaction between the metal and the barrier layer is further reduced. It is therefore possible to again remove metal outside the opening and thereby expose portions of the barrier layer, which are at least partly removed by once more repeating the second chemical mechanical polishing step. By alternately repeating the first chemical mechanical polishing step and the second chemical mechanical polishing step a few times, all metal outside the opening is removed.
A material comprising copper may e.g. be used as the metal. This material has a relatively low electric resistivity and therefore the IC can be operated at high frequencies.
It is favorable if a substantially abrasive-free polishing liquid is used as the first polishing liquid. This type of polishing liquid, which contains no or only a small amount of abrasive particles, is very suited for the removal of relatively soft metals such as copper because it results in a smooth polished surface. In particular the excessive removal of metal from the openings, known in the field of chemical mechanical polishing as dishing, is reduced.
It is advantageous if a material comprising tantalum is used as the barrier layer. This material is very capable of preventing the diffusion of metal, in particular of copper, and it hardly diffuses itself into the dielectric material. Often it is supplied in a double layer of tantalum and tantalum nitride because the former material adheres well to the dielectric material, metals, in particular copper, adhere well to the latter, and tantalum adheres well to tantalum nitride. It is advantageous if a polishing liquid comprising abrasive particles is used as the second polishing liquid. The abrasive particles, which may comprise, e.g. silica, aluminum, zirconium oxide, titanium oxide, cerium oxide, or any other abrasives known in the art, and are used in conventional chemical mechanical polishing, make the removal of a hard barrier layer relatively easy.
Suitably, a dielectric having a dielectric constant smaller than silicon dioxide is used as the dielectric material. Due to the relatively low dielectric constant the IC can be operated at high frequencies.
The second object is achieved according to the invention in that the system control means enables the polishing station and the polishing liquid supply means to repeat the first chemical mechanical polishing step after having performed the second chemical mechanical polishing step.
The third object is achieved according to the invention by the computer program enabling the polishing apparatus to repeat the first chemical mechanical polishing step after having performed the second chemical mechanical polishing step.
These and other aspects of the method for manufacturing, the chemical mechanical polishing apparatus and the computer program according to the invention will be further elucidated and described with reference to the drawings, in which:
Figs. 1A- IF are cross-section al views of the IC at various steps of the method; and
Fig. 2 is a schematic drawing of the chemical mechanical polishing apparatus. The Figures are not drawn to scale. In the Figures, like reference numerals generally refer to like parts.
The method for manufacturing an IC comprises the step of providing the prefabricated IC 10 shown in Fig. 1 A. The pre-fabricated integrated circuit 10 comprises an electrical device 2 which may be any type of transistor such as, e.g., a metal oxide semiconductor field effect transistor (MOSFET), or any type of diode or any other electrical device, which can be integrated in an IC.
The pre-fabricated integrated circuit 10 has a surface 11 which is coated with, in succession, a dielectric material 12, a barrier layer 14 and a metal 15. The dielectric material 12 and the metal 15 are separated by the barrier layer 14. The dielectric material 12 has an opening 13. The metal 15 extends into the opening 13, thereby electrically contacting the electrical device 2. When finishing the method, the barrier layer 14 and the metal 15 inside the opening 13 are parts of the in-laid metal structure. The barrier layer 14 is electrically conducting , but its relatively low electric conductivity prevents its use as a conductor other than for a relatively small resistance, i.e. the thickness of the layer effective as a metal diffusion barrier.
In the embodiment of Fig. 1 A the pre-fabricated IC further comprises a substrate 4, which may be of monocrystalline silicon or gallium arsenic. Alternatively, it may be of any other material on which an IC can be suitably manufactured such as, e.g. glass.
In the next step of the method, portions of the metal 15 outside the opening 13 are removed by a first chemical mechanical polishing step using a first polishing liquid 24, thereby locally exposing the barrier layer 14. The first chemical mechanical polishing step preferentially removes the metal 15. The pre-fabricated IC obtained after execution of the first chemical mechanical polishing step is shown in Fig. IB.
Subsequently, portions of the locally exposed barrier layer 14 are removed by a second chemical mechanical polishing step using a second polishing liquid 25. The second chemical mechanical polishing step preferentially removes the barrier layer 14. The prefabricated IC obtained after execution of the second chemical mechanical polishing step is shown in Fig. IC.
The metal 15, which in Figs. 1A-1F is copper, is removed preferentially by the first chemical mechanical polishing step using the first polishing liquid 24, which is a substantially abrasive free polishing liquid. The barrier layer 14, which in Figs. 1 A-1F comprises tantalum and tantalum nitride, is removed preferentially by the second polishing liquid 25, which is a slurry comprising abrasive particles. The dielectric material 12 in Figs. 1 A-1F is a dielectric which has a dielectric constant smaller than silicon dioxide.
According to the invention, the first chemical mechanical polishing step is repeated after having performed the second chemical mechanical polishing step. By repeating the first chemical mechanical polishing step, the amount of the metal 15 outside the opening 13 is further reduced. The pre-fabricated IC obtained after repeating the first chemical mechanical polishing step is shown in Fig. ID.
The second chemical mechanical polishing step is repeated after repetition of the first chemical mechanical polishing step, thereby removing portions of the barrier layer 14 which have been exposed by the previous step. The pre-fabricated IC obtained after repeating the second chemical mechanical polishing step is shown in Fig. IE.
The first chemical mechanical polishing step and the second chemical mechanical polishing step are alternately repeated a few times until substantially all metal 15 outside the opening 13 is removed. The pre-fabricated integrated circuit 10 shown in Fig. IF then has a smooth surface 11', which can be further processed to make additional layers of the in-laid metal structure, if desired.
To this end, the surface 11', shown in Fig. IF, is coated with additional dielectric material, in which one or more openings are made. Then the dielectric material and the opening are coated with an additional barrier layer and additional metal analogous to the coating described above. Subsequently, the above-mentioned method is executed once more to further manufacture the in-laid metal structure.
The above-described method is executed using a chemical mechanical polishing apparatus 20, which comprises a polishing station 21 with a polishing member 27 having a polishing surface 22. In the embodiment shown in Fig. 2, the polishing station 21 comprise a first polishing station 21a with a first polishing member 27a having a first polishing surface 22a and a second polishing station 21b with a second member 27b having a second polishing surface 22b. The polishing members 27a, 27b are each a substantially flat disk. The first polishing surface 22a and/or the second polishing surface 22b may comprise abrasive particles, fixed to the first polishing surface 22a and/or the second polishing surface 22b. However, the first polishing surface 22a and/or the second polishing surface 22b may alternatively be free of abrasive particles or may comprise abrasive particles which are not fixed to the first polishing surface 22a and/or the second polishing surface 22b, but which are supplied to the first polishing surface 22a and/or the second polishing surface 22b as part of the first polishing liquid 24 and/or the second polishing liquid 25 by a polishing liquid supply unit 23.
The polishing liquid supply unit 23 is able to independently supply the first polishing liquid 24 and the second polishing liquid 25 to the polishing surface 22. In the embodiment shown in Fig. 2, the polishing liquid supply unit 23 comprises a first nozzle 30a for dispensing the first polishing liquid 24 contained in a first reservoir 31 a to the first polishing surface 22a and a second nozzle 30b for dispensing the second polishing liquid 25 contained in a second reservoir 31b to the second polishing surface 22b.
The polishing station 21 further comprises a workpiece holder 40 able to hold the pre-fabricated IC 10 and press the pre-fabricated IC 10 against the polishing surface 22. In the embodiment shown in Fig. 2, the workpiece holder 40 can be translated parallel to the polishing surface 22 to move the pre-fabricated IC 10 from the first polishing station 21a to the second polishing station 21b, and from the second polishing station 21b to the first polishing station 21a, and it can translated in a direction perpendicular to the polishing surface 22 by means of a workpiece holder arm 41.
The polishing tool 20 further comprises a system control unit 26 for enabling the polishing station 21 and the polishing liquid supply unit 23 to carry out the method described above. The system control unit 26 is a computer which is provided with an information carrier 28 on which a computer program is present. The computer program comprises instructions by which the computer controls the position of the workpiece holder arm 41 and the dispensing of the first polishing liquid 24 and the second polishing liquid 25. In summary, the invention relates to a method for manufacturing an integrated circuit according to the invention, which starts with providing a pre-fabricated integrated circuit 10 having a surface 11 coated with a dielectric material 12, a barrier layer 14 and a metal 15. The dielectric material 12, which is separated from the metal 15 by the barrier layer 14, has an opening 13, which is filled by the metal 15. Portions of the metal 15 outside the opening 13 are removed by a first chemical mechanical polishing step, which preferentially removes the metal 15, to locally expose the barrier layer 14. Portions of the locally exposed barrier layer 14 are removed by a second chemical mechanical polishing step, which preferentially removes the barrier layer 14. According to the invention, the first chemical mechanical polishing step is repeated after having performed the second chemical mechanical polishing step. The apparatus is able to perform the method. The computer program is able to control the method.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. LIST OF REFERENCE NUMERALS:
electrical device 2 in-laid metal structure 3 substrate 4 pre-fabricated integrated circuit 10 surface 11 dielectric material 12 opening 13 barrier layer 14 metal 15 chemical mechanical polishing apparatus 20 polishing station 21, 21a, 21b polishing surface 22, 22a, 22b polishing liquid supply means 23 first polishing liquid 24 second polishing liquid 25 system control means 26 polishing member 27, 27a, 27b information carrier 28 first/second nozzle 30a, 30b first/second reservoir 31 a, 3 lb workpiece holder 40 workpiece holder arm 41

Claims

CLAIMS:
1. A method of manufacturing an integrated circuit, comprising the steps of:
- providing a pre-fabricated integrated circuit (10) comprising an electrical device (2) and having a surface (11) coated with a dielectric material (12), a barrier layer (14) and a metal (15),in that order, the dielectric material (12) and the metal (15) being separated by the barrier layer (14), the dielectric material (12) having an opening (13), the metal (15) extending into the opemng (13), thereby electrically contacting the electrical device (2);
- removing portions of the metal (15) outside the opening (13) by a first chemical mechanical polishing step, using a first polishing liquid (24) until the barrier layer (14) is locally exposed; - removing portions of the locally exposed barrier layer (14) by a second chemical mechanical polishing step, using a second polishing liquid (25); and
- repeating the first chemical mechanical polishing step after having performed the second chemical mechanical polishing step.
2. A method as claimed in claim 1, further comprising repeating the second chemical mechamcal polishing step after having repeated the first chemical mechanical polishing step.
3. A method as claimed in claim 2, characterized by alternately repeating the first chemical mechanical polishing step and the second chemical mechanical polishing step until substantially all metal (15) outside the opening (13) is removed.
4. A method as claimed in claim 1, characterized in that a substantially abrasive- free polishing liquid is used as the first polishing liquid (24).
5. A method as claimed in claim 1, characterized in that a dielectric having a dielectric constant smaller than silicon dioxide is used as the dielectric material (12).
6. A chemical mechanical polishing apparatus (20) comprising: - a polishing station (21) with a polishing member (27) having a polishing surface (22);
- a polishing liquid supply means (23) for independently supplying a first polishing liquid (24) and a second polishing liquid (25) to the polishing surface (22); - a system control means (26) for enabling the polishing station (21) and the polishing liquid supply means (23) to carry out the method of manufacturing an integrated circuit of claim 1, wherein
- the system control means (26) enables the polishing station (21) and the polishing liquid supply means (23) to repeat the first chemical mechanical polishing step after having performed the second chemical mechanical polishing step.
7. A computer program for enabling a chemical mechanical polishing apparatus (20) to carry out the method of manufacturing an integrated circuit of claim 1, further characterized by enabling the polishing apparatus (20) to repeat the first chemical mechanical polishing step after having performed the second chemical mechanical polishing step.
8. An information carrier (27) on which a computer program as claimed in claim 7 is stored.
PCT/IB2003/003770 2002-09-13 2003-08-13 Manufacturing an ic WO2004025720A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003255986A AU2003255986A1 (en) 2002-09-13 2003-08-13 Manufacturing an ic

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02078784 2002-09-13
EP02078784.2 2002-09-13

Publications (1)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6261158B1 (en) * 1998-12-16 2001-07-17 Speedfam-Ipec Multi-step chemical mechanical polishing
US6326299B1 (en) * 1998-11-09 2001-12-04 Hitachi, Ltd. Method for manufacturing a semiconductor device
US20020023715A1 (en) * 2000-05-26 2002-02-28 Norio Kimura Substrate polishing apparatus and substrate polishing mehod
US6380069B1 (en) * 2000-01-14 2002-04-30 United Microelectronics Corp. Method of removing micro-scratch on metal layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6326299B1 (en) * 1998-11-09 2001-12-04 Hitachi, Ltd. Method for manufacturing a semiconductor device
US6261158B1 (en) * 1998-12-16 2001-07-17 Speedfam-Ipec Multi-step chemical mechanical polishing
US6380069B1 (en) * 2000-01-14 2002-04-30 United Microelectronics Corp. Method of removing micro-scratch on metal layer
US20020023715A1 (en) * 2000-05-26 2002-02-28 Norio Kimura Substrate polishing apparatus and substrate polishing mehod

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AU2003255986A1 (en) 2004-04-30

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