Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
  • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
  • H03K4/066—Generating pulses having essentially a finite slope or stepped portions having triangular shape using a Miller-integrator
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
  • H03B27/00—Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
  • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
  • H03B5/20—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator
  • H03B5/24—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
  • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
  • H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
  • H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
  • H03K4/50—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor
  • H03K4/501—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator
  • H03K4/502—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator the capacitor being charged from a constant-current source
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
  • H03K3/03—Astable circuits
  • H03K3/0315—Ring oscillators

Definitions

• the present invention generally relates to oscillator circuits, and more specifically relates to an oscillator circuit having reduced layout area and lower power supply transients.
• Oscillator circuits are found in many electronic circuit applications.
• oscillator circuits can be found in DC/DC converters, capacitive sensors, audio receivers, and FM (frequency modulation) generators, to name a few.
• the frequency of the oscillator is set by a capacitor.
• the capacitor is charged and discharged during operation of some oscillator circuits, the voltage on some internal nodes can be boosted beyond the power supply rails causing abnormal behavior.
• attenuation capacitors have been used. However, adding attenuation capacitors increases the total amount of capacitance that is charged and discharged, resulting in large spikes in power supply current.
• the attenuation capacitors need to be at least as large as the capacitors used to set the frequency and therefore greatly increase the amount of surface area required to implement the oscillator circuit on an integrated circuit.
• a user of an integrated circuit oscillator needs to be able to set the oscillation frequency of the oscillator.
• One way to make the oscillation frequency user settable is to use an external oscillation capacitor.
• the size of the attenuation capacitor is dependent on the size of the oscillation capacitor, the user must add two external capacitors, an oscillation capacitor and an attenuation capacitor, to set the oscillation frequency. Therefore, there is a need for an integrated circuit oscillator that eliminates the need for attenuation capacitors.
• FIG. 1 illustrates, in schematic diagram form, an oscillator circuit in accordance with the prior art
• FIG. 2 illustrates a waveform of the input and output voltages of the oscillator circuit of FIG. 1;
• FIG. 3 illustrates in partial block diagram form and partial schematic diagram form, an oscillator circuit in accordance with one embodiment of the present invention;
• FIG. 4 illustrates, in schematic diagram form, an oscillator circuit in accordance with another embodiment of the present invention
• FIG. 5 illustrates a waveform of the input and output voltages of the oscillator circuit of FIG. 4.
• the present invention provides a CMOS (complementary metal- oxide semiconductor) oscillator circuit having a switchable current source controlled by a feedback signal, a comparator circuit, a monitor and control circuit, and a feedback capacitor.
• the comparator circuit provides an output signal dependent on the voltage at its input(s).
• the monitor and control circuit is coupled to both input and output terminals of the comparator circuit for monitoring and controlling a voltage swing of its output voltage.
• the feedback capacitor is coupled between the output terminal of the monitor and control circuit and input terminal of the comparator and is sized to set the oscillation frequency as desired. Because the accuracy of the comparator is not critical, a simple high-gain inverter circuit can be used for this function.
• the monitor and control circuit constrains its output signal within the power supply rails without the use of an attenuation capacitor.
• the oscillator circuit can be made smaller, thus requiring less surface area of an integrated circuit.
• power supply current spikes are reduced because the additional capacitance of an attenuation capacitor is not being repeatedly charged and discharged along with the oscillation capacitor.
• only one external capacitor is connected to the terminals of the device unlike some prior art oscillator circuits that require of at least two external capacitors, an oscillation capacitor and an attenuation capacitor.
• FIG. 1 illustrates, in schematic diagram form, an oscillator circuit 10 in accordance with the prior art.
• a feedback capacitor 30 is connected between an input and an output of a plurality of series-connected inverters 18, 20, 22, and 24.
• the plurality of series-connected inverters functions as a comparator with a reference voltage of about half of the supply voltage.
• the current that charges and discharges the capacitor is generated using a P-channel transistor 12, and N-channel transistors 14 and 28.
• P-channel transistor 12 and N-channel transistor 14 are biased to operate as current sources.
• N-channel transistor 28 functions as a switch in response to a control signal provided by inverter 26.
• an output voltage Nou ⁇ of inverter 24 switches high or low.
• the feedback capacitor 30 coupled between the output terminal of inverter 24 and the input terminal of inverter 18 has the effect of raising the voltage V I ⁇ above the power supply voltage.
• An analysis of oscillator circuit 10 shows that the oscillation frequency of oscillator circuit 10 is a function of the capacitance value of capacitor 30, the amplitude of the voltage swing at the output Nou ⁇ and the amount of current provided by current sources 12 and 14.
• Attenuation capacitor 16, coupled to the input terminal of inverter 18, is used to keep V I ⁇ within the power supply rails because of charge sharing between capacitor 16 and capacitor 30.
• capacitor 16 should generally be at least as large as capacitor 30. Attenuation capacitor 16 had no effect on the oscillation frequency because the attenuation of the voltage swing on V I provided by the capacitor is exactly balanced by the increased effective capacitance charged by the current sources. However, it would be desirable to maintain the voltage swing of V IN within the supply rails without using attenuation capacitor 16.
• FIG. 2 illustrates a waveform of the input and output voltages of oscillator circuit 10 of FIG. 1.
• V IN is at a high voltage.
• V O U T is also at a high voltage.
• Feedback voltage FB is high, causing switch 28 to close, beginning the discharge of capacitors 16 and 30 by current source 14.
• the rate of discharge of capacitors 16 and 30 is illustrated in FIG. 2 by the slope of V I between times tO and tl and is dependent on the size of capacitors 16 and 30.
• the output of inverter 18 becomes a high voltage and V OUT becomes a low voltage. This is the end of the first half-cycle.
• This voltage is coupled to the input node 15 via capacitor 30.
• the output of inverter 26 transitions to a low voltage, thus causing switch 28 to open, or become substantially non-conductive.
• switch 28 is open, capacitors 16 and 30 are now charged toward the power supply voltage V DD as illustrated between times tl and t2.
• the signals switch, ending the second half-cycle.
• capacitor 16 to oscillator 10 does not affect the frequency of oscillation, but is only used to attenuate the voltage swings at V IN -
• integrating attenuation capacitor 16 requires a large amount of surface area on an integrated circuit.
• oscillator circuit 10 may allow oscillator capacitor 30 to be connected externally to the circuit to allow a user to choose the oscillation frequency. In this case, the user must add two capacitors, an oscillator capacitor and an attenuation capacitor.
• FIG. 3 illustrates, in partial block diagram form and partial schematic diagram form, oscillator circuit 40 in accordance with one embodiment of the present invention.
• oscillator circuit 40 may be implemented on an integrated circuit using CMOS (complementary metal-oxide semiconductor) circuit elements.
• Oscillator circuit 40 includes current sources 42 and 46, switch 44, comparator 48, monitor and control circuit 50, capacitor 52 and buffer circuit 54.
• current sources 42 and 46 and switch 44 are connected together in series between a power supply voltage terminal labeled V DD and a power supply voltage terminal labeled Vss- Power supply voltage terminal V DD receives, for example, a power supply voltage of 5 volts and power supply voltage terminal Vss is at ground potential.
• current source 42 is a P-channel transistor and current source is an N-channel transistor biased to function as current sources.
• a first input terminal of comparator 48 is coupled between current source 42 and switch 44 at a node 45 for receiving an input voltage V I .
• a second input terminal receives a threshold voltage labeled THRESHOLD and an output terminal provides an output voltage labeled V OUT -
• the threshold voltage THRESHOLD is about one-half of the power supply voltage, but in other embodiments, the threshold voltage can be different than one-half the power supply voltage.
• the threshold voltage does not directly affect the oscillation frequency and its value is not critical, therefore the comparator 48 can be constructed from a simple CMOS inverter where the effective threshold voltage is inherent in the construction of the inverter and is about midway between the supply voltages.
• Monitor and control circuit 50 has input terminals coupled to monitor both V IN and V OUT. and in response, provides an amplitude controlled output voltage.
• monitor and control circuit 50 may include an N-channel transistor and a P-channel transistor coupled in series between the output of comparator 48 and capacitor 52 with their gates connected to node 45 (not shown).
• Capacitor 52 is coupled between the output of monitor and control circuit 50 and node 45.
• Buffer circuit 54 is coupled to the output of comparator 48 for controlling switch 44. Note that the type of circuit used to implement comparator 48 is not important and can be any circuit that provides a positive output for an input voltage above a predetermined threshold and that provides a negative, or lower output, for an input voltage below the same predetermined threshold.
• oscillator circuit 40 generally functions in a similar manner to oscillator circuit 10 except that instead of using an attenuation capacitor to keep V IN below the supply rails, oscillator circuit 40 uses monitor and control circuit 50. Still referring to FIG. 3, periodic input voltage V I is generated at node 45 by opening and closing switch 44. When switch 44 is open, the current from current source 42 charges capacitor 52 toward V DD - When the voltage at node 45 reaches a predetermined voltage level, monitor and control circuit 50 prevents V I from increasing further by controlling the monitor and control circuit 50 voltage V OUT - In other words, monitor and control circuit 50 controls V OUT in order to prevent V JN from approaching to close to the power supply voltage. As V COMP switches a logic high feedback voltage FB causes switch 44 to close.
• Monitor and control circuit 50 controls the voltage swing of voltage V I by limiting the amount of charge on capacitor 52 without using an attenuation capacitor as shown above with the prior art circuit of FIG. 1. Because only the oscillation capacitor 52 is used, oscillator circuit 40 can be integrated using less surface area. Also, in an embodiment that uses an external oscillator capacitor, only one capacitor needs to be added to the circuit. Note that the configuration of current sources 42 and 46 and switch 44 illustrated in FIG. 3 is only one way of providing a current at node 45. Those skilled in the art will realize that there are other circuits for providing the current the current at node 65. For example, in another embodiment, an additional switch can be added between current source 42 and node 45 for providing additional control.
• FIG. 4 illustrates, in schematic diagram form, oscillator circuit 60 in accordance with another embodiment of the present invention.
• Oscillator circuit 60 includes P-channel transistor 62, N-channel transistors 64 and 66, a plurality of series-connected inverters 68, monitor and control circuit 80, inverter 88, and capacitor 90.
• the plurality of series-connected inverters 68 includes inverters 70, 72, 74, and 76.
• Monitor and control circuit 80 includes P-channel transistor 82 and N-channel transistor 84.
• P-channel transistor 62 has a source connected to power supply voltage terminal V DD , a gate for receiving bias voltage PB IAS , and a drain.
• N- channel transistor 64 has a drain connected to the drain of P-channel transistor 62 at node 65, a gate, and a source.
• N-channel transistor 66 has a drain connected to the source of N-channel transistor 64, a gate for receiving bias voltage N BIAS , and a source connected to power supply voltage terminal VSS.
• P-channel transistor 62 and N-channel transistor 66 both function as switchable current sources that alternately charge and discharge feedback capacitor 90 under the control of feedback signal FB.
• N-channel transistor 64 functions as a switch.
• First inverter 70 of the plurality of series-connected inverters 68 has an input terminal connected to node 65, and an output terminal.
• Inverter 72 has an input terminal connected to the output terminal of inverter 70, and an output terminal.
• Inverter 74 has an input terminal connected to the output terminal of inverter 72, and an output terminal.
• the last inverter 76 includes P-channel transistor 78 and N- channel transistor 86. The gates of transistors 78 and 86 are connected to the output terminal of inverter 74.
• a source of transistor 78 is connected to V DD and a drain of transistor 86 is connected to Vss- Note that in FIG.
• inverter 76 is coupled to V DD and Vss- However, in other embodiments, inverter 76 may be coupled to regulated supply voltage to give more precise control of the oscillation frequency.
• Monitor and control circuit 80 is connected between transistors 78 and 86.
• P-channel transistor 82 has a source connected to the drain of P-channel transistor 78, a gate connected to node 65, and a drain for providing output voltage V OUT - N-channel transistor 84 has a drain connected to the drain of P-channel transistor 82, a gate connected to node 65, and a source connected to the drain of N-channel transistor 86.
• Inverter 88 has an input terminal connected to the output terminal of monitor and control circuit 80, and an output terminal connected to the gate of N-channel transistor 64.
• Capacitor 90 has a first current electrode connected to the output terminal of monitor and control circuit 80, and a second current electrode connected to node 65. Capacitor 90 provides positive feedback in oscillator 60.
• FIG. 5 illustrates a waveform of the input and output voltages of oscillator circuit 60 of FIG. 4.
• the comparator 68 input voltage is low (time tO in FIG. 5)
• the drive voltage of V OUT will be low and the feedback signal FB will switch the current sources 62 and 66 so that the current is flowing into capacitor 90 at the comparator 68 input node 65.
• This voltage will rise until it reaches the comparator threshold.
• the comparator switches and the output voltage V O U T swings from its low level to its high level (between times tO and tl).
• the high level voltage V OUT is coupled via the feedback capacitor 90 back to the comparator input node 65, causing the voltage there to rise by the amount of the output voltage swing (typically V DD )- Just after this occurs, the negative feedback signal FB also switches the direction of the current source to transistor 66, causing the discharge of capacitor 90 to begin at about time tl.
• Negative feedback signal FB will again switch the current source 62 to charge the capacitor and the cycle will begin again at about time t2. The next half cycle between times t2 and t3 occurs in the same manner.
• the value of the comparator 68 threshold voltage does not affect the frequency of oscillator 60. It is only important in regulating the voltage about which the input node swings, which is important as the current sources 62 and 66 may have limitations in the voltage that they can drive, and also may have parasitic diodes that clamp the voltage to no more than a diode drop outside the supply rails. In a typical application, the comparator threshold will be about V DD 2 and therefore the voltage at input node 65 will swing by V D D above and below V DD /2 to 1.5* V DD and - 0.5*V DD - In order to preserve frequency stability, the current source circuits must not clamp this voltage swing.
• an additional attenuation capacitor 16 is coupled at input node 15.
• Capacitor 16 attenuates the voltage swing at input node 15, typically by a factor of 2. Therefore, the voltage swing at node 15 is limited to be between 0 volts and V DD , and is not clamped by parasitic diodes associated with current sources 12 and 14.
• Capacitor 16 has no effect on frequency because at the beginning and end of each half-cycle (i.e. when the input voltage is equal to the comparator threshold voltage), the charge on attenuation capacitor 16 is the same, and the current sources require the same time to inject the same charge as in the case where this capacitor is not used.
• monitor & control circuit 50 of FIG. 3 and monitor and control circuit 80 of FIG. 4 control the voltage swing at the output of the comparator so that V O U T doesn't swing by enough to cause the input voltage to exceed the supply rails.
• the frequency stability is assured because all that matters is that at the time the voltage at the comparator input node is crossing the threshold, the output stage has fully swung to its final levels. To a large extent, what happens in the meantime is irrelevant.
• V OUT swinging from 0 volts to V D D
• V DD 12 the input voltage would swing from V DD 12 to V DD , which is still within the rails.
• the feedback capacitor would begin to discharge and when the voltage decreased to close to V DD 12, V O U T completed its transition fully up to V DD , the capacitor would continue to discharge and eventually the input node would reach the comparator threshold.
• the conditions are the same as if V OUT had swung completely initially, so the time required was the same and the frequency remains controlled.
• the monitor and control circuit monitors the input voltage (to see if it is too close to ground or too close to V DD ), to limit, or control, the swing of V OUT to be below or equal to the predetermined voltage until the input node voltage is moving from one rail toward the other rail.
• Transistor 82 and Transistor 84 of monitor and control circuit 80 of FIG. 4 monitor the voltage at input node 65 and limit the application of V OUT from the drains of transistor 78 and transistor 86) to capacitor 90 so that the voltage at input node 65 does not get closer than a MOS (metal-oxide semiconductor) threshold voltage to the rails.
• MOS metal-oxide semiconductor
• the plurality of series- connected inverters 68 includes four inverters.
• the number of series-connected inverters can be different than four.
• the voltage at which the inverters switch logic states is about one-half of the power supply voltage. In other embodiments, the voltage at which the inverters switch logic states can be different.
• the positions of transistors 82 and 84 can be exchanged with the positions for transistors 78 and 86, respectively.
• Monitor and control circuit 80 maintains the periodic output signal of the comparator within the power supply rails without the use of an attenuation capacitor such as attenuation capacitor 16 in FIG. 1.
• the attenuation capacitor can be eliminated because its presence has no affect on the oscillation frequency.
• the oscillator circuit is smaller, thus saving surface area on the integrated circuit.
• power supply current spikes are reduced because an attenuation capacitor is not being repeatedly charged and discharged along with the oscillation capacitor.
• a user needs to be able to set the oscillation frequency using an externally connected capacitor, only one capacitor needs to be connected, thus reducing the number of externally connected components over the prior art oscillator circuit of FIG. 1.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
• Electronic Switches (AREA)

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• 2002
  • 2002-09-06 US US10/236,230 patent/US6803832B2/en not_active Expired - Lifetime
• 2003
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