WO2004019415A1 - GaN-TYPE ENHANCEMENT MOSFET USING HETERO STRUCTURE - Google Patents

GaN-TYPE ENHANCEMENT MOSFET USING HETERO STRUCTURE Download PDF

Info

Publication number
WO2004019415A1
WO2004019415A1 PCT/US2003/026706 US0326706W WO2004019415A1 WO 2004019415 A1 WO2004019415 A1 WO 2004019415A1 US 0326706 W US0326706 W US 0326706W WO 2004019415 A1 WO2004019415 A1 WO 2004019415A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
gan
transistor
mosfet
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/026706
Other languages
French (fr)
Inventor
Fan Ren
Cammy Rene Abernathy
Stephen J. Pearton
Yoshihiro Irokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Florida
Original Assignee
University of Florida
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Florida filed Critical University of Florida
Priority to AU2003265691A priority Critical patent/AU2003265691A1/en
Publication of WO2004019415A1 publication Critical patent/WO2004019415A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

Definitions

  • the invention relates to an enhancement mode metal oxide semiconductor field effect transistor (MOSFET) formed from a Group-Ill nitride compound semiconductor.
  • MOSFET metal oxide semiconductor field effect transistor
  • Si-based power devices are generally used in high power electronic devices.
  • their performance has almost reached the value predicted by theory and can no longer be significantly improved.
  • alternative devices based on different substrates capable of providing improved performance have been under investigation.
  • Gallium nitride which is a Group-Ill nitride compound semiconductor, has a large forbidden band gap, equal to about 3.4 eV.
  • the indirect transition conduction band is positioned at a level higher than the forbidden band by more than 1.5 eV.
  • the saturation velocity of GaN is approximately 2.5. x 10 7 cm/s, which is higher than other types of semiconductors, such as silicon (Si), gallium arsenide (GaAs), and silicon carbide (SiC).
  • the breakdown electric field of GaN is approximately 5 x 10 6 V/cm, which is greater than SiC, and greater than Si and GaAs by more than one order of magnitude.
  • GaN has physical characteristics that are suitable for use in high-frequency, high-temperature, and high-power semiconductor devices.
  • a conventional FET using GaN is a Schottkey gate transistor having a metal semiconductor (MES) structure.
  • An n-type GaN active layer is formed on a sapphire substrate with an intrinsic-GaN buffer layer therebetween.
  • a gate electrode, a source electrode, and a drain electrode are disposed on the active layer.
  • An alternate Schottkey gate FET structure referred to as a high electron mobility transistor (HEMT) structure, includes an electron transit layer made from impurity-undoped GaN and an electron supply layer made from n-type AlGaN which are sequentially laminated on a substrate, such as a sapphire substrate.
  • a gate electrode is formed on the electron supply layer, and a source electrode and a drain electrode are disposed on the electron transit layer on both sides of the electron supply layer.
  • the thickness of the AlGaN electron supply layer is decreased, thereby making the threshold gate voltage around 0 V.
  • This type of FET is referred to as a "enhancement-mode FET", but is not a true enhancement mode FET as it does not require a positive gate voltage to turn on.
  • the Schottky barrier at the gate electrode between a metal and the semiconductor is comparatively low, such as approximately from 1 to 1.2 eV.
  • this Schottky barrier is slightly greater than that of the GaAs-type FETs (0.7 eV), a large forward gate bias voltage cannot be applied.
  • This shortcoming originates from the operation of the MES-structured FET rather than from the constituent material, such as GaN.
  • MOSFET metal- oxide-semiconductor field effect transistor
  • the substrate generally used is silicon
  • SiO 2 silicon oxide
  • the silicon dioxide film provides a highly electrically insulating film.
  • an inversion layer is formed at the Si interface between the SiO 2 film and the Si layer through application of a sufficient gate to body (or source) voltage.
  • N-channel GaN based depletion MOSFETs of MOSHEMTs have been realized without the need for impurity doping in the channel region.
  • AlGaN/GaN heterojunctions experience large piezoelectric effects which generate a large interface charge.
  • the large interface charge can induce an electron sheet in the GaN near its interface with AlGaN.
  • GaN based depletion mode MOSFETs Some have disclosed GaN based depletion mode MOSFETs. Some have even claimed to disclose "enhancement mode GaN based MOSFETs". However, the disclosed "enhancement mode GaN based MOSFET" devices are not truly enhancement mode devices since an enhancement MOSFET is characterized as a MOS device which forms a channel only when the gate to body (or source) voltage exceeds some threshold voltage. Accordingly, there is a need for true GaN based enhancement mode MOSFETs.
  • a GaN-based enhancement mode MOSFET includes a GaN comprising layer and a (Group III)xGa ⁇ - x N layer, where x is from 0 to 1, such as AlxGa ⁇ - x N, disposed on the GaN comprising layer.
  • x is from 0 to 1
  • AlxGa ⁇ - x N disposed on the GaN comprising layer.
  • the Group III element will be referred to herein as being Al, the group III element can be other Group III species, such as B, or mixtures thereof.
  • the thickness of the AlxGa ⁇ - x N layer is less than 20 nm. This provides negligible sheet carrier concentration in the GaN layer at its interface with Al x Ga ⁇ - x N to permit enhancement mode operation. Typically, at some Al x Ga ⁇ - x N thickness value from 10 to about 20 nm, the device will become a depletion mode device for any thickness above this value.
  • a source and a drain region extend through the Al x Ga ⁇ - x N layer into the GaN layer, the source and drain region separated by a channel region.
  • a gate dielectric is disposed over the channel region.
  • the gate dielectric layer can be SiN x , MgO or Sc O 3 .
  • a gate electrode is disposed on the gate dielectric.
  • the MOSFET formed is a true enhancement MOSFET which is in an off-state when the gate is unbiased.
  • the parameter x is preferably from 0.2 to 0.35.
  • the enhancement MOSFET can be either an n-channel or a p-channel device.
  • the Al x Ga ⁇ - x N layer can be undoped or p-doped.
  • the thickness of the Al x Ga ⁇ - x N layer can be less than 10 nm, less than 5 nm, or more preferably from 1 to 4 nm thick.
  • the GaN comprising layer can be p-GaN, undoped GaN or InGaN.
  • a p- AlGaN or undoped AlGaN layer can be disposed below the GaN comprising layer.
  • FIG. 1(a) illustrates an n-channel GaN based enhancement mode MOSFET according to an embodiment of the invention.
  • FIG. 1(b) illustrates an n-channel GaN based enhancement mode MOSFET according to an alternate embodiment of the invention.
  • FIG. 2(a) illustrates the band-structure for the p-AlGaN/GaN heteroj unctions for the AlGaN/GaN MOSFET transistors shown in FIGs. 1(a) and 1(b) with no applied voltage to the gate.
  • FIG. 2(b) illustrates the band-structure for the p- AlGaN/GaN heteroj unctions for the AlGaN/GaN MOSFET transistors shown in FIGs. 1(a) and 1(b) evidencing two inversion channels.
  • a GaN-based enhancement mode MOSFET includes a GaN comprising layer and a (Group III) x Ga ⁇ - x N layer disposed on the GaN layer, where x is between 0 and 1.
  • x is between 0 and 1.
  • the Group III element will be referred to herein as being Al, the group III element can be other Group III species, such as B, or mixtures thereof.
  • the thickness of the Al x Ga ⁇ - x N layer to provide enhancement mode operation is below a certain thickness.
  • a Al x Ga ⁇ - x N layer thickness of approximately 20 nm or less, such as 10 nm, preferably less than 5 nm, and more preferably from 1-4 nm, negligible sheet carrier concentration in the GaN layer at its interface with Al x Ga ⁇ - x N results. Accordingly, the surface of the GaN adjacent to the Al x Ga ⁇ - x N layer can be rendered undoped or even p-type.
  • a source and a drain region each extend through the Al x Ga ⁇ - x N layer into the GaN layer, the source and drain region separated by a channel region.
  • a gate dielectric is disposed over the channel region.
  • a gate electrode is disposed on the gate dielectric.
  • the MOSFET formed is a true enhancement MOSFET which is in an off state when the gate is unbiased.
  • x can be from .05 to 1.0. Preferably, x ranges from 0.2 to 0.35.
  • the invention can be used to produce a true enhancement mode GaN based MOSFET.
  • the invention provides at least two significant advantages as compared to conventional MOSFETs.
  • the thin AlGaN surface layer can protect the GaN channel from being damaged during the deposition of the gate oxide layer. This leads to higher carrier mobility in the GaN layer.
  • the transistor structure forms a GaN quantum well at AlGaN/GaN interface, which can provide better carrier confinement, improved carrier mobility and carrier concentration.
  • the invention can be embodied as either a p-channel or n-channel MOSFET. In the case of an n-channel MOSFET, an epitaxial layer stack comprising p-type or undoped AlGaN and GaN can be used.
  • an epitaxial layer stack comprising n-type or undoped AlGaN and GaN can be used.
  • n-channel MOSFETs and p-channel MOSFETs can formed using the same epitaxial layer stack.
  • the invention is preferably embodied using n-channel MOSFETs due to their improved performance as compared to p-channel MOSFETs.
  • transistor 100 includes gate electrode 110 disposed on gate dielectric layer 115.
  • Gate dielectric layer 115 can be any suitable dielectric, such as SiO 2 , SiNx, MgO or Sc 2 O .
  • Gate dielectric layer 115 is disposed on a thin layer of p-type or undoped AlGaN 120. It may be possible to replace the Al in layer 120 with certain group III elements, such as boron.
  • the thin AlGaN layer 120 is disposed on a p-type or undoped GaN layer 125 to form a vertical heterostructure.
  • the invention can also be used to form vertical MOSFETs.
  • the gate and source contacts are on the front of the substrate the drain is located on the back side of the Jsubstrate.
  • the advantage of vertical MOSFETs is that the breakdown voltage from drain to source can be extremely high since the drift region for the vertical MOSFET is the entire thickness of the substrate.
  • Transistor 100 also comprises n+ source 130 and n+ drain 135 regions.
  • the depth of regions 130 and 135 is preferably 300 to 400 nm.
  • Si or Ge can be used as the n dopant.
  • the thickness of the AlGaN layer 120 can be from about 0.5 nm to about 20 nm, preferably being about 4 to 5 nm. However, if a p- AlGaN layer 120 thicker than about 10 nm is used, the device performance will generally be degraded as compared to a thinner p-AlGaN layer 120 due to longer distance between the gate 110 and the inversion channel (not shown).
  • the p-AlGaN layer 120 comprises a thick undoped AlGaN layer, such as > 20 nm, an n-channel will generally be formed at the AlGaN/GaN interface due to the piezoelectric effect. This will result in the formation of a depletion mode n-channel MOSFET device.
  • n-type GaN can comprise Si-doped GaN.
  • P+ source and drain regions, such as magnesium doped regions, are then formed in the AlGaN/GaN layer stack, such as through ion implantation of Mg or selective area re-growth of Mg-doped GaN.
  • Transistor 100 provides a heteroj unction layer between AlGaN layer 120 and GaN layer 125. Since A1N has a band gap of about 6.4 eV which is almost double as compared to GaN (about 3.3 eV), AlGaN can be appropriately treated as an insulator as compared to the GaN layer. Therefore, transistor 100 can form both a first inversion layer at the surface of AlGaN layer 120 adjacent to gate dielectric layer 115, as well as a second inversion layer in the GaN layer 125 near the AlGaN/GaN interface.
  • the inversion channel in the GaN layer 125 at the AlGaN/GaN interface will be at a lower threshold voltage as compared to the first inversion layer formed at the surface of AlGaN layer 120 adjacent to gate dielectric layer 115.
  • Transistor 150 includes gate electrode 160, disposed on gate dielectric layer 165, which is disposed on a thin layer of p-type or un-doped AlGaN 170.
  • the AlGaN layer is disposed on a layer of InGaN 175, which is disposed on a layer of AlGaN 180.
  • transistor 150 includes two vertical heterostructures.
  • Transistor 150 includes n+ source 185 and drain 190 regions.
  • the depth of regions 185 and 190 is preferably from about 300 to 400 nm.
  • Figure 2(a) shows the band-structure for the p-AlGaN/GaN heteroj unctions for the
  • n-channel enhancement mode transistor 100 or 150 As the gate to source voltage of n-channel enhancement mode transistor 100 or 150 is increased to some positive (“threshold") voltage above the source or body voltage, an inversion channel 250 between the AlGaN layer 120 and the GaN layer 125 will generally be first induced. As the gate voltage is further increased, a second inversion channel 240 at the interface between the gate dielectric 115 and the AlGaN layer 120 is generally also induced, thus providing two inversion n-channels.
  • Figure 2(b) shows the band structure following application of a sufficiently positive voltage to the gate relative to the source or body of the device to create n-channels 240 and 250. As a result of the band structure shown in FIG.
  • devices according to the invention can provide a normally-off, enhancement mode power MOSFET.
  • the invention can find applications in inverter systems, analogous to a standard Si based CMOS inverter layouts for use in high power electronics.
  • the invention can generally be operated at high temperature without a cooling system, because GaN is a wide band gap semiconductor and the switching loss of the enhancement mode FETs according to the invention is low.
  • Enhancement mode devices use less power as compared to depletion mode devices because enhancement mode devices, unlike depletion mode devices, generally consume little or no power during stand-by mode.
  • the invention can reduce switching loss.
  • the invention may also provide improved breakdown voltages as compared to other available structures.
  • a voltage across a gate of a MOSFET produces an electrical field which is distributed through the oxide and semiconductor, the magnitude of which is proportional to the dielectric constant of the oxide.
  • the dielectric constant of MgO and Sc 2 O which can be used for the gate oxide 115 are much higher than that of SiO 2 . Accordingly, the gate to source or body breakdown voltage of the GaN MOSFET should be higher as compared to a GaN MESFET or a Si-MOSFET.
  • the use of high dielectric constant oxide layers permit use of thinner oxide layers. This arrangement provides higher drain current and transconductance.
  • An ideal market for the invention is for high power electronics devices.
  • the invention can be particularly useful.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A GaN based enhancement mode MOSFET includes a GaN layer and a (Group IIII)XGa1-XN layer, such as an Al XGa1-XN disposed on the GaN layer. The thickness of the A1XGa1-XN layer is less than 20 nm to provide a negligible sheet carrier concentration in the GaN layer along its interface with A1XGa1-XN. A source and a drain region extend through the A1XGa1-XN layer into the GaN layer, the source and drain region separated by a channel region. A gate dielectric is disposed over the channel region. A gate electrode is disposed on the gate dielectric. The MOSFET formed is a true enhancement MOSFET which is in an off state when the gate is unbiased.

Description

GaN-TYPE ENHANCEMENT MOSFET USING HETERO STRUCTURE
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
The United States Government has rights in this invention pursuant to Grant No. N00014 99 1 0204 between the Office of Naval Research and the University of Florida.
Field of the Invention
The invention relates to an enhancement mode metal oxide semiconductor field effect transistor (MOSFET) formed from a Group-Ill nitride compound semiconductor.
Background Historically, device performance improvements have been achieved by scaling.
However, fundamental limits to device scaling are being reached and problems related to scaling are becoming more significant. Currently, Si-based power devices are generally used in high power electronic devices. However, their performance has almost reached the value predicted by theory and can no longer be significantly improved. Accordingly, alternative devices based on different substrates capable of providing improved performance have been under investigation.
One area that still has not been fully exploited is the engineering of substrates to achieve higher carrier mobility. Gallium nitride (GaN), which is a Group-Ill nitride compound semiconductor, has a large forbidden band gap, equal to about 3.4 eV. The indirect transition conduction band is positioned at a level higher than the forbidden band by more than 1.5 eV. The saturation velocity of GaN is approximately 2.5. x 107 cm/s, which is higher than other types of semiconductors, such as silicon (Si), gallium arsenide (GaAs), and silicon carbide (SiC). Further, the breakdown electric field of GaN is approximately 5 x 106 V/cm, which is greater than SiC, and greater than Si and GaAs by more than one order of magnitude. Thus, GaN has physical characteristics that are suitable for use in high-frequency, high-temperature, and high-power semiconductor devices.
A conventional FET using GaN is a Schottkey gate transistor having a metal semiconductor (MES) structure. An n-type GaN active layer is formed on a sapphire substrate with an intrinsic-GaN buffer layer therebetween. A gate electrode, a source electrode, and a drain electrode are disposed on the active layer.
An alternate Schottkey gate FET structure, referred to as a high electron mobility transistor (HEMT) structure, includes an electron transit layer made from impurity-undoped GaN and an electron supply layer made from n-type AlGaN which are sequentially laminated on a substrate, such as a sapphire substrate. A gate electrode is formed on the electron supply layer, and a source electrode and a drain electrode are disposed on the electron transit layer on both sides of the electron supply layer.
In another example of known GaN based FETs having the HEMT structure, the thickness of the AlGaN electron supply layer is decreased, thereby making the threshold gate voltage around 0 V. This type of FET is referred to as a "enhancement-mode FET", but is not a true enhancement mode FET as it does not require a positive gate voltage to turn on.
In the foregoing MES or HEMT-structured FETs, the Schottky barrier at the gate electrode between a metal and the semiconductor is comparatively low, such as approximately from 1 to 1.2 eV. Although this Schottky barrier is slightly greater than that of the GaAs-type FETs (0.7 eV), a large forward gate bias voltage cannot be applied. This shortcoming originates from the operation of the MES-structured FET rather than from the constituent material, such as GaN.
In contrast, large forward gate bias voltages are possible from a conventional metal- oxide-semiconductor field effect transistor (MOSFET), where the substrate generally used is silicon, h this type of FET, a gate electrode is formed on a Si layer with a silicon oxide (SiO2) film therebetween. The silicon dioxide film provides a highly electrically insulating film. For enhancement-type MOSFETs, an inversion layer is formed at the Si interface between the SiO2 film and the Si layer through application of a sufficient gate to body (or source) voltage.
N-channel GaN based depletion MOSFETs of MOSHEMTs have been realized without the need for impurity doping in the channel region. AlGaN/GaN heterojunctions experience large piezoelectric effects which generate a large interface charge. The large interface charge can induce an electron sheet in the GaN near its interface with AlGaN.
Some have disclosed GaN based depletion mode MOSFETs. Some have even claimed to disclose "enhancement mode GaN based MOSFETs". However, the disclosed "enhancement mode GaN based MOSFET" devices are not truly enhancement mode devices since an enhancement MOSFET is characterized as a MOS device which forms a channel only when the gate to body (or source) voltage exceeds some threshold voltage. Accordingly, there is a need for true GaN based enhancement mode MOSFETs.
SUMMARY OF THE INVENTION
A GaN-based enhancement mode MOSFET includes a GaN comprising layer and a (Group III)xGaι-xN layer, where x is from 0 to 1, such as AlxGaι-xN, disposed on the GaN comprising layer. Although the Group III element will be referred to herein as being Al, the group III element can be other Group III species, such as B, or mixtures thereof.
The thickness of the AlxGaι-xN layer is less than 20 nm. This provides negligible sheet carrier concentration in the GaN layer at its interface with AlxGaι-xN to permit enhancement mode operation. Typically, at some AlxGaι-xN thickness value from 10 to about 20 nm, the device will become a depletion mode device for any thickness above this value.
A source and a drain region extend through the AlxGaι-xN layer into the GaN layer, the source and drain region separated by a channel region. A gate dielectric is disposed over the channel region. The gate dielectric layer can be SiNx, MgO or Sc O3. A gate electrode is disposed on the gate dielectric. The MOSFET formed is a true enhancement MOSFET which is in an off-state when the gate is unbiased.
The parameter x is preferably from 0.2 to 0.35. The enhancement MOSFET can be either an n-channel or a p-channel device.
The AlxGaι-xN layer can be undoped or p-doped. The thickness of the AlxGaι-xN layer can be less than 10 nm, less than 5 nm, or more preferably from 1 to 4 nm thick.
The GaN comprising layer can be p-GaN, undoped GaN or InGaN. In one embodiment of the invention, a p- AlGaN or undoped AlGaN layer can be disposed below the GaN comprising layer. BRIEF DESCRIPTION OF THE DRAWINGS
A fuller understanding of the present invention and the features and benefits thereof will be accomplished upon review of the following detailed description together with the accompanying drawings, in which:
FIG. 1(a) illustrates an n-channel GaN based enhancement mode MOSFET according to an embodiment of the invention.
FIG. 1(b) illustrates an n-channel GaN based enhancement mode MOSFET according to an alternate embodiment of the invention.
FIG. 2(a) illustrates the band-structure for the p-AlGaN/GaN heteroj unctions for the AlGaN/GaN MOSFET transistors shown in FIGs. 1(a) and 1(b) with no applied voltage to the gate.
FIG. 2(b) illustrates the band-structure for the p- AlGaN/GaN heteroj unctions for the AlGaN/GaN MOSFET transistors shown in FIGs. 1(a) and 1(b) evidencing two inversion channels.
DETAILED DESCRIPTION OF THE INVENTION A GaN-based enhancement mode MOSFET includes a GaN comprising layer and a (Group III)xGaι-xN layer disposed on the GaN layer, where x is between 0 and 1. As noted earlier, although the Group III element will be referred to herein as being Al, the group III element can be other Group III species, such as B, or mixtures thereof.
The thickness of the AlxGaι-xN layer to provide enhancement mode operation is below a certain thickness. By providing a AlxGaι-xN layer thickness of approximately 20 nm or less, such as 10 nm, preferably less than 5 nm, and more preferably from 1-4 nm, negligible sheet carrier concentration in the GaN layer at its interface with AlxGaι-xN results. Accordingly, the surface of the GaN adjacent to the AlxGaι-xN layer can be rendered undoped or even p-type. A source and a drain region each extend through the AlxGaι-xN layer into the GaN layer, the source and drain region separated by a channel region.
A gate dielectric is disposed over the channel region. A gate electrode is disposed on the gate dielectric. The MOSFET formed is a true enhancement MOSFET which is in an off state when the gate is unbiased.
Regarding the composition of the AlxGaι-xN layer, x can be from .05 to 1.0. Preferably, x ranges from 0.2 to 0.35.
The invention can be used to produce a true enhancement mode GaN based MOSFET. Thus, the invention provides at least two significant advantages as compared to conventional MOSFETs. First, the thin AlGaN surface layer can protect the GaN channel from being damaged during the deposition of the gate oxide layer. This leads to higher carrier mobility in the GaN layer. Second, the transistor structure forms a GaN quantum well at AlGaN/GaN interface, which can provide better carrier confinement, improved carrier mobility and carrier concentration. The invention can be embodied as either a p-channel or n-channel MOSFET. In the case of an n-channel MOSFET, an epitaxial layer stack comprising p-type or undoped AlGaN and GaN can be used. To form a p-channel MOSFET, an epitaxial layer stack comprising n-type or undoped AlGaN and GaN can be used. Thus, using undoped base epi, both n-channel MOSFETs and p-channel MOSFETs can formed using the same epitaxial layer stack. When non-complementary structures are not required for a given application, the invention is preferably embodied using n-channel MOSFETs due to their improved performance as compared to p-channel MOSFETs.
Two exemplary embodiments of n-channel enhancement MOSFETs according to the invention are shown in FIGs. 1(a) and 1(b), respectively. Referring to FIG. 1(a), transistor 100 includes gate electrode 110 disposed on gate dielectric layer 115. Gate dielectric layer 115 can be any suitable dielectric, such as SiO2, SiNx, MgO or Sc2O . Gate dielectric layer 115 is disposed on a thin layer of p-type or undoped AlGaN 120. It may be possible to replace the Al in layer 120 with certain group III elements, such as boron.
The thin AlGaN layer 120 is disposed on a p-type or undoped GaN layer 125 to form a vertical heterostructure. Although not described in detail herein, the invention can also be used to form vertical MOSFETs. In a vertical MOSFET, the gate and source contacts are on the front of the substrate the drain is located on the back side of the Jsubstrate. The advantage of vertical MOSFETs is that the breakdown voltage from drain to source can be extremely high since the drift region for the vertical MOSFET is the entire thickness of the substrate.
Transistor 100 also comprises n+ source 130 and n+ drain 135 regions. The depth of regions 130 and 135 is preferably 300 to 400 nm. For example, Si or Ge can be used as the n dopant. The thickness of the AlGaN layer 120 can be from about 0.5 nm to about 20 nm, preferably being about 4 to 5 nm. However, if a p- AlGaN layer 120 thicker than about 10 nm is used, the device performance will generally be degraded as compared to a thinner p-AlGaN layer 120 due to longer distance between the gate 110 and the inversion channel (not shown). If the p-AlGaN layer 120 comprises a thick undoped AlGaN layer, such as > 20 nm, an n-channel will generally be formed at the AlGaN/GaN interface due to the piezoelectric effect. This will result in the formation of a depletion mode n-channel MOSFET device.
To form a p-channel enhancement mode MOSFETs, the steps described above for forming an n-channel MOSFET can generally be repeated, except an undoped or n-type AlGaN and GaN layer stack is provided, rather than p- or undoped AlGaN and GaN. For example, n-type GaN can comprise Si-doped GaN. P+ source and drain regions, such as magnesium doped regions, are then formed in the AlGaN/GaN layer stack, such as through ion implantation of Mg or selective area re-growth of Mg-doped GaN.
Transistor 100 provides a heteroj unction layer between AlGaN layer 120 and GaN layer 125. Since A1N has a band gap of about 6.4 eV which is almost double as compared to GaN (about 3.3 eV), AlGaN can be appropriately treated as an insulator as compared to the GaN layer. Therefore, transistor 100 can form both a first inversion layer at the surface of AlGaN layer 120 adjacent to gate dielectric layer 115, as well as a second inversion layer in the GaN layer 125 near the AlGaN/GaN interface. Since GaN has lower energy band gap, the inversion channel in the GaN layer 125 at the AlGaN/GaN interface will be at a lower threshold voltage as compared to the first inversion layer formed at the surface of AlGaN layer 120 adjacent to gate dielectric layer 115.
An alternate embodiment of an n-channel enhancement mode transistor 150 is shown in FIG. 1(b). Transistor 150 includes gate electrode 160, disposed on gate dielectric layer 165, which is disposed on a thin layer of p-type or un-doped AlGaN 170. The AlGaN layer is disposed on a layer of InGaN 175, which is disposed on a layer of AlGaN 180. Thus, transistor 150 includes two vertical heterostructures.
Transistor 150 includes n+ source 185 and drain 190 regions. The depth of regions 185 and 190 is preferably from about 300 to 400 nm.
Figure 2(a) shows the band-structure for the p-AlGaN/GaN heteroj unctions for the
AlGaN/GaN MOSFET transistors shown in FIGs. 1(a) and 1(b) with no applied voltage to the gate. In this state, no n-channel exists in both the AlGaN 120 and GaN layer 125 since the conduction band edge (Ec) is above the Fermi level (Ef) for both layers. Thus, assuming the device does not punchthrough from source to drain, negligible current will flow between the source and drain even if a large voltage is imposed between the source and the drain. Thus, the device formed is clearly a true enhancement mode device.
As the gate to source voltage of n-channel enhancement mode transistor 100 or 150 is increased to some positive ("threshold") voltage above the source or body voltage, an inversion channel 250 between the AlGaN layer 120 and the GaN layer 125 will generally be first induced. As the gate voltage is further increased, a second inversion channel 240 at the interface between the gate dielectric 115 and the AlGaN layer 120 is generally also induced, thus providing two inversion n-channels. Figure 2(b) shows the band structure following application of a sufficiently positive voltage to the gate relative to the source or body of the device to create n-channels 240 and 250. As a result of the band structure shown in FIG. 2(b), electrons can easily flow between the source and drain upon application of a voltage between the source and drain. With the gate voltage removed, no channel is present and the device is in an off state. Thus, devices according to the invention can provide a normally-off, enhancement mode power MOSFET. The invention can find applications in inverter systems, analogous to a standard Si based CMOS inverter layouts for use in high power electronics. Significantly, the invention can generally be operated at high temperature without a cooling system, because GaN is a wide band gap semiconductor and the switching loss of the enhancement mode FETs according to the invention is low. Enhancement mode devices use less power as compared to depletion mode devices because enhancement mode devices, unlike depletion mode devices, generally consume little or no power during stand-by mode. Thus, the invention can reduce switching loss.
The invention may also provide improved breakdown voltages as compared to other available structures. A voltage across a gate of a MOSFET produces an electrical field which is distributed through the oxide and semiconductor, the magnitude of which is proportional to the dielectric constant of the oxide. The dielectric constant of MgO and Sc2O which can be used for the gate oxide 115, are much higher than that of SiO2. Accordingly, the gate to source or body breakdown voltage of the GaN MOSFET should be higher as compared to a GaN MESFET or a Si-MOSFET. Also, the use of high dielectric constant oxide layers permit use of thinner oxide layers. This arrangement provides higher drain current and transconductance.
An ideal market for the invention is for high power electronics devices. For example, for automobile applications where circuits must withstand a high temperature environment without additional cooling systems, such as beyond the capabilities of Si-based technology (e.g. > 200 °C) or more, the invention can be particularly useful.
It is to be understood that while the invention has been described in conjunction with the preferred specific embodiments thereof, that the foregoing description as well as the examples which follow are intended to illustrate and not limit the scope of the invention. Other aspects, advantages and modifications within the scope of the invention will be apparent to those skilled in the art to which the invention pertains.

Claims

We claim:
1. A GaN based enhancement mode MOSFET, comprising: a GaN comprising layer; a (Group III)xGaι-xN layer, where x is from 0 to 1, disposed on said GaN layer, a thickness of said (Group III)xGaι-xN layer being less than 20 nm; a source and a drain extending through said (Group III)xGaι-xN layer into said GaN layer, said source and drain separated by a channel region, a gate dielectric layer disposed over said channel region, and a gate electrode disposed on said gate dielectric, wherein said MOSFET is in an off-state when said gate is not biased.
2. The transistor of claim 1, wherein said Group III element comprises Al.
3. The transistor of claim 1, wherein x is from 0.2 to 0.35.
4. The transistor of claim 1, wherein said Group III element comprises B.
5. The transistor of claim 1, wherein MOSFET is an n-channel MOSFET.
6. The transistor of claim 1, wherein MOSFET is a p-channel MOSFET.
7. The transistor of claim 1, wherein said (Group III)xGaι-xN layer is undoped.
8. The transistor of claim 1 , wherein said (Group III)xGaι-xN layer is p-doped.
9. The transistor of claim 1 , wherein said thickness of said (Group III)xGaι-xN layer is less than 10 nm thick.
10. The transistor of claim 1 , wherein said thickness of said (Group III)xGaι-xN layer is less than 5 nm thick.
11. The transistor of claim 1 , wherein said thickness of said (Group III)xGaι -xN layer is 1 to 4 nm thick.
12. The transistor of claim 1, wherein said GaN comprising layer is selected from the group consisting of p-GaN, undoped GaN and InGaN.
13. The transistor of claim 1 , further comprising a p- AlGaN or undoped AlGaN layer disposed below said GaN comprising layer.
14. The transistor of claim 1, wherein said gate dielectric layer comprises SiNx, MgO or Sc2O3.
PCT/US2003/026706 2002-08-26 2003-08-26 GaN-TYPE ENHANCEMENT MOSFET USING HETERO STRUCTURE Ceased WO2004019415A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003265691A AU2003265691A1 (en) 2002-08-26 2003-08-26 GaN-TYPE ENHANCEMENT MOSFET USING HETERO STRUCTURE

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US40596402P 2002-08-26 2002-08-26
US60/405,964 2002-08-26

Publications (1)

Publication Number Publication Date
WO2004019415A1 true WO2004019415A1 (en) 2004-03-04

Family

ID=31946950

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/026706 Ceased WO2004019415A1 (en) 2002-08-26 2003-08-26 GaN-TYPE ENHANCEMENT MOSFET USING HETERO STRUCTURE

Country Status (3)

Country Link
US (1) US6914273B2 (en)
AU (1) AU2003265691A1 (en)
WO (1) WO2004019415A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107623032A (en) * 2017-10-24 2018-01-23 电子科技大学 A Novel GaN Heterojunction Field Effect Transistor

Families Citing this family (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7320235B2 (en) * 2001-12-05 2008-01-22 Nexpak Corporation Lockable media storage container
US7649215B2 (en) * 2003-12-05 2010-01-19 International Rectifier Corporation III-nitride device passivation and method
JP4744109B2 (en) * 2004-07-20 2011-08-10 トヨタ自動車株式会社 Semiconductor device and manufacturing method thereof
US20060102931A1 (en) * 2004-11-17 2006-05-18 Thomas Edward Kopley Field effect transistor having a carrier exclusion layer
US7800097B2 (en) * 2004-12-13 2010-09-21 Panasonic Corporation Semiconductor device including independent active layers and method for fabricating the same
US20060148182A1 (en) * 2005-01-03 2006-07-06 Suman Datta Quantum well transistor using high dielectric constant dielectric layer
US8432145B2 (en) * 2005-02-02 2013-04-30 International Rectifier Corporation Voltage supply circuit including a III-nitride based power semiconductor device
US20060226442A1 (en) * 2005-04-07 2006-10-12 An-Ping Zhang GaN-based high electron mobility transistor and method for making the same
US7485512B2 (en) 2005-06-08 2009-02-03 Cree, Inc. Method of manufacturing an adaptive AIGaN buffer layer
US7326971B2 (en) * 2005-06-08 2008-02-05 Cree, Inc. Gallium nitride based high-electron mobility devices
US7364988B2 (en) * 2005-06-08 2008-04-29 Cree, Inc. Method of manufacturing gallium nitride based high-electron mobility devices
US7420226B2 (en) * 2005-06-17 2008-09-02 Northrop Grumman Corporation Method for integrating silicon CMOS and AlGaN/GaN wideband amplifiers on engineered substrates
US8183595B2 (en) * 2005-07-29 2012-05-22 International Rectifier Corporation Normally off III-nitride semiconductor device having a programmable gate
US8044432B2 (en) * 2005-11-29 2011-10-25 The Hong Kong University Of Science And Technology Low density drain HEMTs
US7932539B2 (en) * 2005-11-29 2011-04-26 The Hong Kong University Of Science And Technology Enhancement-mode III-N devices, circuits, and methods
TW200733248A (en) * 2005-11-29 2007-09-01 Univ Hong Kong Science & Techn Monolithic integration of enhancement-and depletion-mode AlGaN/GaN HFETs
US7972915B2 (en) * 2005-11-29 2011-07-05 The Hong Kong University Of Science And Technology Monolithic integration of enhancement- and depletion-mode AlGaN/GaN HFETs
US7592213B2 (en) * 2005-12-29 2009-09-22 Intel Corporation Tensile strained NMOS transistor using group III-N source/drain regions
WO2007116238A1 (en) * 2006-04-11 2007-10-18 Picogiga METHOD OF MANUFACTURING A GaN MOSFET
JP2007329350A (en) * 2006-06-08 2007-12-20 Matsushita Electric Ind Co Ltd Semiconductor device
US7964895B2 (en) * 2006-10-05 2011-06-21 International Rectifier Corporation III-nitride heterojunction semiconductor device and method of fabrication
US7863877B2 (en) * 2006-12-11 2011-01-04 International Rectifier Corporation Monolithically integrated III-nitride power converter
CN101312207B (en) * 2007-05-21 2011-01-05 西安捷威半导体有限公司 Enhancement type HEMT device structure and its manufacture method
US8395132B2 (en) * 2007-06-25 2013-03-12 International Rectifier Corporation Ion implanting while growing a III-nitride layer
US8093597B2 (en) * 2007-06-25 2012-01-10 International Rectifier Corporation In situ dopant implantation and growth of a III-nitride semiconductor body
US8502323B2 (en) * 2007-08-03 2013-08-06 The Hong Kong University Of Science And Technology Reliable normally-off III-nitride active device structures, and related methods and systems
US7875537B2 (en) * 2007-08-29 2011-01-25 Cree, Inc. High temperature ion implantation of nitride based HEMTs
US20090072269A1 (en) * 2007-09-17 2009-03-19 Chang Soo Suh Gallium nitride diodes and integrated components
US7915643B2 (en) 2007-09-17 2011-03-29 Transphorm Inc. Enhancement mode gallium nitride power devices
US8076699B2 (en) * 2008-04-02 2011-12-13 The Hong Kong Univ. Of Science And Technology Integrated HEMT and lateral field-effect rectifier combinations, methods, and systems
US8519438B2 (en) 2008-04-23 2013-08-27 Transphorm Inc. Enhancement mode III-N HEMTs
US20110137184A1 (en) * 2008-08-19 2011-06-09 Fan Ren Pressure sensing
US8289065B2 (en) 2008-09-23 2012-10-16 Transphorm Inc. Inductive load power switching circuits
US20100084687A1 (en) * 2008-10-03 2010-04-08 The Hong Kong University Of Science And Technology Aluminum gallium nitride/gallium nitride high electron mobility transistors
US7898004B2 (en) 2008-12-10 2011-03-01 Transphorm Inc. Semiconductor heterostructure diodes
WO2010118090A1 (en) * 2009-04-08 2010-10-14 Efficient Power Conversion Corporation Enhancement mode gallium nitride transistor with improved gate characteristics
US8742459B2 (en) * 2009-05-14 2014-06-03 Transphorm Inc. High voltage III-nitride semiconductor devices
US8390000B2 (en) 2009-08-28 2013-03-05 Transphorm Inc. Semiconductor devices with field plates
US20110068348A1 (en) * 2009-09-18 2011-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Thin body mosfet with conducting surface channel extensions and gate-controlled channel sidewalls
US8389977B2 (en) 2009-12-10 2013-03-05 Transphorm Inc. Reverse side engineered III-nitride devices
US8344421B2 (en) 2010-05-11 2013-01-01 Iqe Rf, Llc Group III-nitride enhancement mode field effect devices and fabrication methods
US9299821B2 (en) 2010-06-23 2016-03-29 Cornell University Gated III-V semiconductor structure and method
TWI409951B (en) * 2010-10-20 2013-09-21 Nat Univ Tsing Hua Enhancement mode gan-based mosfet
US8742460B2 (en) 2010-12-15 2014-06-03 Transphorm Inc. Transistors with isolation regions
US8895993B2 (en) 2011-01-31 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Low gate-leakage structure and method for gallium nitride enhancement mode transistor
CN103348480B (en) * 2011-01-31 2016-11-16 宜普电源转换公司 Being ion implanted and alignment grid electrode structure voluntarily for gallium nitride transistor
US8643062B2 (en) 2011-02-02 2014-02-04 Transphorm Inc. III-N device structures and methods
JP5866769B2 (en) * 2011-02-16 2016-02-17 富士通株式会社 Semiconductor device, power supply device and amplifier
US8772842B2 (en) 2011-03-04 2014-07-08 Transphorm, Inc. Semiconductor diodes with low reverse bias currents
US8716141B2 (en) 2011-03-04 2014-05-06 Transphorm Inc. Electrode configurations for semiconductor devices
US8901604B2 (en) 2011-09-06 2014-12-02 Transphorm Inc. Semiconductor devices with guard rings
US9257547B2 (en) 2011-09-13 2016-02-09 Transphorm Inc. III-N device structures having a non-insulating substrate
US8598937B2 (en) 2011-10-07 2013-12-03 Transphorm Inc. High power semiconductor electronic components with increased reliability
US9165766B2 (en) 2012-02-03 2015-10-20 Transphorm Inc. Buffer layer structures suited for III-nitride devices with foreign substrates
WO2013155108A1 (en) 2012-04-09 2013-10-17 Transphorm Inc. N-polar iii-nitride transistors
US9184275B2 (en) 2012-06-27 2015-11-10 Transphorm Inc. Semiconductor devices with integrated hole collectors
US8803246B2 (en) 2012-07-16 2014-08-12 Transphorm Inc. Semiconductor electronic components with integrated current limiters
US9048174B2 (en) * 2013-01-18 2015-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Compound semiconductor device having gallium nitride gate structures
JP6522521B2 (en) 2013-02-15 2019-05-29 トランスフォーム インコーポレーテッド Electrode of semiconductor device and method of manufacturing the same
US9087718B2 (en) 2013-03-13 2015-07-21 Transphorm Inc. Enhancement-mode III-nitride devices
US9245993B2 (en) 2013-03-15 2016-01-26 Transphorm Inc. Carbon doping semiconductor devices
US9443938B2 (en) 2013-07-19 2016-09-13 Transphorm Inc. III-nitride transistor including a p-type depleting layer
KR20150051822A (en) * 2013-11-05 2015-05-13 삼성전자주식회사 High electron mobility transistor and method of manufacturing the same
US9048303B1 (en) * 2014-01-30 2015-06-02 Infineon Technologies Austria Ag Group III-nitride-based enhancement mode transistor
US9337279B2 (en) 2014-03-03 2016-05-10 Infineon Technologies Austria Ag Group III-nitride-based enhancement mode transistor
US9318593B2 (en) 2014-07-21 2016-04-19 Transphorm Inc. Forming enhancement mode III-nitride devices
JP6395502B2 (en) * 2014-08-20 2018-09-26 ルネサスエレクトロニクス株式会社 Semiconductor device
US9536966B2 (en) 2014-12-16 2017-01-03 Transphorm Inc. Gate structures for III-N devices
US9536967B2 (en) 2014-12-16 2017-01-03 Transphorm Inc. Recessed ohmic contacts in a III-N device
JP6888013B2 (en) 2016-01-15 2021-06-16 トランスフォーム テクノロジー，インコーポレーテッド Enhancement Mode Group III Nitride Devices with AL (1-x) Si (x) O-Gate Insulators
WO2017210323A1 (en) 2016-05-31 2017-12-07 Transphorm Inc. Iii-nitride devices including a graded depleting layer
US10211328B2 (en) * 2016-09-20 2019-02-19 Board Of Trustees Of The University Of Illinois Normally-off cubic phase GaN (c-GaN) HEMT having a gate electrode dielectrically insulated from a c-AlGaN capping layer
US11522080B2 (en) * 2018-11-07 2022-12-06 Cornell University High-voltage p-channel FET based on III-nitride heterostructures
TWI685968B (en) 2018-11-23 2020-02-21 財團法人工業技術研究院 Enhancement mode gallium nitride based transistor device and manufacturing method thereof
CN111681958A (en) * 2020-05-29 2020-09-18 华南理工大学 A Novel Method for Fabricating Normally-Off HEMT Devices by Diffusion of Heterostructured Magnesium

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6140169A (en) * 1996-12-04 2000-10-31 Sony Corporation Method for manufacturing field effect transistor
US20020052076A1 (en) * 2000-09-27 2002-05-02 Khan Muhammad Asif Metal oxide semiconductor heterostructure field effect transistor
US6429467B1 (en) * 1999-01-29 2002-08-06 Nec Corporation Heterojunction field effect transistor

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6469357B1 (en) * 1994-03-23 2002-10-22 Agere Systems Guardian Corp. Article comprising an oxide layer on a GaAs or GaN-based semiconductor body
US6297538B1 (en) * 1998-03-23 2001-10-02 The University Of Delaware Metal-insulator-semiconductor field effect transistor having an oxidized aluminum nitride gate insulator formed on a gallium nitride or silicon substrate
US6107649A (en) * 1998-06-10 2000-08-22 Rutgers, The State University Field-controlled high-power semiconductor devices
US20010015437A1 (en) * 2000-01-25 2001-08-23 Hirotatsu Ishii GaN field-effect transistor, inverter device, and production processes therefor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6140169A (en) * 1996-12-04 2000-10-31 Sony Corporation Method for manufacturing field effect transistor
US6429467B1 (en) * 1999-01-29 2002-08-06 Nec Corporation Heterojunction field effect transistor
US20020052076A1 (en) * 2000-09-27 2002-05-02 Khan Muhammad Asif Metal oxide semiconductor heterostructure field effect transistor

Non-Patent Citations (10)

* Cited by examiner, † Cited by third party
Title
ASIF KHAN M ET AL: "ENHANCEMENT AND DEPLETION MODE GAN/ALGAN HETEROSTRUCTURE FIELD EFFECT TRANSISTORS", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 68, no. 4, 22 January 1996 (1996-01-22), pages 514 - 516, XP000556069, ISSN: 0003-6951 *
CHOU D-W ET AL: "ALGAN/GAN METAL OXIDE SEMICONDUCTOR HETEROSTRUCTURE FIELD-EFFECT TRANSISTOR BASED ON A LIQUID PHASE DEPOSITED OXIDE", JAPANESE JOURNAL OF APPLIED PHYSICS, PUBLICATION OFFICE JAPANESE JOURNAL OF APPLIED PHYSICS. TOKYO, JP, vol. 41, no. 7A, PART 2, 1 July 2002 (2002-07-01), pages L748 - L750, XP001163104, ISSN: 0021-4922 *
HU X ET AL: "SI3N4/ALGAN/GAN-METAL-INSULATOR-SEMICONDUCTOR HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 79, no. 17, 22 October 2001 (2001-10-22), pages 2832 - 2834, XP001103266, ISSN: 0003-6951 *
KIM J ET AL: "CHARACTERISTICS OF MGO/GAN GATE-CONTROLLED METAL-OXIDE-SEMICONDUCTOR DIODES", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 80, no. 24, 17 June 2002 (2002-06-17), pages 4555 - 4557, XP001126177, ISSN: 0003-6951 *
KIM J ET AL: "INVERSION BEHAVIOR IN SC2O3/GAN GATED DIODES", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 81, no. 2, 8 July 2002 (2002-07-08), pages 373 - 375, XP001129348, ISSN: 0003-6951 *
KOUDYMOV A ET AL: "MAXIMUM CURRENT IN NITRIDE-BASED HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 80, no. 17, 29 April 2002 (2002-04-29), pages 3216 - 3218, XP001122538, ISSN: 0003-6951 *
MISTELE D ET AL: "First AlGaN/GaN MOSFET with photoanodic gate dielectric", MATERIALS SCIENCE AND ENGINEERING B, ELSEVIER SEQUOIA, LAUSANNE, CH, vol. 93, no. 1-3, 30 May 2002 (2002-05-30), pages 107 - 111, XP004351258, ISSN: 0921-5107 *
SIMIN G ET AL: "7.5 kW/mm2current switch using AlGaN/GaN metal-oxide-semiconductor heterostructure field effect transistors on SiC substrates", ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 36, no. 24, 23 November 2000 (2000-11-23), pages 2043 - 2044, XP006015955, ISSN: 0013-5194 *
SIMIN G ET AL: "SIO2/ALGAN/INGAN/GAN MOSDHFETS", IEEE ELECTRON DEVICE LETTERS, IEEE INC. NEW YORK, US, vol. 23, no. 8, August 2002 (2002-08-01), pages 458 - 460, XP001124167, ISSN: 0741-3106 *
TELES L K ET AL: "SPINODAL DECOMPOSITION IN BXGA1-XN AND BXAL1-XN ALLOYS", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 80, no. 7, 18 February 2002 (2002-02-18), pages 1177 - 1179, XP001101688, ISSN: 0003-6951 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107623032A (en) * 2017-10-24 2018-01-23 电子科技大学 A Novel GaN Heterojunction Field Effect Transistor

Also Published As

Publication number Publication date
AU2003265691A1 (en) 2004-03-11
US20040041169A1 (en) 2004-03-04
US6914273B2 (en) 2005-07-05

Similar Documents

Publication Publication Date Title
US6914273B2 (en) GaN-type enhancement MOSFET using hetero structure
JP7411790B2 (en) Gallium nitride device and its driving circuit
US8669591B2 (en) E-mode HFET device
US8076698B2 (en) Transistor and method for operating the same
US8779438B2 (en) Field-effect transistor with nitride semiconductor and method for fabricating the same
US8390029B2 (en) Semiconductor device for reducing and/or preventing current collapse
US7683399B2 (en) Transistor
CN103026491B (en) Normally-off Group III Nitride Metal-Two-Dimensional Electron Gas Tunneling Junction Field Effect Transistor
Saito et al. Recessed-gate structure approach toward normally off high-voltage AlGaN/GaN HEMT for power electronics applications
US9343562B2 (en) Dual-gated group III-V merged transistor
JP2025504928A (en) N-polar device including a depletion layer with improved conductivity - Patents.com
US9275998B2 (en) Inverted P-channel III-nitride field effect tansistor with Hole Carriers in the channel
Saito et al. Design optimization of high breakdown voltage AlGaN-GaN power HEMT on an insulating substrate for R/sub ON/AV/sub B/tradeoff characteristics
EP2629334B1 (en) Power transistor having segmented gate
US20120292665A1 (en) High performance multigate transistor
US20130032860A1 (en) HFET with low access resistance
US10636899B2 (en) High electron mobility transistor with graded back-barrier region
Kambayashi et al. Normally off n-channel GaN MOSFETs on Si substrates using an SAG technique and ion implantation
CN101273458A (en) Enhancement Mode Group III Nitride Field Effect Transistor
Zheng et al. Enhancement-mode GaN p-channel MOSFETs for power integration
EP0334006A1 (en) Stacked channel heterojunction fet
US9437724B2 (en) Semiconductor device and method of manufacturing the semiconductor device
JP2007201093A (en) Nitride semiconductor device
US20240234560A9 (en) Back-barrier for gallium nitride based high electron mobility transistors

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP