WO2004017143A3 - Verfahren zum bestrahlen eines resists - Google Patents

Verfahren zum bestrahlen eines resists Download PDF

Info

Publication number
WO2004017143A3
WO2004017143A3 PCT/DE2003/002351 DE0302351W WO2004017143A3 WO 2004017143 A3 WO2004017143 A3 WO 2004017143A3 DE 0302351 W DE0302351 W DE 0302351W WO 2004017143 A3 WO2004017143 A3 WO 2004017143A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
lacquer
production
resist
structured
Prior art date
Application number
PCT/DE2003/002351
Other languages
English (en)
French (fr)
Other versions
WO2004017143A2 (de
Inventor
Klaus Goller
Roland Haberkern
Original Assignee
Infineon Technologies Ag
Klaus Goller
Roland Haberkern
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Klaus Goller, Roland Haberkern filed Critical Infineon Technologies Ag
Publication of WO2004017143A2 publication Critical patent/WO2004017143A2/de
Publication of WO2004017143A3 publication Critical patent/WO2004017143A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G03F7/203—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/095—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

Die Erfindung betrifft ein Verfahren, bei dem nach der Herstellung einer zustrukturierenden Schicht (12) eine strahlungsempfindliche Resistschichtanordnung(10) erzeugt und vertikal selektiv strukturiert wird. Die Resistschichtanordnung enthält beispielsweise eine untere Lackschicht (14) und eine obere Lackschicht (18). Durch das Verfahren lassen sich Verfahrensschritte bei der Herstellung einer integrierten Schaltungsanordnung einsparen.
PCT/DE2003/002351 2002-07-22 2003-07-11 Verfahren zum bestrahlen eines resists WO2004017143A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10233209.6 2002-07-22
DE2002133209 DE10233209A1 (de) 2002-07-22 2002-07-22 Verfahren zum Bestrahlen eines Resists

Publications (2)

Publication Number Publication Date
WO2004017143A2 WO2004017143A2 (de) 2004-02-26
WO2004017143A3 true WO2004017143A3 (de) 2004-07-15

Family

ID=30010288

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/002351 WO2004017143A2 (de) 2002-07-22 2003-07-11 Verfahren zum bestrahlen eines resists

Country Status (3)

Country Link
DE (1) DE10233209A1 (de)
TW (1) TW200401947A (de)
WO (1) WO2004017143A2 (de)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02302037A (ja) * 1989-05-16 1990-12-14 Mitsubishi Electric Corp 微細パターンの形成方法
EP0489426A2 (de) * 1990-12-06 1992-06-10 Sony Corporation Verfahren zur Projektionsbelichtung
US6007324A (en) * 1977-10-23 1999-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Double layer method for fabricating a rim type attenuating phase shifting mask
US6043164A (en) * 1996-06-10 2000-03-28 Sharp Laboratories Of America, Inc. Method for transferring a multi-level photoresist pattern
US6180512B1 (en) * 1997-10-14 2001-01-30 Industrial Technology Research Institute Single-mask dual damascene processes by using phase-shifting mask
US6242344B1 (en) * 2000-02-07 2001-06-05 Institute Of Microelectronics Tri-layer resist method for dual damascene process
US20010036743A1 (en) * 1999-09-02 2001-11-01 Micron Technology, Inc. Mask for producing rectangular openings in a substrate
WO2002029887A2 (en) * 2000-09-29 2002-04-11 Infineon Technologies North America Corp. One-step etch processes for dual damascene metallization
US6428938B1 (en) * 2000-06-19 2002-08-06 Taiwan Semiconductor Manufacturing Company Phase-shift mask for printing high-resolution images and a method of fabrication

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5595324A (en) * 1978-12-30 1980-07-19 Fujitsu Ltd Manufacturing method of semiconductor device
JPH028852A (ja) * 1988-06-28 1990-01-12 Fujitsu Ltd パターニング方法
KR930008139B1 (en) * 1990-08-30 1993-08-26 Samsung Electronics Co Ltd Method for preparation of pattern
EP1083463A3 (de) * 1999-09-10 2003-11-19 Lucent Technologies Inc. Mustererzeugungsverfahren und Halbleitervorrichtung

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6007324A (en) * 1977-10-23 1999-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Double layer method for fabricating a rim type attenuating phase shifting mask
JPH02302037A (ja) * 1989-05-16 1990-12-14 Mitsubishi Electric Corp 微細パターンの形成方法
EP0489426A2 (de) * 1990-12-06 1992-06-10 Sony Corporation Verfahren zur Projektionsbelichtung
US6043164A (en) * 1996-06-10 2000-03-28 Sharp Laboratories Of America, Inc. Method for transferring a multi-level photoresist pattern
US6180512B1 (en) * 1997-10-14 2001-01-30 Industrial Technology Research Institute Single-mask dual damascene processes by using phase-shifting mask
US20010036743A1 (en) * 1999-09-02 2001-11-01 Micron Technology, Inc. Mask for producing rectangular openings in a substrate
US6242344B1 (en) * 2000-02-07 2001-06-05 Institute Of Microelectronics Tri-layer resist method for dual damascene process
US6428938B1 (en) * 2000-06-19 2002-08-06 Taiwan Semiconductor Manufacturing Company Phase-shift mask for printing high-resolution images and a method of fabrication
WO2002029887A2 (en) * 2000-09-29 2002-04-11 Infineon Technologies North America Corp. One-step etch processes for dual damascene metallization

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 015, no. 086 (E - 1039) 28 February 1991 (1991-02-28) *

Also Published As

Publication number Publication date
TW200401947A (en) 2004-02-01
WO2004017143A2 (de) 2004-02-26
DE10233209A1 (de) 2004-02-05

Similar Documents

Publication Publication Date Title
WO2005039868A3 (de) Strukturierung von elektrischen funktionsschichten mittels einer transferfolie und strukturierung des klebers
EP1107307A4 (de) Halbleitergehäuse, halbleitervorrichtung, elektronikelement und herstellung eines halbleitergehäuses
WO2003088101A3 (en) Method and apparatus for automatic layout of circuit structures
WO2006084686A3 (de) Mehrschichtkörper mit diffraktiver reliefstruktur und herstellverfahren
WO2002073325A3 (en) A method and apparatus for producing a prototype
IN2004DE03899A (en) A method for the start-up of an epoxidation process and a process for the epoxidation of an olefin
SG98450A1 (en) High performance system-on-chip using post passivation process
WO1999042930A3 (en) Method and apparatus for logic synthesis
ATE549795T1 (de) Oberflächenwellen-bauelement und verfahren zu seiner herstellung
WO2002075794A3 (en) A method for making a micromechanical device by using a sacrificial substrate
TW200711982A (en) Method for manufacturing a component having a three-dimensional structure in a surface region and a ceramic component
WO2004108436A3 (en) Floor panel and method for manufacturing such floor panel
DE60238548D1 (de) Verfahren zur herstellung dünner schichten, die mikrokomponenten enthalten
WO2002080239A3 (en) Process for forming sub-lithographic photoresist features
WO2008150930A3 (en) Masking high-aspect ratio structures
WO2004059539A3 (en) A method for accounting for process variation in the design of integrated circuits
EP1653789A4 (de) Leiterplatte und herstellungsverfahren dafür
WO2004047144A3 (de) Organisches elektronisches bauelement mit stukturierter halbleitender funktionsschicht und herstellungsverfahren dazu
TW200621102A (en) Capacitor device and method of manufacturing the same
ATE252225T1 (de) Verfahren zum erzeugen eines mikro- elektromechanischen elements
EP1369913A3 (de) Verfahren zur Strukturierung von dielektrischen Zwischenmetall-Schichten
WO2002006038A3 (en) Method of manufacturing a replica as well as a replica obtained by carrying out a uv light-initiated cationic polymerization
WO2004025739A3 (de) Verfahren zum herstellen einer integrierten pin-diode und zugehörige schaltungsanordnung
TW200518183A (en) Method for combining via patterns into a single mask
WO2004050294A3 (de) Verfahren zur herstellung eines bauteils

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): CN SG US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase