WO2004006617A1 - Paquet electro-optique hybride et commutateur de cellule - Google Patents

Paquet electro-optique hybride et commutateur de cellule Download PDF

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Publication number
WO2004006617A1
WO2004006617A1 PCT/GB2003/002783 GB0302783W WO2004006617A1 WO 2004006617 A1 WO2004006617 A1 WO 2004006617A1 GB 0302783 W GB0302783 W GB 0302783W WO 2004006617 A1 WO2004006617 A1 WO 2004006617A1
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WO
WIPO (PCT)
Prior art keywords
packet
optical
output
input
plural
Prior art date
Application number
PCT/GB2003/002783
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English (en)
Inventor
Robert Walter Alister Scarr
Original Assignee
Cambridge University Technical Services Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cambridge University Technical Services Limited filed Critical Cambridge University Technical Services Limited
Priority to AU2003246922A priority Critical patent/AU2003246922A1/en
Publication of WO2004006617A1 publication Critical patent/WO2004006617A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0062—Network aspects
    • H04Q11/0066—Provisions for optical burst or packet networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0007—Construction
    • H04Q2011/0026—Construction using free space propagation (e.g. lenses, mirrors)
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0037—Operation
    • H04Q2011/0039—Electrical control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0037—Operation
    • H04Q2011/0043—Fault tolerance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0037—Operation
    • H04Q2011/0049—Crosstalk reduction; Noise; Power budget

Definitions

  • the present invention relates to a packet router switch, a packet switch and to a method of switching packets.
  • packets for example IP packets and ATM cells.
  • packet includes ATM cells unless the context indicates the contrary.
  • optical means for routers have been proposed in which electronic input and output modules are connected by optical means. Examples of the optical means that have been included in these designs are free-space optical paths and guided paths such as optical fibres. Some of the designs involve discrete path selection devices forming an intermediate stage and some of the designs have path selection at the input or output modules.
  • воду access contention can be addressed by providing a separate memory for each input stream, but this is prohibitively complex, large and expensive.
  • An alternative is to divide the input streams into groups, and provide a memory per group. This technique is called hereinafter “sectorisation” and each device having a group of inputs and a single memory is termed hereinafter a “sector”.
  • a packet router switch having plural first packet routing devices and plural second packet routing devices, each packet routing device having plural input ports and plural output ports, wherein the total number of output ports of said first packet routing devices is equal to the total number of input ports of said second packet routing devices, each packet routing device being operable to route packets incident at a respective input port to an output port determined by packet header information, the switch having optical components in use providing plural free- space optical paths connecting output ports of the first packet routing devices to input ports of the second packet routing devices.
  • the number of said first packet routing devices is equal to the number of second packet routing devices, and each first packet routing device has a like number of output ports equal in number to the like number of input ports of each second packet routing device.
  • Embodiments of the invention are able to route packets from any of input to any output using a multistage switching process.
  • a shutter device for selectively enabling or disabling said plural optical paths.
  • This arrangement may provide flexible interconnectivity, for instance to take into account changing traffic patterns over the course of a day.
  • the shutter device may comprise a controllable liquid crystal device.
  • the switch may have fan-out optical components in use replicating optical outputs from at least some of said output ports to provide plural instances of said outputs at different spatial locations, and a device for passing selected ones of said instances to the optical inputs of said second packet routing devices.
  • the device may be a controllable shutter thereby providing flexible interconnections. It may alternatively or additionally include a fixed mask.
  • the optical transpose achieved by the path-producing components is realised by lenses: in a second embodiment holographic gratings are used and in a third embodiment both lenses and gratings are used.
  • the gratings may be provided by a controllable spatial light modulator.
  • a method of switching packets using a packet switch having plural input ports and plural output ports comprising an input stage and an output stage, the input stage having N optical outputs, the output stage comprising plural sectors, wherein each sector has a respective one of said output ports and each sector receives packets from all said N optical outputs at its inputs, wherein each said sector has N input shift registers, each input shift register receiving a respective one of said packets at its serial input and having plural parallel taps, each sector having N/j stores where j and N/j are both integers; the method comprising assigning packets from each optical output to a respective time slot from N*h time slots (h>l); supplying each of said N/j stores with packet data from the taps of j shift registers; and selecting between said packets at each sector in accordance with packet header information.
  • the write time decreases to speed up the device; the increase in speed may be used to prevent or reduce knockout.
  • packet switch having an input stage having plural input ports and an output stage having plural output ports, the input stage having plural optical outputs for conveying packets via free-space paths to optical inputs of said output stage, the packet switch further comprising: an optical control device for selectively enabling and disabling said free- space optical paths between the optical inputs and outputs in response to packet header information; a store in use holding respective stored representations of the state of the optical control device for each of plural route settings, the store having an address signal input connected to an output of said input stage for causing read out of a said stored representation at a store output; and a controller connected to receive said store output for setting a state of the optical control device in accordance with a desired route setting, whereby the switch is operable to route packets at a respective input to an output port in dependence on the packet header information.
  • the use of a stored mapping accessible by the input stage of the route setting to the state of the optical shutter enables minimum setting times of the shutters.
  • the controller may contains a memory for holding a map of the current state of the optical control device.
  • the additional provision of a memory in the controller allows the data transferred from the store to be reduced, as for example only changes in state need be transferred.
  • the switch may have an optical control link whereby said controller receives said store output.
  • the optical control link may be one of the free-space paths.
  • an electrical control link may be provided so that the controller receives said store output.
  • a sensing means may be provided to determine the actual state of the optical control device and a signal path be provided for comparison with the stored representation.
  • Figure 1 shows a partial block schematic diagram of an first exemplary routing switch having three stages
  • Figure 2 shows an example of an arrangement of optical components providing fan-out in free-space
  • Figure 3 shows a partial block schematic diagram of a second exemplary routing switch having two stages
  • Figure 4 shows an embodiment of a packet multistage switch embodying the present invention
  • Figure 5 shows a partial schematic diagram of a packet switch embodying the second aspect of the invention.
  • Figure 6 shows a partial schematic diagram of a packet switch embodying the third aspect of the invention.
  • a three stage switch 10 has three input electronic modules 11, 12, 13 each with a respective pair of inputs 14,15; 16,17; 18,19, an optical shutter device 47 having three optical shutter sections 20,21,22 and three output modules 23,24, 25 each with a respective pair of output connection 26,27; 28,29; 30,31.
  • the input electronic modules 11,12,13 each have an associated VCSEL output stage 1 la, 12a, 13a, and the output electronic modules 23,24,25 each have an associated opto-electronic input stage 24a,25a,26a.
  • the VCSEL stages 11 a, 12a, 13a of the input electronic modules 11,12,13 each provide three optical outputs 41a-c; 42a-c; 43a-c.
  • the input optoelectronic stages 24a,25a,26a of the output electronic modules each have respectively three inputs, 44a-c; 45a-c; 46a-c.
  • optical shutter sections 20,21,22 are intermediate the input and output modules 11, 12,13;23,24,25.
  • Fan-out optics connect the outputs 41a-c; 42a-c; 43a-c of the input electronic modules 11-13 to the shutter sections 20-22.
  • the fan-out optics in this embodiment consists of lenses and holographic gratings providing free-space transmission, but in other embodiments lenses alone and holographic gratings alone are used.
  • An example of fan-out optics is described later herein with reference to Figure 2.
  • the fan-out optics are selected so that the outputs of each input electronic module 11,12,13 are replicated at each of the optical shutter sections 20-22 so that each optical shutter section 20,21,22 receives the three outputs of each of the three input electronic modules 11, 12 and 13.
  • the outputs of the shutter sections 20-22 have fan-in optics which connect the outputs of the shutter sections to the three inputs 44a-c; 45a-c; 46a-c of the output electronic modules 23-5.
  • the output electronic modules respond to sensed header information of packets at their three inputs to route to the correct output.
  • Control circuitry (not shown) is provided for controlling the input electronic modules 11,12,13 and for operating the optical shutter sections 20,21,22 in accordance with header information of packets to be transmitted through the switch and in accordance with the current state of the switch.
  • the control circuitry operates the shutter sections 20-22 so that no more than three shutters of each module can be open at any one time.
  • the presence of nine inputs at each optical shutter section gives rise at most three selected paths being enabled by each shutter section.
  • the control circuitry receives this data, and causes input electronic module 11 to apply the packet to a selected one of its outputs 41a,41b,41c choosing one of those outputs not already in use for conveying packets, provided shutter section 21 is capable of connecting to output electronic module 24. If shutter section 21 is already committed to enabling three paths, or if the only paths between the output of the input module and the input to the output electronic module are blocked by other inputs to the output electronic module 24, the control circuitry causes input electronic module 11 to queue the packet. This assumes path rearrangement is not an option. Again queuing can occur provided there is space for queuing; if not the packet is dropped.
  • the packet of concern is output at VCSEL 41b.
  • This output is, by virtue of the fan-out optics, replicated three times, once at each of the shutter sections 20-22.
  • the control circuitry in this case only enables the relevant shutter in module 21 so that the packet is optically passed through the shutter to reach input 45b of output electronic module 24.
  • the module 24 After conversion to electrical signal, the module 24 checks the header of the packet at input 45b, and outputs the packet to output 28 or 29 unless that output is already occupied with transmitting a packet from another input. In that case, the packet is queued until the output is free. If the queue overflows, the packet is dropped.
  • Figure 2 shows diagrammatically the optical layout for a 4 by 4 sectorised switch 101.
  • a set of four VCSEL arrays 1-4 outputs light which is collimated by respective lenses lOla-d, and the resulting parallel beams applied to a holographic fan-out grating 102.
  • the output of the fan-out grating is fed to further lenses 103 a- d to provide fanned-out beams replicating the VCSEL array outputs four times on a liquid crystal shutter matrix 104.
  • the arrangement of the two lens planes and the grating is a 4f arrangement.
  • a third 105 and fourth 106 lens arrangement fans-in the light from the shutter to a detector array 107.
  • the switch 130 has an input electronic module 131 having four multi-path inputs 132 - 135 and providing four multi-path optical outputs 136 - 139 from four VCSEL units.
  • the switch 130 further has four output electronic module sectors 141 - 144 each having a respective electrical multi-path output 145 - 148.
  • Each output electronic module sector has four multi-path optical inputs 141 a-d; 142a-d; 143a-d; 144a-d.
  • Each input has a respective optoelectronic element so that the modules 141-4 operate electronically.
  • the fan-out optics serves to provide one replica of each of the multi-path outputs 136 - 139 at the respective input points a - d of each of the output electronic modules 141 - 144.
  • the output electronic modules respond to the header information of the packets received so as to accept only packets having a specific header or header range. For example, if the sector size were three, the output electronic module sector 141 has two outputs 145a, 145b, and the module accepts packets with headers for the two outputs 145 a, 145b and then distributes them accordingly.
  • the three most common cross-office path allocation algorithms for a telecommunication switch have paths allocated randomly, pseudo-randomly or sequentially. However it has been established by simulation that an algorithm in which a number of paths are pre-assigned with the remainder selectable is more effective in that the control circuit overhead is much reduced compared with the sequential or random algorithms.
  • the paths are selected by an array of electrically controlled optical shutters, for example liquid crystal over silicon (LCOS).
  • LCOS liquid crystal over silicon
  • the shutters 20-2 are replaced by a fixed mask thus reducing the cost of the shutter array. The reliability is also improved.
  • the fixed mask part and selectable shutter part may each be arranged in a respective group.
  • the selectable shutters switch in a time comparable with the duration of transmission of one packet or cell, typically a time of the microsecond or sub- microsecond order.
  • Figure 4 shows how routing switches and specifically but not exclusively, routing switches having either of the architectures described in Figures 1 and 3 can be interconnected to form a two stage large switching complex.
  • FIG 4 there are two switch stages SI 1-S1N; S21-S2N, each with N switches.
  • Each switch has n input and output ports.
  • one interconnection rule known as an orthogonal transform, is that the ith port on the jth switch of stage 1 is connected to the jth port of the ith switch of stage 2.
  • N*n connecting links is given by:
  • the number of links N*n is very large, e.g. 65,000.
  • N*n is large, there are advantages in implementing this interconnection using free-space optical paths.
  • Optical paths in themselves provide lower crosstalk and higher speed than electrical paths, but the use of fibres entails a complex structure which is difficult and expensive to make and install, and difficult to maintain.
  • An alternative method is to use the equivalent of the intermediate optical shutter stage of switch 10 of Figure 1 with all fixed connections.
  • a number m (m ⁇ n) of the outputs from each of the N switches of the first stage is connected to m inputs of the second stage using a partially equipped fixed connection being a transpose of size N*m.
  • one or more small cache memories are provided between the array of shift registers and the main queue store of each output electronics module sector.
  • the main queue store can then run at a relatively reduced rate, say P/k writes/cycle (k>l) rather than P writes/cycle, where P is the total number of input ports on the switch. Assuming that buffering rather than queuing takes place in these cache memories, the peak arrival rate could exceed the P/k value rather than P and packet discard would then take place with a lower probability.
  • a third device incorporates features from the first and second devices.
  • each of the N optical inputs 200 are fed to respective optoelectronic converters 201, and each serial output converted to parallel via a respective shift register 202.
  • the number of inputs is divided into three sets a,b,c.
  • the shift registers 202a of the first set write to a first store 203a, those of the second set 202b write to a second store 203b and those of the third store 202c write to a third store 203c.
  • Read-out is via a common bus to the main readout/queue memory 204.
  • the three stores 202a-202c act as intermediate buffers with the main store 204 remaining as a common item. In another embodiment the three stores replace the single store of the prior art. The stores 202a-202c are large enough to hold information while waiting to be written to the main store.
  • a memory 71 is provided for holding respective stored representations of the state of the shutter that correspond to the available route settings.
  • the memory 70 has an address signal input 72 connected to an output from a switch input stage 73 for causing read out of a said stored representation at a store output 74.
  • a controller 75 is connected to receive the store output for setting a state of the shutters to achieve a desired route setting.
  • the representation are a map on memory of the state of the shutters (or equivalent) to record the cross-office path settings. Where the input stage 73 is sectorised, this map in memory is directly accessible by all the sectors of the input stage. The input stage sends messages to the shutter plane to set and reset the shutters.
  • the messages are sent by an assigned optical link 76 out of the set of links from the input stage 73, and via fan-out optics 78.
  • Information is derived from that link by a shutter controller 79 after conversion to an electrical signal using an optical receiver 77.
  • a separate set of data links is provided between the input stage and the shutter controller.
  • the shutter controller 79 contains a local map of the current shutter state. This enables the data carried by the optical link 76 to be reduced as it only needs to carry changes to the current shutter state, rather than rewriting the data completely.
  • the actual state of the shutters is sensed and fed back to the input stage for diagnostic and maintenance purposes via a feedback electrical link 80.
  • the input stage 73 contains circuitry which then compares the actual state with the desired state, and sets an error flag if agreement does not occur. This is used to prevent use of a route having an error due to a faulty shutter. Redundancy can be provided so that operation may continue.
  • Shutter state sensing may be performed in a number of ways. These include checking the electrical conditions of the shutter control circuitry -typically the shutter is part of a bistable circuit and voltage measurement of that circuit will reveal whether the shutter is in one state or the other, by measuring the transmitted light during a separate set up phase or by measuring back reflected light in a separate measuring device.

Abstract

Un commutateur achemineur de paquets possède une pluralité de premiers dispositifs d'acheminement de paquets et une pluralité de seconds dispositifs d'acheminement de paquets, chaque dispositif d'acheminement de paquets présentant plusieurs ports d'entrée et de sortie. Le nombre total de ports de sortie desdits premiers dispositifs d'acheminement de paquets est égal au nombre total de ports d'entrée desdits seconds dispositifs d'acheminement de paquets. Chaque dispositif d'acheminement de paquets sert à acheminer les paquets incidents au niveau d'un port d'entrée respectif vers un port de sortie déterminé par des informations d'en-tête de paquets. Le commutateur possède des composants optiques qui fournissent plusieurs trajets optiques en espace libre qui connectent les ports de sortie des premiers dispositifs d'acheminement de paquets aux ports d'entrée des seconds dispositifs d'acheminement de paquets.
PCT/GB2003/002783 2002-07-04 2003-06-30 Paquet electro-optique hybride et commutateur de cellule WO2004006617A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003246922A AU2003246922A1 (en) 2002-07-04 2003-06-30 Hybrid electro-optic packet and cell switch

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0215504.2A GB0215504D0 (en) 2002-07-04 2002-07-04 Hybrid electro-optic packet and cell switch
GB0215504.2 2002-07-04

Publications (1)

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WO2004006617A1 true WO2004006617A1 (fr) 2004-01-15

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0590865A2 (fr) * 1992-09-30 1994-04-06 AT&T Corp. Agencement extensible de commutation optique de paquets à plusieurs étages avec commutateur de dérivation
EP0760589A2 (fr) * 1995-08-31 1997-03-05 AT&T Corp. Commutateur de paquets opérant à un terabit par seconde à plusieurs probabilités attribuables de perte de paquets
EP0811862A2 (fr) * 1996-06-03 1997-12-10 Nippon Telegraph And Telephone Corporation Système d'interconnection optique carte-à-carte et unité-à-unité
US5870216A (en) * 1995-10-26 1999-02-09 Trw Inc. Splitterless optical broadcast switch
WO2001093625A2 (fr) * 2000-06-02 2001-12-06 Calient Networks, Inc. Brasseur optique a point de prelevement de signaux optiques

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0590865A2 (fr) * 1992-09-30 1994-04-06 AT&T Corp. Agencement extensible de commutation optique de paquets à plusieurs étages avec commutateur de dérivation
EP0760589A2 (fr) * 1995-08-31 1997-03-05 AT&T Corp. Commutateur de paquets opérant à un terabit par seconde à plusieurs probabilités attribuables de perte de paquets
US5870216A (en) * 1995-10-26 1999-02-09 Trw Inc. Splitterless optical broadcast switch
EP0811862A2 (fr) * 1996-06-03 1997-12-10 Nippon Telegraph And Telephone Corporation Système d'interconnection optique carte-à-carte et unité-à-unité
WO2001093625A2 (fr) * 2000-06-02 2001-12-06 Calient Networks, Inc. Brasseur optique a point de prelevement de signaux optiques

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Publication number Publication date
GB0215504D0 (en) 2002-08-14
AU2003246922A1 (en) 2004-01-23

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