WO2002093843A1 - Systeme de routage - Google Patents

Systeme de routage Download PDF

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Publication number
WO2002093843A1
WO2002093843A1 PCT/GB2001/002155 GB0102155W WO02093843A1 WO 2002093843 A1 WO2002093843 A1 WO 2002093843A1 GB 0102155 W GB0102155 W GB 0102155W WO 02093843 A1 WO02093843 A1 WO 02093843A1
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WO
WIPO (PCT)
Prior art keywords
output
sub
packet
packets
input
Prior art date
Application number
PCT/GB2001/002155
Other languages
English (en)
Inventor
Robert Walter Alister Scarr
Trevor James Hall
Martin H. George
Timothy David Wilkinson
Michael Anthony Hands
Richard Hoptroff
William Arden Crossland
Original Assignee
Opera Systems Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Opera Systems Limited filed Critical Opera Systems Limited
Priority to PCT/GB2001/002155 priority Critical patent/WO2002093843A1/fr
Publication of WO2002093843A1 publication Critical patent/WO2002093843A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H04L49/309—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3009—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0007—Construction
    • H04Q2011/0015—Construction using splitting combining
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0007—Construction
    • H04Q2011/0026—Construction using free space propagation (e.g. lenses, mirrors)

Definitions

  • This invention is concerned with routers, especially those for use in digital communication networks.
  • Digital communication networks for example the Internet, consist of a many data channels interconnected by "routers". These routers route incoming data packets to their destination according to the "address header" attached to the data packet. Routing many packets between a large number of channels at high speed is difficult and expensive.
  • This invention relates to a design for a packet router and in particular the "core switch” part of the router (see Figure 1) that enables higher throughput of data at lower cost than with existing technology. Moreover, the invention allows the core switches as described here to be interconnected to produce larger size routers.
  • the need for faster routers has been tackled by purely electronic means.
  • this makes the router difficult to scale, since the connection of N inputs to N possible outputs requires an N 2 matrix of cross-points or cross-connections which, because of unwanted coupling between unconnected points (i.e. crosstalk), becomes more difficult to achieve as N increases.
  • the invention deals with the problem in quite a different way by making use of the fact that there is no cross coupling between light beams in free space or any other suitable optical medium. More specifically, the router's required ability to cross- connect is achieved by converting the N electrical signals to light signals. These light signals are divided into F groups, called "sectors" and fanned-out F times.
  • the N outputs from each set of F sectors is transmitted, optically to F receiving sectors each of which contains N detectors and hence may receive the totality of the input information.
  • This information which is transmitted serially is in the form of packets and these packets are phased so that only the start of one of the N possible packets is received by the appropriate detector at any one time.
  • Circuitry associated with each detector reads the header and retains or discards the packet according to whether its address corresponds to the address of the receiving sector. The phasing of the packets ensures that the electrical processing that takes place on their receipt is more evenly spaced in time than would be in the case if their starts were sent simultaneously or at random.
  • the retained packets are then stored and sent through to the output channel to which it is addressed when that channel becomes free.
  • a method of routing data in a packetised form between a plurality of incoming links and a plurality of outgoing links including the conversion of the address data in the packet headers into a reduced form suited to the fast connection of packets by a core switch.
  • all incoming data is available for a selected output link and including the segmentation of packets into sub-packets of a length suited to the fast transfer of packets by the core switch.
  • the core switch includes means to phase the packets such that the start of a sub-packet is allocated a specific time slot in a multiplex and the reduced form of address is added to the sub-packet to facilitate its routing through the core switch.
  • the optical transfer of the sub-packet is in serial form to optical detectors coupled to an electronic output unit.
  • the electronic output unit contains means for converting the sub-packets from serial form to parallel form and transferring them to a memory store.
  • the sub-packets are held in the memory store until the outgoing link for which they are destined is free of traffic. When this is so, the memory store is read out and the sub-packets are transformed back to serial form. The reduced header is removed and complete packets are reassembled before transmission on an outgoing link.
  • an apparatus in which there are N replications of the electronic output units each unit being called a sector and providing output to only l/F th of the output links.
  • Optical transfer means are provided by an F- fold replication of the complete input data to each of the F sectors, each off which said sectors ignores the data not wanted by it .
  • an apparatus in which there are F replications or sectors of an electronic input unit and F replications or sectors of an electronic output unit, each input and output unit being divided into F sub-sectors with optical or electrical means for orthogonally connecting sub-sectors of input units to sub-sectors of output units, such that a sub-sector of an input unit with coordinates a,b is connected to an output unit sub-sector b,a wherein the first coordinate refers to the sector and the second to the sub-sector.
  • a packet router in which a multiplicity of core switches are interconnected as modules to make a larger router, means for carrying the reduced form of addressing and sub-packeting over several apparatus as in claims 1,2 and 3 in cascade.
  • Figure 1 shows a packet router of the invention
  • Figure 2 shows a block schematic of the fan-out version of the core switch of the router of Figure 1;
  • FIG. 3 shows a block schematic of the sectorised orthogonal transfer (SOT) version of the router of Figure
  • FIG 4 shows the principle of the use of straight optical fan-out (SOFO) with electrical fan-in;
  • FIG. 5 shows the principle of the use of the alternative sectorised orthogonal transfer (SOT) ;
  • Figure 6 shows a phasing diagram for serial packet transmission through a cross connect
  • Figure 7 shows a schematic view of optical fan-out, with multiple image function
  • Figure 8 fan-out and multiple imaging using a diffraction grating
  • Figure 9 shows optical fan-out based on a Fresnel hologram
  • Figure 10 shows optical fan-out effected using a beam- splitter
  • Figure 11 shows a functional block diagram of the output electronics
  • Figure 12 shows a schematic of per sector electrical fan-in circuitry.
  • Figure 1 shows a block schematic of the module design. It consists of an input packer handler, a core switch and output packet handler.
  • the input packet handler performs two main functions:
  • PS octets
  • the switch is based on a "broadcast” or “the generalised knockout principle” (see M.J Carol & M.G. Hluchy. "The knockout switch principles and performance.” Proc. 12th Conference on Local computing networks, October 1987. pp 16-22).
  • Figure 2 shows one of the embodiments based on straight optical fan-out (SOFO) and
  • Figure 3 shows the other based on sectorised orthogonal transfer (SOT) .
  • SOFO straight optical fan-out
  • SOT sectorised orthogonal transfer
  • Figure 4 The principle of Figure 2 is amplified in Figure 4 for a particular example of 64 inputs and an optical fan-out of 4.
  • the inputs are copied F times to F output sectors.
  • F is the fan-out which is best achieved optically avoiding the cross coupling problems associated with an all electronic solution.
  • Each of the F sectors receives the complete set of input packets but ignores/discards those not intended for it .
  • Those that are wanted are written to a per sector store which stores packet segments and is organised to act as a queue that holds those packet segments until their destination ports are free.
  • N 64 ( Figure 4)
  • a fan-out of 4 with 4 sectors each having 16 output ports, the electronics are then performing a fan-in of 64 to 16, i.e. a fan-in of 4.
  • SOT sectorised orthogonal transfer
  • Figure 3 Figure 3 and as amplified in Figure 5, the input is first divided into sectors and then sub-sectors.
  • the input for one sector is broadcast to all sub-sectors but is only selected by a given sub-sector if that sub-sector is "opposite" the relevant output sub-sector.
  • Sub-sectors are arranged in an orthogonal array and there is a direct optical connection, or flip-chip bonding, between sub-sectors on the input and output planes with common storage per sector on the output plane.
  • SOT needs less inter-plane connections than SOFO but is more sensitive to traffic patterns and hence may lose more packets.
  • the concept of orthogonal transfer as described here has been shown in previous embodiments although not perhaps recognized as such. In US Patent No.
  • Each of the N incoming packets is allocated a time slot modulo N and of duration ti - this is done to avoid store contention problems on fan-in.
  • Many packets are transferred in parallel but for a specific incoming packet transfer is only allowed to start transfer when its time slot occurs.
  • the input packet assembly buffers must be at least N bits per packet to achieve the desired phasing (see Figure
  • OH represents the local addressing over head plus stuffing bits.
  • T is called the "tranche size”.
  • the local address is added to the first of the sub-segments and one or more stuffing bits are added between each sub-segment. If a packet is present on a given input, its first sub-segment will start transmission in its time slot in serial form from the optical transmitter to the input detectors of the fan-in block.
  • Optical Input Plane contains point sources organised as a one or two dimensional array and could be either;
  • a number of spatially distributed optical emitters, which could be organised is a one or two dimensional array.
  • the SOFO design fits into the optical fan-out section of the core switch ( Figure 2) and requires that the array of point sources in the (OIP) are copied to multiple copies of the array displaced spatially and non-overlapping at the Optical Receiver Plane (ORP) , as labelled in Figure 8.
  • the construction of each copied array may be magnified positively or negatively in comparison to the OIP in order that the size of the point sources matches the size of the individual detectors in the ORP. It is possible that the copied images may be copied without maintaining the same orientation as the process of fan-out may cause each copy to be "flipped" round its local axis. This would result in points PI..4 being ordered as P4..1, etc.
  • the optical design of the waveguide based optical fan- out system would require additional optics in order to control the beam divergence and spot size of each of the point sources propagating from the OIP.
  • the optics could be as simple as a single microlens designed to couple the light from one point source into one waveguide input channel.
  • the waveguide would then confine the light to propagate along its channel and split according to the construction and placement of the waveguide splitter technology.
  • the diffractive/holographic component ( Figure 9)
  • This component is designed to control the splitting of the light into the multiple images and may require a lens to be used to image the multiple images to the ORP (as shown in Figure 9) .
  • the diffractive/holographic component may itself incorporate an imaging function and image the light to the ORP (as shown in Figure 10) .
  • each BS will split the light of the array into two identical arrays, in terms of their spatial/angular light distributions, but not necessarily in terms of the optical power split.
  • a cascade of BS components (which may not be identical in their power splitting behaviour) will define the optical paths between the OIP and the ORP.
  • Each copy of the OIP will follow one particular optical path through the BS network.
  • the initial beam splitter (BS 1) splits the light into two paths such that 33% of the optical power travels straight through the beam splitter and out towards the ORP.
  • the optical design shown here uses microlenses to collimate the light from the points in the OIP and it uses microlenses to image the beams through the beam splitter network.
  • BS can be used to perform multiple imaging and that, if desired, the optical power splitting performed by the beams splitters can be designed to allow an approximately even sharing of the optical power between copies of the input image .
  • the process used to control the multiple imaging of the OIP array to the ORP should aim to communicate the optical energy from a point source in the OIP to its corresponding receivers in the output plane. Any optical energy which is imaged to the OIP which does not arrive at its correct receiver area will be seen as optical crosstalk between channels in the switch.
  • the spot size of each of the fan-out spots must be controlled by the optical system in order that the major proportion of its light will impinge on a single optical detector in the ORP.
  • auxiliary fast buffer (Figure 11) can be added to provide a retiming function but can result in packets being discarded on the "knock-out" principle ( Figure 12 does not contain this function) .
  • W can be chosen to match the speed capability of the storage technology.
  • the purpose of the inter sub-segment stuffing bits is to allow the serial shifting to stop without loss of information while parallel read-out takes place from a shift register into the queue store.
  • Part of the local address is the destination port number of the output and at each output port there is a queue of pointers.
  • the address of the queue store location assigned to it is put on the relevant pointer queue.
  • the number of locations in the queue store per packet is T, the tranche size.
  • Segment size, tranche size and W can be adjusted within limits to match the capability of the core switch - in particular the speed/size performance of the queue store can be optimised.
  • Each output stream is assigned a time slot modulo N/F with read time available of N WF/Ng sees.
  • the output process is the converse off the input, i.e. parallel read-out from the queue store with parallel read-in into a shift register, one per port. The stuffing bits are reinserted and serial read out takes place from the shift registers.
  • output can be into a packet re-assembler, which involves stripping off the stuffing and local address bits and reconstituting the full packet from packet segments in the form appropriate to its outgoing network protocol .
  • the local header can be designed to embrace multistage operation and no stripping is necessary at that point.

Abstract

L'invention concerne une architecture de routage par paquets, comprenant un dispositif de traitement de paquets à l'entrée, un commutateur central, et un dispositif de traitement de paquets à la sortie. Le dispositif de traitement de paquets à l'entrée traduit le format d'adresse d'entrée en une forme appropriée pour le fonctionnement rapide du commutateur central et segmente le paquet à une longueur convenant pour le commutateur central. Le commutateur central comprend trois parties principales, à savoir, un élément d'alignement d'entrée, une interconnexion optique et une sortance électrique. L'interconnexion optique peut comprendre une sortance optique ou un ensemble univoque de connexions. Le dispositif de traitement de paquets de sortie reconstitue le paquet en son format d'origine (à l'entrée). Le fonctionnement efficace de l'élément d'entrance électrique est réalisé par mise en phase du départ des paquets d'entrée, et l'élément d'entrance électrique contient les moyens de mémorisation permettant la mise en file d'attente nécessaire pour les paquets sortants. Les caractéristiques de l'invention résident dans l'architecture réalisée comme un tout, le procédé de mise en phase des paquets, l'organisation des circuits d'entrance électriques et l'utilisation d'un transfert orthogonal sectorisé (SOT).
PCT/GB2001/002155 2001-05-14 2001-05-14 Systeme de routage WO2002093843A1 (fr)

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Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005039119A1 (fr) * 2003-10-15 2005-04-28 Qualcomm Incorporated Procede, appareil et systeme de multiplexage d'unites de donnees de protocole
WO2005119858A2 (fr) * 2004-05-28 2005-12-15 Intel Corporation Appareil a lumiere laser accordable
US7818018B2 (en) 2004-01-29 2010-10-19 Qualcomm Incorporated Distributed hierarchical scheduling in an AD hoc network
US7882412B2 (en) 2004-10-05 2011-02-01 Sanjiv Nanda Enhanced block acknowledgement
US7894538B2 (en) 2003-08-27 2011-02-22 Qualcomm Incorporated Frequency-independent spatial processing for wideband MISO and MIMO systems
US8315271B2 (en) 2004-03-26 2012-11-20 Qualcomm Incorporated Method and apparatus for an ad-hoc wireless communications system
US8355372B2 (en) 2004-05-07 2013-01-15 Qualcomm Incorporated Transmission mode and rate selection for a wireless communication system
US8401018B2 (en) 2004-06-02 2013-03-19 Qualcomm Incorporated Method and apparatus for scheduling in a wireless network
US8842657B2 (en) 2003-10-15 2014-09-23 Qualcomm Incorporated High speed media access control with legacy system interoperability
US8903440B2 (en) 2004-01-29 2014-12-02 Qualcomm Incorporated Distributed hierarchical scheduling in an ad hoc network
US9072101B2 (en) 2003-10-15 2015-06-30 Qualcomm Incorporated High speed media access control and direct link protocol
US9137087B2 (en) 2003-10-15 2015-09-15 Qualcomm Incorporated High speed media access control
US9198194B2 (en) 2005-09-12 2015-11-24 Qualcomm Incorporated Scheduling with reverse direction grant in wireless communication systems
US9226308B2 (en) 2003-10-15 2015-12-29 Qualcomm Incorporated Method, apparatus, and system for medium access control
US9869836B2 (en) 2008-01-30 2018-01-16 Hewlett Packard Enterprise Development Lp Optical interconnects

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Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7894538B2 (en) 2003-08-27 2011-02-22 Qualcomm Incorporated Frequency-independent spatial processing for wideband MISO and MIMO systems
US8774098B2 (en) 2003-10-15 2014-07-08 Qualcomm Incorporated Method, apparatus, and system for multiplexing protocol data units
US9226308B2 (en) 2003-10-15 2015-12-29 Qualcomm Incorporated Method, apparatus, and system for medium access control
US9137087B2 (en) 2003-10-15 2015-09-15 Qualcomm Incorporated High speed media access control
US9072101B2 (en) 2003-10-15 2015-06-30 Qualcomm Incorporated High speed media access control and direct link protocol
EP2528281A1 (fr) * 2003-10-15 2012-11-28 Qualcomm Incorporated Procédé, appareil et système de multiplexage d'unités de données de protocole
WO2005039119A1 (fr) * 2003-10-15 2005-04-28 Qualcomm Incorporated Procede, appareil et systeme de multiplexage d'unites de donnees de protocole
US8842657B2 (en) 2003-10-15 2014-09-23 Qualcomm Incorporated High speed media access control with legacy system interoperability
US7818018B2 (en) 2004-01-29 2010-10-19 Qualcomm Incorporated Distributed hierarchical scheduling in an AD hoc network
US8903440B2 (en) 2004-01-29 2014-12-02 Qualcomm Incorporated Distributed hierarchical scheduling in an ad hoc network
US8315271B2 (en) 2004-03-26 2012-11-20 Qualcomm Incorporated Method and apparatus for an ad-hoc wireless communications system
US8355372B2 (en) 2004-05-07 2013-01-15 Qualcomm Incorporated Transmission mode and rate selection for a wireless communication system
WO2005119858A3 (fr) * 2004-05-28 2006-05-04 Intel Corp Appareil a lumiere laser accordable
WO2005119858A2 (fr) * 2004-05-28 2005-12-15 Intel Corporation Appareil a lumiere laser accordable
US8401018B2 (en) 2004-06-02 2013-03-19 Qualcomm Incorporated Method and apparatus for scheduling in a wireless network
US8578230B2 (en) 2004-10-05 2013-11-05 Qualcomm Incorporated Enhanced block acknowledgement
US7882412B2 (en) 2004-10-05 2011-02-01 Sanjiv Nanda Enhanced block acknowledgement
US9198194B2 (en) 2005-09-12 2015-11-24 Qualcomm Incorporated Scheduling with reverse direction grant in wireless communication systems
US9869836B2 (en) 2008-01-30 2018-01-16 Hewlett Packard Enterprise Development Lp Optical interconnects

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