WO2004002060A1 - Routeur de radiodiffusion lineairement extensible, configure pour le traitement de types de signaux d'entree audio multiples - Google Patents

Routeur de radiodiffusion lineairement extensible, configure pour le traitement de types de signaux d'entree audio multiples Download PDF

Info

Publication number
WO2004002060A1
WO2004002060A1 PCT/US2003/019392 US0319392W WO2004002060A1 WO 2004002060 A1 WO2004002060 A1 WO 2004002060A1 US 0319392 W US0319392 W US 0319392W WO 2004002060 A1 WO2004002060 A1 WO 2004002060A1
Authority
WO
WIPO (PCT)
Prior art keywords
router
data
aes
broadcast router
digital audio
Prior art date
Application number
PCT/US2003/019392
Other languages
English (en)
Inventor
Carl Christensen
David Lynn Bytheway
Lynn Howard Arbuckle
Original Assignee
Thomson Licensing S.A.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing S.A. filed Critical Thomson Licensing S.A.
Priority to AU2003278738A priority Critical patent/AU2003278738A1/en
Publication of WO2004002060A1 publication Critical patent/WO2004002060A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/622—Queue service order
    • H04L47/6225—Fixed service order, e.g. Round Robin
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools

Definitions

  • PCT/ (Atty. Docket No. IU010620), PCT/ (Atty. Docket No. IU020158),
  • PCT/ (Atty. Docket No. IU020159), PCT/ (Atty. Docket No. IU020160), PCT/ (Atty. Docket No. IU020161), PCT/ (Atty. Docket No. IU020162),
  • PCT/ (Atty. Docket No. IU020252), PCT/ (Atty. Docket No. IU020253),
  • PCT/ (Atty. Docket No. IU020254), PCT/ (Atty. Docket No.
  • the present invention relates to broadcast routers and, more particularly, to a linearly expandable broadcast router configured to handle multiple audio input signal types.
  • a broadcast router allows each one of a plurality of outputs therefrom to be assigned a signal from any one of a plurality of inputs thereto.
  • an N x M broadcast router has N inputs and M outputs coupled together by a routing engine which allows any one of the N inputs to be applied to each one of the M outputs.
  • it is desirable to construct larger broadcast routers for example, a 4N x 4M broadcast router.
  • One solution to building larger broadcast routers has been to employ the smaller broadcast router as a building block of the proposed larger broadcast router. This technique, however, resulted in the exponential growth of the proposed larger broadcast routers.
  • linearly expandable broadcast routers suffer from other types of deficiencies.
  • existing digital audio routers that are linearly expandable often require all inputs to be synchronous (i.e., having identical sample rates), or require all asynchronous inputs be forced through a sample rate converter, which prevents the router from transmitting the exact input data.
  • These issues pose a quality problem when dealing with normal digital audio, and can result in a complete loss of data when routing compressed digital audio data streams.
  • the present disclosure introduces the concept of a linearly expandable broadcast router that simultaneously routes synchronous signals, signals of multiple sample rates and asynchronous signals/signals with different alignments or slightly different rates.
  • the linearly expandable audio data router comprises a routing engine and a data store coupled to the routing engine and configured to store an input digital audio data signal received thereby as a series of data frames in a series of timeslots in response to queries of the data frames performed at a rate exceeding a maximum sample rate of the input digital audio data signal.
  • the present disclosure also introduces a method of routing asynchronous digital audio data signals.
  • the method includes: (1) receiving asynchronous digital audio data signal data frames in a plurality of buffers at a first rate, (2) querying the buffers at a second rate greater than the first rate to detect data in the buffers, (3) marking first routing timeslots as valid based on the querying, and (4) placing data detected by the querying in the valid marked timeslots.
  • the present disclosure also introduces a linearly expandable digital data router comprising, in one embodiment, means for receiving a digital signal as a series of data frames, means for querying the data frames at a rate faster than a sample rate of the data frames, means for storing timing information corresponding to the data frames, means for routing the data frames and the corresponding timing information, and means for re-framing the data frames based on the corresponding timing information.
  • FIG. 1 is a block diagram of one embodiment of a fully redundant, linear expandable broadcast router according to aspects of the present disclosure
  • FIG. 2 is an expanded block diagram of one embodiment of a first broadcast router component of the fully redundant, linearly expandable broadcast router shown in FIG. 1 ;
  • FIG. 3 is an expanded block diagram of one embodiment of an AES input circuit of the first broadcast router component shown in FIG. 2;
  • FIG. 4 is an expanded block diagram of one embodiment of an AES bi-phase decoder circuit of the AES input circuit shown in FIG. 3
  • FIG. 5 is an expanded block diagram of one embodiment of a transport multiplexer of the AES input circuit shown in FIG. 3;
  • FIG. 6 is an expanded block diagram of one embodiment of an AES output circuit of the first broadcast router component shown in FIG. 2;
  • FIG. 7 is an expanded block diagram of one embodiment of a transport demultiplexer of the AES output circuit shown in FIG. 6.
  • the fully redundant, linearly expandable broadcast router 100 is comprised of plural broadcast router components coupled to one another to form the larger fully redundant linearly expandable broadcast router 100.
  • Each broadcast router component is a discrete router device which includes first and second router matrices, the second router matrix being redundant of the first router matrix.
  • each broadcast router has first and second routing engines, one for each of the first and second router matrices, each receiving, at an input side thereof, the same input digital audio data streams and placing, at an output side thereof, the same output digital audio data streams.
  • each of the broadcast router components used to construct the fully redundant, linearly expandable broadcast router are N x M sized broadcast routers.
  • the fully redundant, linearly expandable broadcast router 100 could instead be constructed of broadcast router components of different sizes relative to one another.
  • the fully redundant, linearly expandable broadcast router 100 is formed by coupling together first, second, third and fourth broadcast router components 102, 104, 106 and 108.
  • first, second, third and fourth broadcast router components 102, 104, 106 and 108 are purely by way of example. Accordingly, it should be clearly understood that a fully redundant, linearly expandable broadcast router constructed in accordance with the teachings of the present invention may be formed using various other numbers of broadcast router components.
  • the first, second, third and fourth broadcast router components 102, 104, 106 and 108 which, when fully connected in the manner disclosed herein, collectively form the fully redundant, linearly expandable broadcast router 100, may either be housed together in a common chassis as illustrated in FIG.
  • the broadcast router components 102, 104, 106 and 108 may have different sizes relative to one another or, in the alternative, may all have the same N x M size, one size that has proven suitable for the uses contemplated herein is 256 x 256.
  • a suitable configuration for the fully redundant, linear expandable broadcast router 100 would be to couple five broadcast router components, each sized at 256 x 256, thereby resulting in a 1 ,280 x 1 ,280 broadcast router.
  • the first broadcast router component 102 is comprised of a first router matrix 102a and a second (or “redundant”) router matrix 102b used to replace the first router matrix 102a in the event of a failure thereof.
  • each one of the second, third and fourth broadcast router components 104, 106, and 108 of the fully redundant, linearly expandable broadcast router 100 are comprised of a first router matrix 104a, 106a and 108a, respectively, and a second (or “redundant") router matrix 104b, 106b and 108b, respectively, used to replace the first router matrix 104a, 106a and 108a, respectively, in the event of a failure thereof.
  • the designation of the second router matrices 102b, 104b, 106b and 108b as a redundant matrix for use as a backup for the first router matrices 102a, 104a, 106a and 108 a, respectively, in the event of a failure thereof is purely arbitrary and it is fully contemplated that either one of a router matrix pair residing within a broadcast router component may act as a backup for the other of the router matrix pair residing within that broadcast router component.
  • the first router matrix 102a of the first broadcast router component 102, the first router matrix 104a of the second broadcast router component 104, the first router matrix 106a of the third broadcast router component 106 and the first router matrix 108a of the fourth broadcast router component 108 are coupled together in a first arrangement of router matrices which conforms to a fully connected topology.
  • the second router matrix 102b of the first broadcast router component 102, the second router matrix 104b of the second broadcast router component 104, the second router matrix 106b of the third broadcast router component 106 and the second router matrix 108b of the fourth broadcast router component 108 are coupled together in a second arrangement which, like the first arrangement, conforms to a fully connected topology.
  • each router matrix of an arrangement of router matrices is coupled, by a discrete link, to each and every other router matrix forming part of the arrangement of router matrices.
  • first, second and third bi-directional links 110, 112 and 114 couples the first router matrix 102a of the first broadcast router component 102 to the first router matrix 104a of the second broadcast router component 104, the first router matrix 106a of the third broadcast router component 106 and the first router matrix 108a of the fourth broadcast router component 108, respectively.
  • fourth and fifth bi-directional links 116 and 118 couple the first router matrix 104a of the second broadcast router component 104 to the first router matrix 106a of the third broadcast router component 106 and the first router matrix 108a of the fourth broadcast router component 108, respectively.
  • a sixth bi-directional link 120 couples the first router matrix 106a of the third broadcast router component 106 to the first router matrix 108a of the fourth broadcast router component 108.
  • first, second and third bidirectional links 122, 124 and 126 couples the second router matrix 102b of the first broadcast router component 102 to the second router matrix 104b of the second broadcast router component 104, the second router matrix 106b of the third broadcast router component 106 and the second router matrix 108b of the fourth broadcast router component 108, respectively.
  • fourth and fifth bi-directional links 128 and 130 couple the second router matrix 104b of the second broadcast router component 104 to the second router matrix 106b of the third broadcast router component 106 and the second router matrix 108b of the fourth broadcast router component 108, respectively.
  • a sixth bi-directional link 132 couples the second router matrix 106b of the third broadcast router component 106 to the second router matrix 108b of the fourth broadcast router component 108.
  • the bidirectional links 110 through 120 may be formed of copper wire, optical fiber or another transmission medium deemed suitable for the exchange of digital signals.
  • the pairs of broadcast router components may instead be coupled together by first and second unidirectional links.
  • FIG. 2 shows the first broadcast router component 102.
  • the second, third and fourth broadcast router components 104, 106 and 108 are similarly configured to the first broadcast router component 102 and need not be described in greater detail.
  • certain components of the foregoing description of the first broadcast router component 102, as well as the second, third and fourth broadcast routers 104, 106 and 108 have been simplified for brevity of description.
  • the broadcast router 102 includes N selectors 138-1 through
  • each one of the selectors 138-1 through 138-N is a first 2: 1 selector circuit having, as a first input thereto, a first transport stream built by an Audio Engineering Society (“AES”) input circuit 140-1 through 140-N, respectively, and, as a second input thereto, a second transport stream built from a decoded digital audio data stream conforming to the multichannel digital audio (“MADI”) standard by a MADI input circuit 142-1 through 142-N, respectively.
  • AES Audio Engineering Society
  • MADI multichannel digital audio
  • Each one of the first selector circuits 138-1 through 138- N further includes a control input (not shown) for selecting between the two transport streams.
  • the selected transport stream output each one of the first selector circuits 138-1 through 138-N is fed to an input side of a routing engine 144, a transmitting (or “TX") expansion port 276, a first receiving (or “RX”) expansion port 278, a second receiving expansion port 280 and a third receiving expansion port 282 of the first router matrix 102a.
  • TX transmitting
  • RX first receiving expansion port
  • the transmitting expansion port 276 of the first router matrix 102a is comprised of a memory subsystem in which the transport streams received from the first selector circuits 138-1 through 138-N of the first broadcast router component 102 are buffered before transfer to plural destinations and a processor subsystem for controlling the transfer of the transport streams received from the first selector circuits 138-1 through 138-N to a receiving expansion port of the first router matrix 104a of the second broadcast router component 104, the first router matrix 106a of the third broadcast router component 106 and the first router matrix 108a of the fourth broadcast router component 108.
  • each one of the first, second and third expansion ports 278, 280 and 282 of the first router matrix 102a are, in a broad sense, comprised of a memory subsystem in which input transport streams received from a transmitting expansion port of the first router matrix of another broadcast router component may be buffered before transfer to their final destination and a processor subsystem for controlling the transfer of the input transport streams received from the transmitting expansion port of the first router matrix of the other broadcast router component to inputs of the routing engine 144 of the first router matrix 102a of the first broadcast router component 102.
  • transport streams 1 through N containing information extracted from AES input 1-32N and/or MADI inputs 1-N are transmitted to the routing engine 144 and the transmission expansion port 276.
  • input transport streams 1 through N are forwarded to the first router matrix 104a of the second broadcast router component 104 over the link 110, to the first router matrix 106a of the third broadcast router 106 over the link 112 and to the first router matrix 108a of the fourth broadcast router 108 over the link 114.
  • input transport streams N+l through 2N are transmitted, from the transmission expansion port of the first router matrix 104a of the second broadcast router component 104, to the first receiver expansion port 278 over the link 110;
  • input transport streams 2N+1 through 3N are transmitted, from the transmission expansion port of the first router matrix 106a of the third broadcast router component 106, to the second receiver expansion port 280 over the link 112; and
  • input transport streams 3N+1 through 4N are transmitted, from the transmission expansion port of the first router matrix 108a of the fourth broadcast router component 108, to the third receiver expansion port 282 over the link 114.
  • input transport streams N+l through 2N, 2N+1 through 3N and 3N+1 through 4N are input, by the first, second and third receiver expansion ports 278, 280 and 282, respectively, the routing engine 144.
  • the first and second router matrices 102a and 102b are redundant matrices relative to one another.
  • routing engine 152 of the second router matrix 102b must have the same set of input transport streams as the routing engine 144. Accordingly, in a fashion like that hereinabove described, the selected transport streams output each one of the first selector circuits 138-1 through 138-N are also fed to an input side of the routing engine 152 as well as a transmitting port 284.
  • the transport streams fed to the first receiving expansion port 278, the second receiving expansion port 290 and the third receiving expansion port 282 are also fed to a first receiving expansion ports 286, a second receiving expansion port 288 and a third receiving expansion port 290, respectively, of the second router matrix 102b.
  • the transmitting expansion port 284 of the second router matrix 102b is comprised of a memory subsystem in which the transport streams received from the first selector circuits 138-1 through 138-N of the first broadcast router component 102 are buffered before transfer to plural destinations and a processor subsystem for controlling the transfer of the transport streams received from the selector circuits 138-1 through 138-N to a receiving expansion port of the second router matrix 104b of the second broadcast router component 104, the second router matrix 106b of the third broadcast router component 106 and the second router matrix 108b of the fourth broadcast router component 108.
  • each one of the first, second and third expansion ports 286, 288 and 290 of the second router matrix 102b are, in a broad sense, comprised of a memory subsystem in which the transport streams received from a transmitting expansion port of the first router matrix of another broadcast router component may be buffered before transfer to their final destination and a processor subsystem for controlling the transfer of the transport streams received from the transmitting expansion port of the first router matrix of the other broadcast router component to inputs of the routing engine 152 of the second router matrix 102b of the first broadcast router component 102.
  • input transport streams 1 through N are transmitted to the routing engine 152 and the transmission expansion port 284. From the transmission expansion port 284, input transport streams 1 through N are forwarded to the second router matrix 104b of the second broadcast router component 104 over the link 122, to the second router matrix 106b of the third broadcast router 106 over the link 124 and to the second router matrix 108b of the fourth broadcast router 108 over the link 126.
  • input transport streams N+l through 2N are transmitted, from the transmission expansion port of the second router matrix 104b of the second broadcast router component 104, to the third receiver expansion port 290 over the link 122;
  • input transport streams 2N+1 through 3N are transmitted, from the transmission expansion port of the second router matrix 106b of the third broadcast router component 106, to the second receiver expansion port 288 over the link 124; and
  • input transport streams 3N+1 through 4N are transmitted, from the transmission expansion port of the second router matrix 108b of the fourth broadcast router component 108, to the first receiver expansion port 288 over the link 126.
  • the input transport streams N+l through 2N, 2N+1 through 3N and 3N+1 through 4N are transmitted, by the third, second and first receiver expansion ports 290, 288 and 286, respectively, to the routing engine 154.
  • Sample Time indicates the number of clock transitions that took place between x preambles of the incoming stream; Empty: is set if the receiver is receiving data but does not have a complete sample ready. At 48 KHz, over half of the data frames will be empty. At 96 KHz, less than half of the data frames will be empty; ok: is set if there are no known problems with the data. Normally, this bit indicates that the receiver is decoding a valid data stream. But the bit may also be cleared by the matrix if an error occurs; blocksync: determines the start of channel status block (blocksync is asserted if the received frame contained a Z preamble); uce: indicates whether an uncorrectable error was detected in the FEC. This bit is set in the expansion block and used by the output cards. If this bit is set, the output card will use the other stream, if present and not in error; P represents a parity bit for AES ;
  • C represents a channel status bit for AES ;
  • U represents a user bit for AES
  • V represents a validity bit for AES
  • Residing within the routing engine 144 of the first router matrix 102a is switching means for assigning any one of the 4N AES streams received as inputs to the routing engine
  • routing engine 144 may be embodied in software, for example, as a series of instructions; hardware, for example, as a series of logic circuits; or a combination thereof.
  • routing engine 152 residing within the routing engine 152 of the second router matrix 102b is switching means for assigning any one of the 4N input AES streams received as inputs to the routing engine 152 to any one of the M output lines of the routing engine 152.
  • the routing engine 152 may be variously embodied in software, hardware or a combination thereof.
  • One suitable configuration for the routing engines 144 and 152 would involve the use of data and time information extracted from the input transport streams as inputs to a Y x Z crosspoint matrix where Y is the maximum number of inputs allowed in a system and Z is the number of outputs in a chassis.
  • Another suitable configuration for the routing engines 144 and 152 would involve the use of a dual-ported RAM to route, to each one of M outputs, a selected one of N inputs. Such a routing engine is disclosed in co-pending
  • each one of the 1 through M AES streams output the routing engines 144 and 152 of the first and second router matrices 102a and 102b, respectively, of the first broadcast router component 102 are propagated to a corresponding one of second selector circuits 160-1 through 160-M.
  • the second selector circuits 160-1 through 160-M collectively determine whether the 1 through M AES streams output the routing engine 144 of the first routing matrix 102a or the 1 through M AES streams output the routing engine 152 of the second routing matrix 102b shall be the output of the first broadcast router component 102.
  • Each one of the second selector circuits 160-1 through 160-M share a common control input (not shown) for selecting whether the AES streams output the routing engine 144 or the AES streams output the routing engine 152 shall be passed by the second selector circuits 160-1 through 160-M.
  • the selected AES streams are propagated to a respective one of information duplication circuits 162-1 through 162-M.
  • the information duplication circuits 162-1 through 162-M pass the received AES streams to either the AES output circuits 164-1 through 164-M or the MADI output circuits 166-1 through 166-M for encoding and output from the first broadcast router component 102.
  • the received information streams were MADI streams, they, too, could be passed to either the AES output circuits 164-1 through 164-M or the MADI output circuits 166-1 through 166-M for encoding and output from the first broadcast router component 102.
  • FIG. 3 shows the AES input circuit 140-1.
  • the remaining AES input circuits, specifically, the AES input circuits 140-2 through 140-N are similarly configured to the AES input circuit 140-1 and need not be described in greater detail.
  • the AES input circuit 140-1 includes AES bi-phase decoder circuits 296-1 through 296-32 and a transport stream multiplexer 295.
  • Input to each one of the AES bi-phase decoder circuits 296-1 through 296-32 is a respective encoded input digital audio data stream, conforming to the AES-3 standard, and originating at a signal source (not shown).
  • the AES bi-phase decoder circuits 296-1 through 296-32 decodes the respective encoded AES input digital audio data stream received thereby.
  • the resulting 32 decoded AES input digital audio data streams produced by the AES bi-phase decoder circuits 296-1 through 296-32 are input the transport stream multiplexer 295 which builds, from the 32 decoded AES input digital audio data streams, an input transport stream which is passed to the selector circuit 138-1.
  • FIG. 4 shows the AES bi-phase decoder circuit 296-1.
  • the remaining AES biphase decoder circuits, specifically, the AES bi-phase decoder circuits 296-2 through 296-32 are similarly configured to the AES bi-phase decoder circuit 296-1 and need not be described in greater detail.
  • the AES bi-phase decoder 296-1 works by using a fast clock to sample an incoming data stream, here, the AES encoded digital audio data stream. In order to decode the encoded AES digital audio data stream, the AES biphase decoder 296-1 also requires an estimated bit time.
  • the term “fast clock” refers to a clock having a frequency of at least twenty times faster than the frequency of the incoming encoded AES digital audio data stream.
  • bit time refers to the number of fast clocks that will occur during a typical bit of the incoming encoded AES digital audio data stream.
  • the AES bi-phase decoder 296-1 may operate in two modes. In the first mode, the bit time is user-selected for direct input to the decoding logic circuit 298 while, in the second mode, the bit time is automatically generated from the incoming encoded AES digital audio data stream.
  • the AES bi-phase decoder 296-1 is comprised of a time extraction circuit 297, a decoding logic circuit 298, a bit time estimator 300 and an appropriately sized data store, for example, a 32-bit wide asynchronous first-in-first-out ("FIFO") memory 302.
  • the AES bi-phase decoder 296-1 receives the encoded AES digital audio data stream from the AES input 140-1. Within the AES bi-phase decoder 296-1, the encoded AES digital audio data stream is then routed to each of the time extraction circuit 297, the decoding logic circuit 298 and the bit time estimator 300.
  • the time extraction circuit 297 extracts certain time information, specifically, the number of fast clocks separating successive preambles, from the encoded AES digital audio data stream. The time extraction circuit 297 then passes the extracted time information to the decoding logic circuit 298 for decoding of the encoded AES digital audio data stream. For certain usages to be more fully described later, in one embodiment, the time extraction circuit 297 is further configured to pass the extracted time information to the transport stream multiplexer 295. Further details regarding the operation of the time extraction circuit 297 are set forth in greater detail in co- pending U.S. Patent Application Ser. No. 10/ (Atty. Docket No. IU020254) and previously incorporated by reference.
  • the AES input circuit 140-1 includes 32 bi-phase decoding circuits 296-1 through 296-32, each of which decodes a respective encoded AES input digital audio data stream.
  • the digital audio data stream to be decoded and certain time information, specifically, the number of fast clocks separating successive preambles are provided to the decoding logic circuit 298.
  • the decoding logic circuit 298 measures the time between subsequent transitions in the digital audio data stream to be decoded and, based upon the measured time separating such transitions, the decoding logic circuit 298 identifies logical ones, logical zeros, X-type preambles, Y-type preambles and Z-type preambles in the digital audio data stream.
  • the decoding logic circuit 298 Upon commencing the extraction of digital audio data from the encoded AES digital audio data stream, the decoding logic circuit 298 will place the first such decoded preamble, typically, a Z-type preamble, into bits 31-28 of the FIFO memory 302. By measuring the time separating subsequently detected transitions, additional data will be extracted from the received encoded AES digital audio data stream. For example, if the decoding logic circuit 298 subsequently identified a logical "0" or a logical "1", the newly decoded data bit would be transferred into bit 31 of the FIFO memory 302, thereby causing the first decoded preamble to be moved into bits 30-27 of the FIFO memory.
  • each such bit will be identified as either a logical "0", a logical "1" or as part of a preamble.
  • each data bit is successfully identified, it is transferred into bit 31 of the FIFO 302, thereby gradually filling the FIFO 302 with a first 32-bit subframe of AES digital data.
  • the decoding logic circuit 298 concludes that it has begun to decode a next 32-bit subframe of AES digital data. Accordingly, the existing contents of the FIFO 302 are transferred to the transport stream multiplexer 295 for construction of the input transport stream.
  • the transport multiplexer 295 includes plural data stores 304-1 through 304-32, each of which may be, for example, a suitably sized FIFO, and control circuitry 306, for example, a master scheduler, which may be embodied in either hardware or software.
  • Each of the FIFOs 304-1 through 304-32 forming part of the transport stream multiplexer 295 is coupled to a corresponding one of the FIFOs 296-1 through 296-32 forming part of the AES output circuit 140-1.
  • the data store described above may include components in addition to or in place of the FIFOs 304-1 through 304-32.
  • the input transport stream constructed by the AES input circuit 140-1 be comprised of synchronous signals, signals of multiple sample rates and asynchronous signals/signals with different alignments or slightly different sample rates.
  • the AES input data stream being decoded by the bi-phase decoder 296-1 may have a frequency of 96 KHz
  • the AES input stream being decoded by the bi-phase decoder 296-2 may have a frequency of 48 KHz
  • the AES input stream being decoded by the bi-phase decoder 296-3 may have a frequency of 44.1 KHz.
  • the decoding logic circuit 298 for a bi-phase decoder 296-1 through 296-32 determines that a 32-bit subframe of data has been decoded
  • the decoding logic circuit 298 for that bi-phase decoder 296-1 through 296-32 initiates the transfer of the decoded subframe of data from the FIFO 302 forming of that bi-phase decoder 296-1 through 296-32 to the FIFO 304-1 through 304-32 coupled thereto.
  • each one of the FIFOs 304-1 through 304-32 will periodically hold a subframe of decoded data for one of the AES input digital audio data streams.
  • the transport stream to be constructed by the master scheduler 306 is comprised of a series of time slots. Using a master clock input and a master strobe input to coordinate the alignment of the timeslots, the master schedule 306 constructs the transport stream by querying the FIFOs 304-1 through 304-32 to determine if the FIFOs 304-1 through 304-32 hold a subframe of decoded data for one of the AES digital audio data streams.
  • the master scheduler 306 will query the FIFOs 304-1 through 304-32 in a sequential order. For example, the master scheduler 306 may first query the FIFO 304-1, followed by the FIFO 304- 2, the FIFO 304-3 and so on. It is further contemplated that the master scheduler 306 may issue the query in various ways. For example, the master scheduler 306 may issue the query by asserting the QUERY input to the desired one of the FIFOs 304-1 through 304-32.
  • the queried FIFOs 304-1 through 304-32 contain a subframe of decoded data for one of the AES digital audio data streams
  • the queried FIFO 304-1 through 304-32 will transfer the subframe of decoded data to the master scheduler 306 on the DATA output and assert the VALID output.
  • the master scheduler 306 will place the received subframe of decoded data in a time slot of the transport stream being constructed which corresponds to the queried one of the FIFOs 304-1 through 304-32.
  • the master scheduler 306 marks the time slot holding the delivered subframe of decoded data as valid.
  • the FIFOs 304-1 through 304-32 are empty when queried by the master scheduler 306, no data will be transferred to the master scheduler 306 on the DATA output and the VALID output will remain deasserted.
  • the master scheduler 306 will then leave the timeslot corresponding to the queried one of the FIFOs 304-1 through 304-32 empty and mark the time slot as invalid.
  • the FIFOs 304-1 through 304-32 are queried at a rate faster than the maximum sample rate supported by the broadcast router 100, thereby ensuring that at least some of the time slots of the transport steam will be empty.
  • the FIFOs 304-1 through 304-32 may be queried at a rate 10% faster than the maximum sample rate supported by the broadcast router 100.
  • the master scheduler 306 builds a time-multiplexed transport stream having both full and empty time slots. Once constructed, the transport stream is propagated to the routing engines 144 and 152 for further processing in the manner previously described with respect to FIG. 2.
  • the output of the routing engines 144 and 152 is then passed to a digital audio or other type of encoder configured to rebuild the encoded AES digital audio data stream from the data or data and timing information contained therein.
  • the broadcast router 100 may be capable of routing asynchronous signals, including synchronous signals of multiple signal rates, because timing information corresponding to these asynchronous signals may be employed to deconstruct and reconstruct the encoded AES digital audio data stream.
  • the sources of the various AES digital audio data streams input the broadcast router 100 need not be based on the same clock.
  • the manipulation performed by the broadcast router components 102, 104, 106, 108 need not rely on timing data, for example, timing data obtained from a processor clock internal or external to the router 100, other than the timing information extracted from the encoded AES digital audio data stream itself.
  • FIG. 6 shows the AES output circuit 164-1.
  • the remaining AES output circuits, specifically, the AES output circuits 164-2 through 164-M are similarly configured to the AES output circuit 164-1 and need not be described in greater detail.
  • the AES output circuit 164-1 includes a transport stream demultiplexer 285 and AES bi-phase encoder circuits 287-1 through 287-M. In turn, as best shown in FIG.
  • the transport stream demultiplexer 285 includes control circuitry 308, for example a master descheduler, which may be embodied in either hardware or software, and plural data stores 310-1 through 310-32, each of which may be, for example, a suitably sized FIFO.
  • each one of the FIFOs 310-1 through 310-32 forming part of the transport stream demultiplexer 285 is coupled to a corresponding one of the bi-phase encoders 287-1 through 287-32 forming part of the AES output circuit 164-1.
  • the data store described above may include components in addition to or in place of the FIFOs 310-1 through 310-32.
  • the master schedule 306 deconstructs the transport stream by querying the FIFOs 304-1 through 304-32 to determine if the FIFOs 304-1 through 304-32 hold a subframe of decoded data for one of the AES digital audio data streams. If so, the master descheduler 308 removes the data contained in each one of the time slots of the transport stream and transfers the removed data to the appropriate one of the FIFOs 310-1 through 310-32. To do so, the master descheduler 308 checks each time slot to determine if it has been marked valid or invalid.
  • the master descheduler 308 forwards the data contained therein to the FIFO 310-1 through 310-32 which corresponds to the position of the queried time slot relative to the sequential order in which the time slots are arranged. For example, if the first time slot in the transport stream is marked valid, the data contained therein is transferred to the FIFO 310-1, if the second time slot in the transport stream is marked valid, the data contained therein is transferred to the FIFO 310-2, if the third time slot in the transport stream is marked valid, the data contained therein is transferred to the FIFO 310-3 and so on.
  • time information may be derived by determining which of the time slots for a particular FIFO were empty and which were filled with data. More specifically, by determining how much time separates successive valid time slots filled with data from a particular AES digital audio data stream, time information for that AES digital audio data stream may be readily ascertained.
  • the process by which time information for an AES digital audio data, stream is extracted by keeping track of the valid and invalid time slots in the decoded AES digital audio data stream is generally referred to as an "extra boxcar" configuration.
  • Employing this method may embed timing information into the data stream by keeping track of the empty boxcars in each stream.
  • embodiments may reduce the amount of storage space required to form the FIFO buffers 310-1 through 310-32 because dedicated timing information need not be stored therein, these embodiments may experience a higher delay attributable to the latency of the additional data manipulation required to track the "empty boxcars.”
  • the reconstructed decoded AES digital audio data streams are propagated to respective ones of the AES bi-phase encoder circuits 287-1 through 287-32 for generation of a bi-phase encoded AES digital audio data stream. Further details as to how the bi-phase encoder circuits 287-1 through 297-32 generate bi-phase encoded AES digital audio data streams are set forth in co- pending U.S. patent application Serial No. 10/ (Atty. Docket No. IU020158) and previously incorporated by reference.
  • the FIFOs 304-1 through 304-32 may be further configured to hold timing information for the subframes of decoded data held thereby. For example, upon the decoding logic circuit 298 for one of the bi-phase decoders 296-1 through 296-32 determining that a 32-bit subframe of data has been decoded, the decoding logic circuit 298 for that bi-phase decoder 296-1 through 296-32 may also initiate the transfer of timing information, extracted by the time extraction circuit 297, to the FIFO 304-1 through 304-32 coupled thereto.
  • both the data provided by the decoding logic circuit 298 and the timing information provided by the time extraction circuit 297 would be stored in the FIFOs 304-1 through 304-32 of the transport stream multiplexer 295.
  • this method differs little from that previously described.
  • the alignment may be accomplished by employing a reference signal. That is, a data signal to be routed may be initially aligned with the reference signal prior to routing operations. After routing, the data signal may be aligned when: (1) it is rebuilt (or re-framed) by an expansion port receiver (such as the expansion port receiver 278) or other receiver, (2) an output (such as the output 164-1) is switched to a particular input (such as the input 140-1), or (3) it locks to the reference signal. Thereafter, the routed data signal may continue to be transmitted to the selected output based on the timing information passed to the output along with the signal data. Thereafter, if the data signal is synchronous, it will remain locked to the reference signal. However, if the data signal is asynchronous, it will not remain locked to the reference signal.
  • custom tailored casing transitions may also be employed. Especially in those applications in which the data signal to be routed has substantially the same bit time as the reference signal, but the data signal and reference signal may be slightly out of alignment (or out of phase). The casing transitions may gradually delay or otherwise skew the data signal until it is once again aligned with the reference signal.

Abstract

L'invention concerne un routeur de données audio, linéairement extensible (100), comprenant un moteur d'acheminement (144) et une mémoire de données (304-1 à 304-32) couplée au moteur d'acheminement (144), et configurée pour mémoriser un signal reçu de données audio numériques d'entrée, sous forme d'une série de trames de données dans une série de tranches temporelles, en réponse à des demandes de trames de données effectuées à un débit excédant un débit maximum d'échantillons des signaux de données audio numériques d'entrée.
PCT/US2003/019392 2002-06-21 2003-06-20 Routeur de radiodiffusion lineairement extensible, configure pour le traitement de types de signaux d'entree audio multiples WO2004002060A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003278738A AU2003278738A1 (en) 2002-06-21 2003-06-20 Linearly expandable broadcast router configured for handling multiple audio input signal types

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US39084702P 2002-06-21 2002-06-21
US60/390,847 2002-06-21

Publications (1)

Publication Number Publication Date
WO2004002060A1 true WO2004002060A1 (fr) 2003-12-31

Family

ID=30000639

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/019392 WO2004002060A1 (fr) 2002-06-21 2003-06-20 Routeur de radiodiffusion lineairement extensible, configure pour le traitement de types de signaux d'entree audio multiples

Country Status (2)

Country Link
AU (1) AU2003278738A1 (fr)
WO (1) WO2004002060A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004002050A1 (fr) 2002-06-21 2003-12-31 Thomson Licensing S.A. Routeur de diffusion a tolerance de pannes

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5815146A (en) * 1994-06-30 1998-09-29 Hewlett-Packard Company Video on demand system with multiple data sources configured to provide VCR-like services
US6324165B1 (en) * 1997-09-05 2001-11-27 Nec Usa, Inc. Large capacity, multiclass core ATM switch architecture
US20020044563A1 (en) * 2000-03-10 2002-04-18 Tellabs Operations, Inc. Data packet scheduler

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5815146A (en) * 1994-06-30 1998-09-29 Hewlett-Packard Company Video on demand system with multiple data sources configured to provide VCR-like services
US6324165B1 (en) * 1997-09-05 2001-11-27 Nec Usa, Inc. Large capacity, multiclass core ATM switch architecture
US20020044563A1 (en) * 2000-03-10 2002-04-18 Tellabs Operations, Inc. Data packet scheduler

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004002050A1 (fr) 2002-06-21 2003-12-31 Thomson Licensing S.A. Routeur de diffusion a tolerance de pannes

Also Published As

Publication number Publication date
AU2003278738A1 (en) 2004-01-06

Similar Documents

Publication Publication Date Title
US7697529B2 (en) Fabric channel control apparatus and method
US6775300B2 (en) Clock distribution in a communications network
EP0859495A2 (fr) Réseau de données multimédia haut-débit
EP1216549B1 (fr) Resynchronisation de files d'attente: mise a niveau synchrone en temps reel d'un systeme de commutation reparti
US7027447B2 (en) Communications interface between clock domains with minimal latency
CA2387214A1 (fr) Commutation de protection sans a-coups
JPH11504496A (ja) 低い待ち時間、高いクロック周波数、プレジオ非同期 パケット・ベースクロスバー・スイッチング・チップ・システム及び方法
US20030118042A1 (en) Packet communications method and apparatus
JPH0888638A (ja) パケットスイッチング伝送システム
US7747447B2 (en) Broadcast router having a serial digital audio data stream decoder
UA48218C2 (uk) Спосіб передачі даних у мережі синхронної цифрової ієрархії (sdh) та мережа sdh
JPS63279633A (ja) 同報通信システム
JPH02226926A (ja) 多重チャネルｐｃｍタイプのリング上にｈｄｌｃフレームを伝送するためのシステム
US20050053022A1 (en) Encoding and merging multiple data streams of fibre channel network
JP3732412B2 (ja) パケット通信方法及び通信装置、中継開始ノード装置及び中継開始方法、中継ノード装置及び中継方法、中継終了ノード装置及び中継終了方法
US6931371B2 (en) Digital interface device
WO2004002060A1 (fr) Routeur de radiodiffusion lineairement extensible, configure pour le traitement de types de signaux d'entree audio multiples
EP1176768B1 (fr) Procédé et dispositif pour stocker des paquets ayant un indicateur de limite
US7035267B1 (en) Transferring and queueing length and data as one stream
JP4370246B2 (ja) リニアに拡張可能なブロードキャストルータ用のクロック抽出回路
TW591399B (en) Bus frame protocol
US8863203B2 (en) Video server apparatus
JP2006080715A (ja) トランスポート・ストリーム送信装置および受信装置
WO2004002081A1 (fr) Moteur de routage pour routeur de diffusion
JP4535256B2 (ja) 多重信号分離方法及び装置

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP