WO2003105189B1 - Strained-semiconductor-on-insulator device structures - Google Patents

Strained-semiconductor-on-insulator device structures

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Publication number
WO2003105189B1
WO2003105189B1 PCT/US2003/018007 US0318007W WO2003105189B1 WO 2003105189 B1 WO2003105189 B1 WO 2003105189B1 US 0318007 W US0318007 W US 0318007W WO 2003105189 B1 WO2003105189 B1 WO 2003105189B1
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WO
Grant status
Application
Patent type
Prior art keywords
strained
layer
method
substrate
forming
Prior art date
Application number
PCT/US2003/018007
Other languages
French (fr)
Other versions
WO2003105189A2 (en )
WO2003105189A3 (en )
Inventor
Glyn Braithwaite
Matthew T Currie
Eugene A Fitzgerald
Richard Hammond
Thomas A Langdo
Anthony J Lochtefeld
Original Assignee
Amberwave Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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    • HELECTRICITY
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/66772Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66893Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66916Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN heterojunction gate
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
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    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • HELECTRICITY
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275Vertical isolation by bonding techniques

Abstract

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Claims

AMENDED CLAIMS
[received by the International Bureau on 03 March 2004 (03.03.04); claims 188-190, 192-193, 196-198 and 200-202 are replaced by amended claims, claims 1-187, 191, 194-195 and 199 remain unchanged]
187. A method for forming a structure, the method comprising: providing a substrate having a strained semiconductor layer disposed over a dielectric layer; defining a collector in a portion of the strained semiconductor layer; forming a base over the collector; and forming an emitter over the base.
188. The method of claim 187, wherein the strained semiconductor layer is tensilely strained.
189. The method of claim 188, wherein the strained semiconductor layer comprises tensilely strained silicon.
190. The method of claim 187, wherein the strained semiconductor layer is compressively strained.
191. A method for forming a structure, the method comprising: providing a first substrate having a strained layer disposed thereon, wherein the strained layer includes a first semiconductor material; bonding the strained layer to a second substrate, wherein the second substrate comprises a bulk material; removing the first substrate from the strained layer, the strained layer remaining bonded to the bulk semiconductor material; defining a collector in a portion of the strained layer; forming a base over the collector; and forming an emitter over the base, wherein the strain of the strained layer is not induced by the second substrate and the strain is independent of lattice mismatch between the strained layer and the second substrate.
192. The method of claim 191, wherein the strained layer is tensilely strained.
193. The method of claim 192 wherein the strained layer comprises tensilely strained silicon.
194. The method of claim 187 wherein the strained layer is compressively strained.
65
195. A method for forming a structure, the method comprising: providing a relaxed substrate comprising a bulk material and a strained layer disposed in contact with the relaxed substrate, the strain of the strained layer not being induced by the underlying substrate and the strain being independent of a lattice mismatch between the strained layer and the relaxed substrate; defining a collector in a portion of the strained layer; forming a base over the collector; and forming an emitter over the base.
196. The method of claim 195, wherein the strained layer is tensilely strained.
197. The method of claim 196, wherein the strained layer comprises tensilely strained silicon.
198. The method of claim 195 wherein the strained layer is compressively strained.
199. A method for forming a structure, the method comprising: providing a substrate having a strained semiconductor layer disposed over a substrate dielectric layer; forming a transistor in the strained layer by forming a gate dielectric layer above a portion of the strained semiconductor layer, forming a gate contact above the gate dielectric layer, and forming a source region and a drain region in a portion of the strained semiconductor layer, proximate the gate dielectric layer; removing a portion of the strained layer and the substrate dielectric layer to expose a portion of the substrate; defining a collector in the exposed portion of the substrate; forming a base over the collector; and forming an emitter over the base.
200. The method of claim 199, wherein the strained layer is tensilely strained.
201. The method of claim 200, wherein the strained layer comprises tensilely strained silicon.
66
202. The method of claim 199, wherein the strained layer is compressively strained.
67
PCT/US2003/018007 2002-06-07 2003-06-06 Strained-semiconductor-on-insulator device structures WO2003105189B1 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US38696802 true 2002-06-07 2002-06-07
US60/386,968 2002-06-07
US60/404,058 2002-08-01
US40405802 true 2002-08-15 2002-08-15
US41600002 true 2002-10-04 2002-10-04
US10/264,935 2002-10-04
US60/416,000 2002-10-04
US10264935 US20030227057A1 (en) 2002-06-07 2002-10-04 Strained-semiconductor-on-insulator device structures

Publications (3)

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WO2003105189A2 true WO2003105189A2 (en) 2003-12-18
WO2003105189A3 true WO2003105189A3 (en) 2004-03-04
WO2003105189B1 true true WO2003105189B1 (en) 2004-05-21

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Publication number Priority date Publication date Assignee Title
US7119400B2 (en) * 2001-07-05 2006-10-10 Isonics Corporation Isotopically pure silicon-on-insulator wafers and method of making same
US7375385B2 (en) * 2002-08-23 2008-05-20 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups
US20070286952A1 (en) * 2003-07-31 2007-12-13 Jifeng Liu Method and Structure of Strain Control of Sige Based Photodetectors and Modulators
US7161169B2 (en) * 2004-01-07 2007-01-09 International Business Machines Corporation Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain
US7138302B2 (en) * 2004-01-12 2006-11-21 Advanced Micro Devices, Inc. Method of fabricating an integrated circuit channel region
US7282449B2 (en) 2004-03-05 2007-10-16 S.O.I.Tec Silicon On Insulator Technologies Thermal treatment of a semiconductor layer
FR2867307B1 (en) 2004-03-05 2006-05-26 Soitec Silicon On Insulator Heat treatment after smart-cut detachment
FR2867310B1 (en) * 2004-03-05 2006-05-26 Soitec Silicon On Insulator Technical improvement of the quality of a thin layer CHARGED
JP2008500720A (en) * 2004-05-25 2008-01-10 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Method of manufacturing a semiconductor device and such a device
WO2006060054A1 (en) * 2004-12-01 2006-06-08 Amberwave Systems Corporation Hybrid semiconductor-on-insulator and fin-field-effect transistor structures and related methods
JP5018066B2 (en) * 2006-12-19 2012-09-05 信越半導体株式会社 Manufacturing method of a strained Si substrate

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Publication number Priority date Publication date Assignee Title
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5240876A (en) * 1991-02-22 1993-08-31 Harris Corporation Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process
JP2001036054A (en) * 1999-07-19 2001-02-09 Mitsubishi Electric Corp Manufacture of soi substrate
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
WO2002015244A3 (en) * 2000-08-16 2002-10-31 Cheng Zhi Yuan Process for producing semiconductor article using graded expitaxial growth
US6603156B2 (en) * 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
US6717213B2 (en) * 2001-06-29 2004-04-06 Intel Corporation Creation of high mobility channels in thin-body SOI devices

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WO2003105189A3 (en) 2004-03-04 application

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