WO2003095712A2 - Procede de fabrication de structures tridimensionnelles solidaires de circuits a semi-conducteurs - Google Patents

Procede de fabrication de structures tridimensionnelles solidaires de circuits a semi-conducteurs Download PDF

Info

Publication number
WO2003095712A2
WO2003095712A2 PCT/US2003/014664 US0314664W WO03095712A2 WO 2003095712 A2 WO2003095712 A2 WO 2003095712A2 US 0314664 W US0314664 W US 0314664W WO 03095712 A2 WO03095712 A2 WO 03095712A2
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
mask
layer
layers
contact pads
Prior art date
Application number
PCT/US2003/014664
Other languages
English (en)
Other versions
WO2003095712A3 (fr
Inventor
Adam L. Cohen
Original Assignee
University Of Southern California
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University Of Southern California filed Critical University Of Southern California
Priority to AU2003228977A priority Critical patent/AU2003228977A1/en
Publication of WO2003095712A2 publication Critical patent/WO2003095712A2/fr
Publication of WO2003095712A3 publication Critical patent/WO2003095712A3/fr

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00126—Static structures not provided for in groups B81C1/00031 - B81C1/00119
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D1/00—Electroforming
    • C25D1/003—3D structures, e.g. superposed patterned layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/019—Bonding or gluing multiple substrate layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/05—Temporary protection of devices or parts of the devices during manufacturing
    • B81C2201/053—Depositing a protective layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
    • B81C2203/0735—Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • This invention relates to the field of electrochemical deposition and more particularly to the field of electrochemical fabrication which includes electrochemical deposition of one or more materials according to desired cross-sectional configurations so as to build up three-dimensional structures from a plurality of at least partially adhered layers of deposited material. More particularly the invention relates to the integration of multilayer electrochemically fabricated structures with semiconductor circuitry and in particular to the formation of such structures on integrated circuits.
  • This electrochemical deposition technique allows the selective deposition of a material using a unique masking technique that involves the use of a mask that includes patterned conformable material on a support structure that is independent of the substrate onto which plating will occur.
  • the conformable portion of the mask is brought into contact with a substrate while in the presence of a plating solution such that the contact of the conformable portion of the mask to the substrate inhibits deposition at selected locations.
  • these masks might be generically called conformable contact masks; the masking technique may be generically called a conformable contact mask plating process. More specifically, in the terminology of MEMGen ® Corporation of Burbank, California such masks have come to be known as INSTANT MASKSTM and the process known as INSTANT MASKINGTM or INSTANT MASKTM plating. Selective depositions using conformable contact mask plating may be used to form single layers of material or may be used to form multi-layer structures.
  • the teachings of the '630 patent are hereby incorporated herein by reference as if set forth in full herein. Since the filing of the patent application that led to the above noted patent, various papers about conformable contact mask plating (i.e. INSTANT MASKING) and electrochemical fabrication have been published:
  • Microstructures Micromachining and Microfabrication Process Technology, SPIE 1999 Symposium on Micromachining and Microfabrication, September 1999.
  • one or more additional layers may be formed adjacent to the immediately preceding layer and adhered to the smoothed surface of that preceding layer. These additional layers are formed by repeating the first through third operations one or more times wherein the formation of each subsequent layer treats the previously formed layers and the initial substrate as a new and thickening substrate.
  • At least a portion of at least one of the materials deposited is generally removed by an etching process to expose or release the three-dimensional structure that was intended to be formed.
  • the preferred method of performing the selective electrodeposition involved in the first operation is by conformable contact mask plating.
  • one or more conformable contact (CC) masks are first formed.
  • the CC masks include a support structure onto which a patterned conformable dielectric material is adhered or formed.
  • the conformable material for each mask is shaped in accordance with a particular cross- section of material to be plated. At least one CC mask is needed for each unique cross- sectional pattern that is to be plated.
  • the support for a CC mask is typically a plate-like structure formed of a metal that is to be selectively electroplated and from which material to be plated will be dissolved. In this typical approach, the support will act as an anode in an electroplating process.
  • the support may instead be a porous or otherwise perforated material through which deposition material will pass during an electroplating operation on its way from a distal anode to a deposition surface.
  • CC masks it is possible for CC masks to share a common support, i.e. the patterns of conformable dielectric material for plating multiple layers of material may be located in different areas of a single support structure.
  • the entire structure is referred to as the CC mask while the individual plating masks may be referred to as "submasks". In the present application such a distinction will be made only when relevant to a specific point being made.
  • the conformable portion of the CC mask is placed in registration with and pressed against a selected portion of the substrate (or onto a previously formed layer or onto a previously deposited portion of a layer) on which deposition is to occur.
  • the pressing together of the CC mask and substrate occur in such a way that all openings, in the conformable portions of the CC mask contain plating solution.
  • the conformable material of the CC mask that contacts the substrate acts as a barrier to electrodeposition while the openings in the CC mask that are filled with electroplating solution act as pathways for transferring material from an anode (e.g. the CC mask support) to the non-contacted portions of the substrate (which act as a cathode during the plating operation) when an appropriate potential and/or current are supplied.
  • Figure 1 (a) shows a side view of a CC mask 8 consisting of a conformable or deformabie (e.g. elastomeric) insulator 10 patterned on an anode 12.
  • the anode has two functions.
  • Figure 1 (a) also depicts a substrate 6 separated from mask 8.
  • One is as a supporting material for the patterned insulator 10 to maintain its integrity and alignment since the pattern may be topologically complex (e.g., involving isolated "islands" of insulator material).
  • the other function is as an anode for the electroplating operation.
  • CC mask plating selectively deposits material 22 onto a substrate 6 by simply pressing the insulator against the substrate then electrodepositing material through apertures 26a and 26b in the insulator as shown in Figure 1 (b). After deposition, the CC mask is separated, preferably non-destructively, from the substrate 6 as shown in Figure 1 (c).
  • the CC mask plating process is distinct from a "through-mask" plating process in that in a through-mask plating process the separation of the masking material from the substrate would occur destructively. As with through-mask plating, CC mask plating deposits material selectively and simultaneously over the entire layer.
  • the plated region may consist of one or more isolated plating regions where these isolated plating regions may belong to a single structure that is being formed or may belong to multiple structures that are being formed simultaneously.
  • CC mask plating as individual masks are not intentionally destroyed in the removal process, they may be usable in multiple plating operations.
  • Figures 1 (d) - 1 (f) Another example of a CC mask and CC mask plating is shown in Figures 1 (d) - 1 (f).
  • Figure 1(d) shows an anode 12' separated from a mask 8' that comprises a patterned conformable material 10' and a support structure 20.
  • Figure 1 (d) also depicts substrate 6 separated from the mask 8'.
  • Figure 1 (e) illustrates the mask 8' being brought into contact with the substrate 6.
  • Figure 1 (f) illustrates the deposit 22' that results from conducting a current from the anode 12' to the substrate 6.
  • Figure 1(g) illustrates the deposit 22' on substrate 6 after separation from mask 8'.
  • an appropriate electrolyte is located between the substrate 6 and the anode 12' and a current of ions coming from one or both of the solution and the anode are conducted through the opening in the mask to the substrate where material is deposited.
  • This type of mask may be referred to as an anodeless INSTANT MASKTM (AIM) or as an anodeless conformable contact (ACC) mask.
  • CC mask plating allows CC masks to be formed completely separate from the fabrication of the substrate on which plating is to occur (e.g. separate from a three-dimensional (3D) structure that is being formed).
  • CC masks may be formed in a variety of ways, for example, a photolithographic process may be used.
  • Figures 2(a) - 2(f) show that the process involves deposition of a first material 2 which is a sacrificial material and a second material 4 which is a structural material.
  • the CC mask 8 in this example, includes a patterned conformable material (e.g. an elastomeric dielectric material) 10 and a support 12 which is made from deposition material 2.
  • the conformal portion of the CC mask is pressed against substrate 6 with a plating solution 14 located within the openings 16 in the conformable material 10.
  • An electric current, from power supply 18, is then passed through the plating solution 14 via (a) support 12 which doubles as an anode and (b) substrate 6 which doubles as a cathode.
  • Figure 2(a) illustrates that the passing of current causes material 2 within the plating solution and material 2 from the anode 12 to be selectively transferred to and plated on the cathode 6.
  • the CC mask 8 is removed as shown in Figure 2(b).
  • Figure 2(c) depicts the second deposition material 4 as having been blanket-deposited (i.e. non- selectively deposited) over the previously deposited first deposition material 2 as well as over the other portions of the substrate 6.
  • the blanket deposition occurs by electroplating from an anode (not shown), composed of the second material, through an appropriate plating solution (not shown), and to the cathode/substrate 6.
  • the entire two-material layer is then planarized to achieve precise thickness and flatness as shown in Figure 2(d).
  • the multi-layer structure 20 formed of the second material 4 i.e. structural material
  • first material 2 i.e. sacrificial material
  • the embedded structure is etched to yield the desired device, i.e. structure 20, as shown in Figure 2(f).
  • FIG. 3(a) - 3(c) Various components of an exemplary manual electrochemical fabrication system 32 are shown in Figures 3(a) - 3(c).
  • the system 32 consists of several subsystems 34, 36, 38, and 40.
  • the substrate holding subsystem 34 is depicted in the upper portions of each of Figures 3(a) to 3(c) and includes several components: (1 ) a carrier 48, (2) a metal substrate 6 onto which the layers are deposited, and (3) a linear slide 42 capable of moving the substrate 6 up and down relative to the carrier 48 in response to drive force from actuator 44.
  • Subsystem 34 also includes an indicator 46 for measuring differences in vertical position of the substrate which may be used in setting or determining layer thicknesses and/or deposition thicknesses.
  • the subsystem 34 further includes feet 68 for carrier 48 which can be precisely mounted on subsystem 36.
  • the CC mask subsystem 36 shown in the lower portion of Figure 3(a) includes several components: (1 ) a CC mask 8 that is actually made up of a number of CC masks (i.e. submasks) that share a common support/anode 12, (2) precision X-stage 54, (3) precision Y-stage 56, (4) frame 72 on which the feet 68 of subsystem 34 can mount, and (5) a tank 58 for containing the electrolyte 16.
  • Subsystems 34 and 36 also include appropriate electrical connections (not shown) for connecting to an appropriate power source for driving the CC masking process.
  • the blanket deposition subsystem 38 is shown in the lower portion of Figure 3(b) and includes several components: (1 ) an anode 62, (2) an electrolyte tank 64 for holding plating solution 66, and (3) frame 74 on which the feet 68 of subsystem 34 may sit. Subsystem 38 also includes appropriate electrical connections (not shown) for connecting the anode to an appropriate power supply for driving the blanket deposition process.
  • the planarization subsystem 40 is shown in the lower portion of Figure 3(c) and includes a lapping plate 52 and associated motion and control systems (not shown) for planarizing the depositions.
  • the '630 patent sets forth a process for integrating EFAB production with integrated circuits.
  • the structural EFAB material is plated onto and in electrical contact with aluminum contact pads on the integrated circuit. These contact pads may be considered primary contact pads and the locations to which contact with the EFAB structural material will be made.
  • the integrated circuit design is modified to include secondary contact pads (i.e. one or more pads) that are electrically connected to the primary pads but are spaced therefrom by a distance.
  • the secondary contact pads provide connection points for feeding current to the primary contact pads so that the primary pads may function as cathodes during electroplating operations.
  • the process is illustrated in Figures 13a - 13i of that patent and is outlined as follows: 1. The process starts with a.
  • An integrated circuit that includes a silicon wafer 38, a primary contact pad 40, and a secondary contact pad 41 connected to the primary pad by conductor 42. With the exception of the contact pads 40 and 41 the integrated circuit is covered by passivation layer 44 ( Figure 13a & 13b); and b.
  • the copper disk 36 is adhered to the bottom surface of the silicon wafer 38 with the polyimide 34 coated surface of the copper disk located between the copper and the silicon. 3.
  • the silicon wafer is partially sawed through which assists in separation of the die after processing.
  • a photosensitive polyimide 35 is spin coated onto the top surface of wafer 38. This coating provides an additional passivation layer and potentially protects aluminum pads 40 and 41 during subsequent etching operations and it fills saw line 46. 5. The polyimide 35 is patterned by selective exposure to light and subsequent development to expose contact pads 40 and 41.
  • the wafer is degreased and immersed in zincate plating solution which provides a thin coating over the exposed aluminum contact pads to increase adhesion of subsequently deposited material.
  • a photoresist is applied and patterned leaving a valley into which copper may be deposited to form a bus 48 that connects contact pads 41 (Fig. 13d). Copper is deposited, for example by sputtering and the photoresist is removed leaving behind copper bus 48. 8. A photoresist is applied and patterned to cover most of bus 48 to prevent nickel from depositing thereon.
  • a thin plating base of copper 51 is deposited, e.g. by sputtering, over the entire surface of the integrated circuit.
  • the copper deposited by electroplating and sputtering is removed by etching.
  • the polyimide 35 is stripped thereby exposing the resulting microstructure device 54 attached to wafer 38 (Fig. 13i).
  • Formation of a second layer may then begin by applying a photoresist layer over the first layer and then repeating the process used to produce the first layer. The process is then repeated until the entire structure is formed and the secondary metal is removed by etching.
  • the photoresist is formed over the plating base or previous layer by casting and the voids in the photoresist are formed by exposure of the photoresist through a patterned mask via X-rays or UV radiation.
  • a first aspect of the invention provides an electrochemical fabrication process for producing a three-dimensional structure from a plurality of adhered layers, the process including: (A) selectively depositing at least a portion of a layer onto the substrate, wherein the substrate may include previously deposited material; (B) forming a plurality of layers such that successive layers are formed adjacent to and adhered to previously deposited layers, wherein said forming includes repeating operation (A) a plurality of times; wherein at least a plurality of the selective depositing operations include: (1 ) locating a mask on or in proximity to a substrate; (2) in presence of a plating solution, conducting an electric current between an anode and the substrate through the at least one opening in the mask, such that a selected deposition material is deposited onto the substrate to form at least a portion of a layer; and (3) separating the selected preformed mask from the substrate; wherein the substrate includes a semiconductor wafer or single die containing electrical circuitry and having contact pads to which structural material is to connect; and wherein the process of contacting
  • a second aspect of the invention provides an electrochemical fabrication process for producing a three-dimensional structure from a plurality of adhered layers, the process including: (A) selectively depositing at least a portion of a layer onto the substrate, wherein the substrate may include previously deposited material; (B) forming a plurality of layers such that successive layers are formed adjacent to and adhered to previously deposited layers, wherein said forming includes repeating operation (A) a plurality of times; wherein at least a plurality of the selective depositing operations include: (1 ) locating a mask on or in proximity to a substrate; (2) in presence of a plating solution, conducting an electric current between an anode and the substrate through the at least one opening in the mask, such that a selected deposition material is deposited onto the substrate to form at least a portion of a layer; and (3) separating the selected preformed mask from the substrate; wherein the substrate includes a semiconductor wafer or single die containing electrical circuitry and having contact pads to which structural material is to connect; and wherein the process of contacting
  • a third aspect of the invention provides an electrochemical fabrication process for producing a three-dimensional structure from a plurality of adhered layers, the process including: (A) selectively depositing at least a portion of a layer onto the substrate, wherein the substrate may include previously deposited material; (B) forming a plurality of layers such that successive layers are formed adjacent to and adhered to previously deposited layers, wherein said forming includes repeating operation (A) a plurality of times; wherein at least a plurality of the selective depositing operations include: (1 ) locating a mask on or in proximity to a substrate; (2) in presence of a plating solution, conducting an electric current between an anode and the substrate through the at least one opening in the mask, such that a selected deposition material is deposited onto the substrate to form at least a portion of a layer; and (3) separating the selected preformed mask from the substrate; wherein the substrate includes a semiconductor wafer or single die containing electrical circuitry and having contact pads to which structural material is to connect and having a passivation layer;
  • Figures 1 (a) - 1 (c) schematically depict side views of various stages of a CC mask plating process
  • Figures 1 (d) - (g) schematically depict a side views of various stages of a CC mask plating process using a different type of CC mask.
  • Figures 2(a) - 2(f) schematically depict side views of various stages of an electrochemical fabrication process as applied to the formation of a particular structure where a sacrificial material is selectively deposited while a structural material is blanket deposited.
  • Figures 3(a) - 3(c) schematically depict side views of various example subassemblies that may be used in manually implementing the electrochemical fabrication method depicted in Figures 2(a) - 2(f).
  • Figures 4(a) - 4(i) schematically depict the formation of a first layer of a structure using adhered mask plating where the blanket deposition of a second material overlays both the openings between deposition locations of a first material and the first material itself.
  • Figures 5(a) - 5(1) schematically depict side views of various stages of a process according to a first embodiment for forming electrochemically fabricated structures on integrated circuits.
  • Figures 6(a) - 6(f) schematically depict side views of various stages of a process according to one variation of a second embodiment for forming electrochemically fabricated structures on integrated circuits.
  • FIGS. 1 (a) - 1 (g), 2(a) - 2(f), and 3(a) - 3(c) illustrate various features of one form of electrochemical fabrication that are known.
  • Other electrochemical fabrication techniques are set forth in the '630 patent referenced above, in the various previously incorporated publications, in various other patents and patent applications incorporated herein by reference, still others may be derived from combinations of various approaches described in these publications, patents, and applications, or are otherwise known or ascertainable by those of skill in the art from the teachings set forth herein. All of these techniques may be combined with those of the various embodiments of various aspects of the invention to yield enhanced embodiments. Still other embodiments may be derived from combinations of the various embodiments explicitly set forth herein.
  • Figures 4(a)-4(i) illustrate various stages in the formation of a single layer of a multilayer fabrication process where a second metal is deposited on a first metal as well as in openings in the first metal where its deposition forms part of the layer.
  • a side view of a substrate 82 is shown, onto which patternable photoresist 84 is cast as shown in Figure 4(b).
  • a pattern of resist is shown that results from the curing, exposing, and developing of the resist.
  • the patterning of the photoresist 84 results in openings or apertures 92(a) - 92(c) extending from a surface 86 of the photoresist through the thickness of the photoresist to surface 88 of the substrate 82.
  • a metal 94 e.g. nickel
  • the photoresist has been removed (i.e. chemically stripped) from the substrate to expose regions of the substrate 82 which are not covered with the first metal 94.
  • a second metal 96 e.g., silver
  • Figure 4(g) depicts the completed first layer of the structure which has resulted from the planarization of the first and second metals down to a height that exposes the first metal and sets a thickness for the first layer.
  • Figure 4(h) the result of repeating the process steps shown in Figures 4(b) - 4 (g) several times to form a multi-layer structure are shown where each layer consists of two materials. For most applications, one of these materials is removed as shown in Figure 4(i) to yield a desired 3-D structure 98 (e.g. component or device).
  • the various electrochemical fabrication processes used in various embodiments, alternatives, and techniques disclosed herein may have application to conformable contact masks and masking operations, proximity masks and masking operations (i.e. operations that use masks that at least partially selectively shield a substrate by their proximity to the substrate even if contact is not made), non-conformable masks and masking operations (i.e. masks and operations based on masks whose contact surfaces are not significantly conformable), and adhered masks and masking operations (masks and operations that use masks that are adhered to a substrate onto which selective deposition or etching is to occur as opposed to only being contacted to it).
  • Various embodiments are directed to techniques for interfacing or integrating the electrochemical fabrication of multi-layer three dimensional structures with semiconductor devices (e.g.
  • the semiconductor devices are provided in wafer form or die form and are used as substrates for the electrochemical fabrication build up process. These devices may be supplied with a passivation layer of adequate thickness already applied or such layers may be thickened prior to beginning the integration process.
  • FIG. 5(a) - 5(1) An integration process of a first preferred embodiment is depicted in Figures 5(a) - 5(1).
  • a wafer 102 (or single die) is received from a standard IC fabrication process as shown in Figure 5(a).
  • the wafer includes electronic circuitry (not shown) with interface contact pads 104 and connected bus contact pads 106 exposed.
  • the pads are connected by runners 108 which travel under a passivation layer 112 which covers the surface of the wafer 102.
  • Pads 104 and runners 108 may have been specifically designed with the intent of integrating a device made by electrochemical fabrication, or alternatively pre- designed pads and interconnects that can serve as runners may be used.
  • Other pads (not shown) may be located on wafer 102 for purposes of wire bonding, flip chip packaging, etc.
  • a photoresist layer 122 is applied to the upper surface of the wafer as shown in Figure 5(b).
  • the photoresist is patterned so that the interface pads 104 remain covered with hardened photoresist 124 as shown in Figure 5(c). These covered pads are the ones to which the multilayer electrochemically fabricated structure will be interfaced.
  • a thin layer of copper 126 is deposited over the entire surface as shown in Figure 5(d).
  • the deposition of the copper may for example occur via a physical vapor deposition process (e.g. evaporated or sputtered), via electroless copper plating, or via direct metallization (i.e. direct plating).
  • a physical vapor deposition process e.g. evaporated or sputtered
  • electroless copper plating e.g. electroless copper plating
  • direct metallization i.e. direct plating
  • the adhesion between the copper and the exposed aluminum bus contact pads is not critical it may be unnecessary to apply a coating of zincate to the surface prior to copper deposition. But a zincate coating can be applied if desired or found necessary.
  • the bus contact pads 106 are located some distance from the interface contact pads, some damage by the copper to the bus contact pads may be acceptable. If such damage is a concern or found to be a problem a barrier layer can be applied prior to the copper deposition. The barrier layer can then be removed
  • the transition/barrier layer may include one or both of a coating of an adhesion promoter (such as zincate) and a diffusion barrier such as titanium nitride (TiN), tantalum (Ta), and/or tantalum Nitride (TaN).
  • an adhesion promoter such as zincate
  • a diffusion barrier such as titanium nitride (TiN), tantalum (Ta), and/or tantalum Nitride (TaN).
  • an electrochemical fabrication structural material 134 e.g., Ni
  • the deposits are again planarized as shown Figure 5(j) exposing the thickly plated copper 128, and removing the barrier layer 132 except near where it bounds the remaining nickel deposit 134 near the interface contact pads 104.
  • the electrochemical fabrication process is performed to build up the multiple layers of the three dimensional structure.
  • the multilayer deposition process is shown as completed in Figure 5(k).
  • the electrochemical fabrication process may be performed in a variety of manners and may include a variety of operations, such as, for example, selective depositions, selective etchings, blanket depositions, blanket etchings, planarization operations, and the like. It may also include various cleaning, activation, passivation, and other treatment operations. The selection of operations and the ordering of the operations may vary from build process to build process or even from layer-to-layer within a single build process. Any selective deposition operations, selective etching operations, or selective treatment operations may make use of contact masks (e.g. of the conformable or non-conformable 5 type), proximity masks, and/or adhered masks.
  • contact masks e.g. of the conformable or non-conformable 5 type
  • a diffusion barrier layer could be deposited prior to the thin copper deposit 126 but after formation of 5 the patterned resist 124, it could be removed by controlled etching as its surface area would be largely exposed compared to the amount of exposure that a coating between the interface contact pads 104 and the electrochemically fabricated structure would have. Due to this differential in exposure, it is believed that controlled etching may be performed, after layer formation is complete and the sacrificial material has been removed, to remove ,0 the barrier/transition layer from non-contact regions of the electrochemically fabricated structure without excessive damage to the contact regions after layer formation.
  • a barrier layer could be applied prior to the application of the photoresist thereby obviating the need for a potential barrier layer prior to thin copper deposition of Figure 5(d) and prior to the structural material deposition of '.5 Figure 5(i).
  • the uncovered portion of the barrier layer would be removed after the removal of the copper.
  • an adhesion transition layer may also be formed at different stages of the process.
  • the runner and bus pad would not be needed. 50
  • the interface pad is made larger than the area intended for deposition of the structural material (e.g. Ni).
  • the portion of the interface contact pad 104 that is not covered by the structural material serves as the contact pad (rather than having a remote contact pad).
  • the contact pad since Al metallization used in the integrated circuit device may be attacked by the Cu stripper, etching of the Cu surrounding the structural material may damage the pad near the structural material. Using the runner and remote contact pad avoids this problem. Also this alternative embodiment could benefit from the previous alternative embodiment where the pre-photoresist application of a barrier layer would inhibit the attack.
  • a second group of embodiments may take an alternative approach to interfacing the wafer 102 to the initial conductive deposits onto which the multiple layers of the structure will be formed.
  • Figures 6(a) - 6(f) show one variation of the second group of embodiments.
  • Figure 6(a) shows wafer 102 which may be prepared for the interfacing process by, for example, coating pads 140 with a material that facilitates electrodeposition
  • a catalyst 142 for an electroless plating bath that is suitable for depositing the sacrificial material has been applied to the surface of the IC passivation layer 112. Catalyst 142 may be selectively located on the
  • Catalyst 142 may be selectively applied, for example, by contacting the protruding surface of passivation 112 with a plate or stamp coated with a thin film of catalyst 142, or
  • catalyst 142 e.g. via an ink jet or an extrusion head.
  • sacrificial material 144 has been deposited onto the catalyzed surface, which is assumed to be confined to the top surface of passivation 112.
  • the deposit has been continued until material 144 'mushrooms' out and makes contact with the perimeter of pads 140. Once such contact is made, pads 140 are in
  • the starting layer includes 0 regions of sacrificial material (e.g., copper) and regions of structural material (e.g., nickel).
  • the starting layer includes a structural material in regions that contact the pads and are intended to be electrically active, while a temporary presence of copper is located in all other regions.
  • FIG. 5(a) - 5(1) An integration process of a first preferred embodiment is depicted in Figures 5(a) - 5(1).
  • a wafer 102 (or single die) is received from a standard IC fabrication process as shown in Figure 5(a).
  • the wafer includes electronic circuitry (not shown) with interface contact pads 104 and connected bus contact pads 106 exposed.
  • the pads are connected by runners 108 which travel under a passivation layer 1 12 which covers the surface of the wafer 102.
  • a photoresist layer 122 is applied to the upper surface of the wafer as shown in Figure 5(b).
  • the photoresist is patterned so that the interface pads 104 remained covered with hardened photoresist 124 as shown in Figure 5(c). These covered pads are the ones to which the multilayer electrochemically fabricated structure will be interfaced.
  • a thin layer of copper 126 is deposited over the entire surface as shown in Figure 5(d).
  • the deposition of the copper may for example occur via a physical vapor deposition process (e.g. evaporated or sputtered) or electroless copper plating.
  • a physical vapor deposition process e.g. evaporated or sputtered
  • electroless copper plating e.g. gold, silver, gold, silver, silver, copper, copper, copper, copper, or sputtered.
  • the adhesion between the copper and the exposed aluminum bus contact pads is not critical it may be unnecessary to apply a coating of zincate to the surface prior to copper deposition. But a Zincate coating can be applied is desired or found necessary.
  • the bus contact pads 106 are located some distance from the interface contact pads, some damage by the copper to the bus contact pads may be acceptable. If such damage is a concern or found to be a problem a barrier layer can be applied prior to the copper deposition. The barrier layer can then be removed toward the end of the process after removal of the copper
  • the transition/barrier layer may include one or both of a coating of an adhesion promoter (such as zincate) amid a diffusion barrier such as titanium nitride (TiN), tantalum (Ta), and/or tantalum Nitride (TaN).
  • an adhesion promoter such as zincate
  • TiN titanium nitride
  • Ta tantalum
  • TaN tantalum Nitride
  • an electrochemical fabrication structural material 134 e.g., Ni
  • an electrochemical fabrication structural material 134 e.g., Ni
  • the structural material of choice is nickel and the sacrificial material of choice is copper, and in other embodiments other or additional structural materials may be chosen and other or additional sacrificial materials may be chosen.
  • Some embodiments may be based on a combination of the teachings herein with various teachings incorporated herein by reference. Some embodiments may not use any blanket deposition process and/or they may not use a planarization process. Some embodiments may involve the selective deposition of a plurality of different materials on a single layer or on different layers. Some embodiments may use blanket depositions processes that are not electrodeposition processes. Some embodiments may use selective deposition processes on some layers that are not conformable contact masking processes and are not even electrodeposition processes. Some embodiments may use nickel as a structural material while other embodiments may use different materials such as gold, silver, or any other electrodepositable materials that can be separated from the copper and/or some other sacrificial material.
  • Some embodiments may use copper as the structural material with or without a sacrificial material. Some embodiments may remove a sacrificial material while other embodiments may not.
  • the anode may be different from the conformable contact mask support and the support may be a porous structure or other perforated structure. Some embodiments may use multiple conformable contact masks with different patterns so as to deposit different selective patterns of material on different layers and/or on different portions of a single layer. In some embodiments, the depth of deposition will be enhanced by pulling the conformable contact mask away from the substrate as deposition is occurring in a manner that allows the seal between the conformable portion of the CC mask and the substrate to shift from the face of the conformal material to the inside edges of the conformable material.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Materials Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Analytical Chemistry (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Cette invention a trait à des procédés améliorés de fabrication par voie électrochimique de structures multicouche tridimensionnelles, utilisant comme substrat des circuits à semi-conducteurs. Certaine régions électriquement fonctionnelles de cette structure sont faites d'un matériau structural (du nickel, par exemple) adhérant aux plots de contact du circuit. Les plots de contact en aluminium et les structures au silicium sont protégés des dégâts causés par une diffusion du cuivre par application de couches barrière appropriées.
PCT/US2003/014664 2002-05-07 2003-05-07 Procede de fabrication de structures tridimensionnelles solidaires de circuits a semi-conducteurs WO2003095712A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003228977A AU2003228977A1 (en) 2002-05-07 2003-05-07 Method of and apparatus for forming three-dimensional structures integral with semiconductor based circuitry

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37918302P 2002-05-07 2002-05-07
US60/379,183 2002-05-07

Publications (2)

Publication Number Publication Date
WO2003095712A2 true WO2003095712A2 (fr) 2003-11-20
WO2003095712A3 WO2003095712A3 (fr) 2005-08-18

Family

ID=29420501

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/014664 WO2003095712A2 (fr) 2002-05-07 2003-05-07 Procede de fabrication de structures tridimensionnelles solidaires de circuits a semi-conducteurs

Country Status (3)

Country Link
US (2) US20040065554A1 (fr)
AU (1) AU2003228977A1 (fr)
WO (1) WO2003095712A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1711961A2 (fr) * 2003-12-31 2006-10-18 Microfabrica Inc. Procede et dispositif pour maintenir le parallelisme de couches et/ou obtenir des epaisseurs voulues de couches pendant la fabrication electrochimique de structures
WO2009083488A1 (fr) * 2007-12-31 2009-07-09 Nivarox-Far S.A. Procédé de fabrication d'une microstructure métallique et microstructure obtenue selon ce procédé

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW522238B (en) * 2001-10-18 2003-03-01 Chipmos Technologies Inc Method for manufacturing probes of a probe card
AU2003228974A1 (en) * 2002-05-07 2003-11-11 Memgen Corporation Method of and apparatus for forming three-dimensional structures
US20070238265A1 (en) * 2005-04-05 2007-10-11 Keiichi Kurashina Plating apparatus and plating method
KR100870820B1 (ko) * 2005-12-29 2008-11-27 매그나칩 반도체 유한회사 이미지 센서 및 그의 제조방법
EP2803083A4 (fr) 2012-01-10 2014-12-31 Hzo Inc Masques servant à l'application de revêtements de protection sur des ensembles électroniques, ensembles électroniques masqués, et procédés associés
JP2014522543A (ja) 2012-06-18 2014-09-04 エイチズィーオー・インコーポレーテッド 完全に組み立てられている電子デバイスの内部表面へ保護被覆を塗工するためのシステム及び方法
US9894776B2 (en) 2013-01-08 2018-02-13 Hzo, Inc. System for refurbishing or remanufacturing an electronic device
US10449568B2 (en) 2013-01-08 2019-10-22 Hzo, Inc. Masking substrates for application of protective coatings
JP6034884B2 (ja) 2013-01-08 2016-11-30 エイチズィーオー・インコーポレーテッド 基板からの保護被覆選択部分の除去

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5685491A (en) * 1995-01-11 1997-11-11 Amtx, Inc. Electroformed multilayer spray director and a process for the preparation thereof
US6027630A (en) * 1997-04-04 2000-02-22 University Of Southern California Method for electrochemical fabrication
WO2000042231A2 (fr) * 1999-01-15 2000-07-20 The Regents Of The University Of California Films de polysilicium-germanium permettant de realiser des systemes micro-electromecaniques

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5829128A (en) * 1993-11-16 1998-11-03 Formfactor, Inc. Method of mounting resilient contact structures to semiconductor devices
US5011580A (en) * 1989-10-24 1991-04-30 Microelectronics And Computer Technology Corporation Method of reworking an electrical multilayer interconnect
US5190637A (en) * 1992-04-24 1993-03-02 Wisconsin Alumni Research Foundation Formation of microstructures by multiple level deep X-ray lithography with sacrificial metal layers
US5378583A (en) * 1992-12-22 1995-01-03 Wisconsin Alumni Research Foundation Formation of microstructures using a preformed photoresist sheet
US6023103A (en) * 1994-11-15 2000-02-08 Formfactor, Inc. Chip-scale carrier for semiconductor devices including mounted spring contacts
US6064213A (en) * 1993-11-16 2000-05-16 Formfactor, Inc. Wafer-level burn-in and test
US5718618A (en) * 1996-02-09 1998-02-17 Wisconsin Alumni Research Foundation Lapping and polishing method and apparatus for planarizing photoresist and metal microstructure layers
US5994152A (en) * 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
US5866281A (en) * 1996-11-27 1999-02-02 Wisconsin Alumni Research Foundation Alignment method for multi-level deep x-ray lithography utilizing alignment holes and posts
US5801100A (en) * 1997-03-07 1998-09-01 Industrial Technology Research Institute Electroless copper plating method for forming integrated circuit structures
US6008102A (en) * 1998-04-09 1999-12-28 Motorola, Inc. Method of forming a three-dimensional integrated inductor
US6255126B1 (en) * 1998-12-02 2001-07-03 Formfactor, Inc. Lithographic contact elements
US6569701B2 (en) * 2001-10-25 2003-05-27 Rockwell Automation Technologies, Inc. Method for fabricating an isolated microelectromechanical system device
TWI227285B (en) * 2001-10-15 2005-02-01 Univ Southern California Methods of and apparatus for producing a three-dimensional structure
US7252861B2 (en) * 2002-05-07 2007-08-07 Microfabrica Inc. Methods of and apparatus for electrochemically fabricating structures via interlaced layers or via selective etching and filling of voids
US7259640B2 (en) * 2001-12-03 2007-08-21 Microfabrica Miniature RF and microwave components and methods for fabricating such components
US20030221968A1 (en) * 2002-03-13 2003-12-04 Memgen Corporation Electrochemical fabrication method and apparatus for producing three-dimensional structures having improved surface finish
US20040065550A1 (en) * 2002-05-07 2004-04-08 University Of Southern California Electrochemical fabrication methods with enhanced post deposition processing
US7250101B2 (en) * 2002-05-07 2007-07-31 Microfabrica Inc. Electrochemically fabricated structures having dielectric or active bases and methods of and apparatus for producing such structures
WO2003095715A1 (fr) * 2002-05-07 2003-11-20 University Of Southern California Procedes et appareil de surveillance de la qualite de depot au cours d'operations de galvanoplastie effectuees a l'aide d'un masque de contact adaptable
AU2003228974A1 (en) * 2002-05-07 2003-11-11 Memgen Corporation Method of and apparatus for forming three-dimensional structures
AU2003228976A1 (en) * 2002-05-07 2003-11-11 Memgen Corporation Multistep release method for electrochemically fabricated structures
WO2003095713A1 (fr) * 2002-05-07 2003-11-20 University Of Southern California Procedes et appareils de masquage de contacts adaptables utilisant une activation cathodique in situ d'un substrat
JP4554357B2 (ja) * 2002-05-07 2010-09-29 マイクロファブリカ インク 電気化学的に成型加工され、気密的に封止された微細構造および上記微細構造を製造するための方法および装置
US7229542B2 (en) * 2002-05-07 2007-06-12 Microfabrica Inc. Methods of and apparatus for molding structures using sacrificial metal patterns

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5685491A (en) * 1995-01-11 1997-11-11 Amtx, Inc. Electroformed multilayer spray director and a process for the preparation thereof
US6027630A (en) * 1997-04-04 2000-02-22 University Of Southern California Method for electrochemical fabrication
WO2000042231A2 (fr) * 1999-01-15 2000-07-20 The Regents Of The University Of California Films de polysilicium-germanium permettant de realiser des systemes micro-electromecaniques

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
COHEN A ET AL: "EFAB: rapid, low-cost desktop micromachining of high aspect ratio true 3-D MEMS" MICRO ELECTRO MECHANICAL SYSTEMS, 1999. MEMS '99. TWELFTH IEEE INTERNATIONAL CONFERENCE ON ORLANDO, FL, USA 17-21 JAN. 1999, PISCATAWAY, NJ, USA,IEEE, US, 17 January 1999 (1999-01-17), pages 244-251, XP010321754 ISBN: 0-7803-5194-0 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1711961A2 (fr) * 2003-12-31 2006-10-18 Microfabrica Inc. Procede et dispositif pour maintenir le parallelisme de couches et/ou obtenir des epaisseurs voulues de couches pendant la fabrication electrochimique de structures
EP1711961A4 (fr) * 2003-12-31 2008-10-22 Microfabrica Inc Procede et dispositif pour maintenir le parallelisme de couches et/ou obtenir des epaisseurs voulues de couches pendant la fabrication electrochimique de structures
WO2009083488A1 (fr) * 2007-12-31 2009-07-09 Nivarox-Far S.A. Procédé de fabrication d'une microstructure métallique et microstructure obtenue selon ce procédé
JP2011521098A (ja) * 2007-12-31 2011-07-21 ニヴァロックス−ファー ソシエテ アノニム 金属微細構造体を製作する方法およびこの方法により得られる微細構造体
US8557506B2 (en) 2007-12-31 2013-10-15 Nivarox-Far S.A. Method of fabricating a metallic microstructure and microstructure obtained via the method

Also Published As

Publication number Publication date
US20040065554A1 (en) 2004-04-08
AU2003228977A1 (en) 2003-11-11
AU2003228977A8 (en) 2003-11-11
WO2003095712A3 (fr) 2005-08-18
US20070221505A1 (en) 2007-09-27

Similar Documents

Publication Publication Date Title
US20040004001A1 (en) Method of and apparatus for forming three-dimensional structures integral with semiconductor based circuitry
US20070221505A1 (en) Method of and Apparatus for Forming Three-Dimensional Structures Integral With Semiconductor Based Circuitry
US7640651B2 (en) Fabrication process for co-fabricating multilayer probe array and a space transformer
US7195989B2 (en) Electrochemical fabrication methods using transfer plating of masks
US7501328B2 (en) Methods for electrochemically fabricating structures using adhered masks, incorporating dielectric sheets, and/or seed layers that are partially removed via planarization
US7109118B2 (en) Electrochemical fabrication methods including use of surface treatments to reduce overplating and/or planarization during formation of multi-layer three-dimensional structures
US7250101B2 (en) Electrochemically fabricated structures having dielectric or active bases and methods of and apparatus for producing such structures
US20050067292A1 (en) Electrochemically fabricated structures having dielectric or active bases and methods of and apparatus for producing such structures
US20050202180A1 (en) Electrochemical fabrication methods for producing multilayer structures including the use of diamond machining in the planarization of deposits of material
US20160258075A1 (en) Method of Forming Electrically Isolated Structures Using Thin Dielectric Coatings
US20090197371A1 (en) Integrated Circuit Packaging Using Electrochemically Fabricated Structures
US7531077B2 (en) Electrochemical fabrication process for forming multilayer multimaterial microprobe structures
US7384530B2 (en) Methods for electrochemically fabricating multi-layer structures including regions incorporating maskless, patterned, multiple layer thickness depositions of selected materials
US7527721B2 (en) Electrochemical fabrication method for producing multi-layer three-dimensional structures on a porous dielectric
US9244101B2 (en) Electrochemical fabrication process for forming multilayer multimaterial microprobe structures
US20090165295A1 (en) Electrochemical Fabrication Methods Incorporating Dielectric Materials and/or Using Dielectric Substrates
US20150307997A1 (en) Methods for Fabricating Metal Structures Incorporating Dielectric Sheets
US20160194774A1 (en) Electrochemical Fabrication Process for Forming Multilayer Multimaterial Microprobe Structures Incorporating Dielectrics
US20050189959A1 (en) Electrochemical fabrication process for forming multilayer multimaterial microprobe structures
US20090057157A1 (en) EFAB Methods Including Controlled Mask to Substrate Mating
US20080142369A1 (en) Integrated Circuit Packaging Using Electrochemically Fabricated Structures

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP