WO2003073685A1 - Interconnexion entre des bus de reseaux commandes au moyen de circuits anti-verrouillage - Google Patents

Interconnexion entre des bus de reseaux commandes au moyen de circuits anti-verrouillage Download PDF

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Publication number
WO2003073685A1
WO2003073685A1 PCT/EP2003/000687 EP0300687W WO03073685A1 WO 2003073685 A1 WO2003073685 A1 WO 2003073685A1 EP 0300687 W EP0300687 W EP 0300687W WO 03073685 A1 WO03073685 A1 WO 03073685A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
interface
relevant
input
modules
Prior art date
Application number
PCT/EP2003/000687
Other languages
English (en)
Inventor
Mario Besi
Marco Ripamonti
Original Assignee
Siemens Mobile Communications S.P.A.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Mobile Communications S.P.A. filed Critical Siemens Mobile Communications S.P.A.
Publication of WO2003073685A1 publication Critical patent/WO2003073685A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/18—Automatic changing of the traffic direction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/1461—Suppression of signals in the return path, i.e. bidirectional control circuits

Definitions

  • FIG. 1 is a diagram of an interconnection system of the type to which this invention is applied;
  • figure 2 is a large block diagram of the invention;
  • figure 3 is a block diagram of a an embodiment of the invention through analogue circuits ;
  • - figure 4 is a block diagram of a first embodiment of the implementation of fig. 3 ;
  • figure 5 is a block diagram of a second embodiment of the implementation of fig. 3;
  • figure 6 is a block diagram of an embodiment of the invention through logic circuits ;
  • figure 7 is a diagram similar to fig. 6, representing the implementation of the anti-locking circuit through logic ports ;
  • figure 8 is a large block diagram of a preferred embodiment of the invention.
  • the circuit 9 ' includes a couple of differential amplifiers 10A, 10B having the two inputs connected between the output and input terminals Tl, Rl and T2, R2 respectively, of one of the two interfaces 6l', 62', and the output connected to input terminal T2, Tl of the other interface.
  • each analogue interface cannot be considered completely linear. It shall be necessary to foresee that the idle points of the operational amplifiers are compensated in temperature, in order that the temperature does not shift the idle point in direct current. Also compensation means are not indicated. The sector technician could easily realize, through an analysis of the circuit, made according to ordinary techniques, that the circuit is perfectly stable.
  • figures 4, 5 show two analogue embodiments to be used when the lines 21, 22 are short lines in which one of the two wires (e.g. wire L) is common and acts as reference .
  • a structure of this type still enables a gain higher than one unit (but lower than 2) maintaining the circuit stability.
  • ports 28, 29 are connected between them in such a way to form the set/reset bi-stable (and therefore the output of one of the ports is connected to the input of the other one) .
  • the other input of ports 28, 29 is connected to the output of ports 26, 27, while outputs are connected to a first input of the last two ports 23, 24. These have in turn their second input connected to the output of port 26 and 27 respectively, and the outputs connected to input terminals Tl, T2.

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Small-Scale Networks (AREA)

Abstract

L'invention concerne un système d'interconnexion entre une pluralité de modules électroniques (5a...5n) par l'intermédiaire d'une ligne de transmission équilibrée (2, 21, 22) (BUS CAN) présentant une terminaison sur les deux extrémités. Lorsque les modules sont répartis sur une grande zone, il est habituellement nécessaire d'employer une ligne de longueur importante entraînant une baisse des performances en matière de débit de transmission. Pour obtenir de bonnes performances, les modules (5a...5n) sont divisés en groupes respectivement associés à une ligne de transmission correspondante (21, 22). Les lignes de transmission (21, 22) des groupes sont connectées par l'intermédiaire d'éléments (8) permettant de transférer les signaux présents sur une ligne (22) vers une autre ligne (c.-à-d. 21). La connexion est réalisée de manière que les modules électriques connectés aux lignes considèrent ces dernières comme une seule ligne.
PCT/EP2003/000687 2002-02-28 2003-01-23 Interconnexion entre des bus de reseaux commandes au moyen de circuits anti-verrouillage WO2003073685A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ITMI2002A000401 2002-02-28
IT2002MI000401A ITMI20020401A1 (it) 2002-02-28 2002-02-28 Sistema di interconnessione tra moduli elettronici utillzante linea di comunicaxione teminata alle due estremita'

Publications (1)

Publication Number Publication Date
WO2003073685A1 true WO2003073685A1 (fr) 2003-09-04

Family

ID=11449391

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2003/000687 WO2003073685A1 (fr) 2002-02-28 2003-01-23 Interconnexion entre des bus de reseaux commandes au moyen de circuits anti-verrouillage

Country Status (2)

Country Link
IT (1) ITMI20020401A1 (fr)
WO (1) WO2003073685A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023137593A1 (fr) * 2022-01-18 2023-07-27 华为数字能源技术有限公司 Appareil et système de traitement de bus

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5809077A (en) * 1996-01-30 1998-09-15 Mercedes Benz Ag Circuit for signal-transmitting connection of data networks
US5923187A (en) * 1996-01-18 1999-07-13 U.S. Philips Corporation Multidirectional data transmission device
EP1073232A1 (fr) * 1999-07-27 2001-01-31 Koninklijke Philips Electronics N.V. Interface bidirectionelle
US20010004751A1 (en) * 1999-12-16 2001-06-21 Trw Automotive Electronics & Components Gmbh & Co. Kg Decoupling unit for bus systems
US6344756B1 (en) * 2000-11-14 2002-02-05 International Business Machines Corporation Echo cancellation circuit for a Bi-directional current mode link
EP1199836A2 (fr) * 2000-10-18 2002-04-24 FESTO AG & Co Répéteur de bus bidirectionel

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923187A (en) * 1996-01-18 1999-07-13 U.S. Philips Corporation Multidirectional data transmission device
US5809077A (en) * 1996-01-30 1998-09-15 Mercedes Benz Ag Circuit for signal-transmitting connection of data networks
EP1073232A1 (fr) * 1999-07-27 2001-01-31 Koninklijke Philips Electronics N.V. Interface bidirectionelle
US20010004751A1 (en) * 1999-12-16 2001-06-21 Trw Automotive Electronics & Components Gmbh & Co. Kg Decoupling unit for bus systems
EP1199836A2 (fr) * 2000-10-18 2002-04-24 FESTO AG & Co Répéteur de bus bidirectionel
US6344756B1 (en) * 2000-11-14 2002-02-05 International Business Machines Corporation Echo cancellation circuit for a Bi-directional current mode link

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EKIZ H ET AL: "Performance analysis of a CAN/CAN bridge", 1996 INTERNATIONAL CONFERENCE ON NETWORK PROTOCOLS (CAT. NO.96TB100070), 29 October 1996 (1996-10-29) - 1 November 1996 (1996-11-01), Los Alamitos, CA, USA, IEEE Comput. Soc. Press,, pages 181 - 188, XP002244716, ISBN: 0-8186-7453-9 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023137593A1 (fr) * 2022-01-18 2023-07-27 华为数字能源技术有限公司 Appareil et système de traitement de bus

Also Published As

Publication number Publication date
ITMI20020401A0 (it) 2002-02-28
ITMI20020401A1 (it) 2003-08-28

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