WO2003071550A1 - Dispositif de circuit integre a semi-conducteur - Google Patents

Dispositif de circuit integre a semi-conducteur Download PDF

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Publication number
WO2003071550A1
WO2003071550A1 PCT/JP2002/001659 JP0201659W WO03071550A1 WO 2003071550 A1 WO2003071550 A1 WO 2003071550A1 JP 0201659 W JP0201659 W JP 0201659W WO 03071550 A1 WO03071550 A1 WO 03071550A1
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Prior art keywords
write
address
data
memory
semiconductor memory
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PCT/JP2002/001659
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English (en)
Japanese (ja)
Inventor
Kan Takeuchi
Yoshinobu Nakagome
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Renesas Technology Corp.
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Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to JP2003570360A priority Critical patent/JPWO2003071550A1/ja
Priority to PCT/JP2002/001659 priority patent/WO2003071550A1/fr
Publication of WO2003071550A1 publication Critical patent/WO2003071550A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Definitions

  • the present invention relates to a semiconductor integrated circuit device, for example, a semiconductor memory such as a dynamic random access memory (hereinafter referred to as DRAM), a static random access memory (hereinafter referred to as SRAM), or a ferroelectric memory. It relates to technology that is effective for high reliability technology.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • ferroelectric memory ferroelectric memory
  • Japanese Unexamined Patent Application Publication No. 7-93171 discloses a method for detecting an error in write data and a write address during a memory write operation so that incorrect data is not written.
  • a configuration in which the writing operation is sometimes suppressed and only the process in which the writing is performed is forcibly terminated is described as a conventional technique.
  • Figures 31 to 34 show semiconductor memos. 3 shows an example of the write operation timing in the memory.
  • Figure 31 is for synchronous DRAM (SDRAM)
  • Figure 32 is for double-data rate SDRAM (DDR SDRAM)
  • Figure 33 is for direct 'run bus DRAM (DR DRAM)
  • Figure 34 Shows the case of a high-speed SRAM, respectively.
  • ACT is a row-system active '1 1 biochemistry
  • WR is specified and writes
  • MSK column system indicates the suppression of the write operation.
  • the notation of control signals follows general conventions.
  • the configuration for detecting an error in the data address is public.
  • the PC I bus is a typical example.
  • the present inventors have found that it is difficult to realize an address error in a semiconductor memory used as a cache or a main memory without deteriorating its high-speed performance. That is, it is necessary to suspend the write operation while detecting an error in the write address. And even if there are no errors, the latency will be reduced.
  • the semiconductor memory used as a cache or main memory has the peculiarity that it must respond at the operating speed as close as possible to the CPU, and it falls into the dilemma of achieving both high speed and high reliability. Further, as the speeding-up progresses, an address error occurs at the time of reception in the semiconductor memory. Therefore, the error detection needs to be performed inside the semiconductor memory at least after reception.
  • a dynamic circuit may be used as a 7-address / command decoder to increase the speed, and a decoding soft error may occur.
  • a decoding soft error may occur.
  • Japanese Patent Publication No. Sho 63-3-512999 states that, at the time of writing, a redundant code generated from both the write data and the write address is added to the write data and written to the memory, so that when reading, It describes a method for detecting an error from the data and code and the read address. In this case, it is not necessary to suspend the write operation, but there is a problem that irreversible destruction of the write data has already occurred.
  • An object of the present invention is to provide a semiconductor integrated circuit device that achieves both high speed and high reliability. Another object of the present invention is to provide a semiconductor memory which has achieved high reliability.
  • Detecting that at least one of the write address and the write command is incorrect is performed in parallel with the write operation and detected, preventing data from being written to an invalid memory cell and not writing. Means to notify the master device of this. Further, it has at least the features of any of the following first to fourth embodiments.
  • the burst write function (consecutive addresses in a continuous address by giving one initial address and burst length).
  • the time T rm from when the semiconductor memory receives the data until the data reaches the memory cell is longer for the first data of the burst write than for the last data. It is configured to be longer.
  • the semiconductor memory according to the first embodiment is used as a memory of a system having a cache memory at a higher level, that is, as a secondary cache or a main memory.
  • a single write function (a function of writing data only to one address in one shot) is further provided, and the above-mentioned T rm is better for the first data of the burst write. It is configured to be longer for single-write data.
  • the error detection operation is not performed in a single write.
  • the above address error detection is performed only for a part of the addresses, and among a plurality of memory cell groups divided by the part of the addresses, a certain memory cell group is determined.
  • This memory cell group corresponds to a page unit managed by OS (Operating System).
  • OS Operating System
  • this memory cell group corresponds to one application use area when multiple applications are executed simultaneously.
  • the semiconductor memory of the present invention is of an address multi-system (a system in which a first address group and a second address group are given with a time difference).
  • the part of the address for performing the address error detection is all of the first address group or a part thereof.
  • the error detection operation is started before receiving the write data.
  • the check information for performing the error detection operation is provided together with the write data, and among the processes required for the error detection operation, the processes that can be performed without the check information include the check information. Started without waiting for arrival.
  • a write command is internally generated by a combination of a plurality of control signals received by the semiconductor memory of the present invention, and any one of the plurality of control signal sets specifying the write command is used. If erroneous is received, it shall be set to no operation and notify the master device that writing has not been performed.
  • the write address is fetched twice at different times, and these are compared to detect an address error.
  • a register for changing a range of addresses for performing the address error detection is provided. This includes the case where the address range is zero, that is, no error detection is performed.
  • FIG. 1 is a block diagram showing one embodiment of a semiconductor memory according to the present invention.
  • FIG. 2 is a waveform diagram for explaining an example of a burst write operation of the semiconductor memory circuit of FIG. 1,
  • FIG. 3 is a main part circuit configuration diagram showing one embodiment of the semiconductor memory of FIG. 1,
  • FIG. 4 illustrates an example of the operation of the burst write stop circuit of FIG. FIG.
  • FIG. 5 is a main part circuit configuration diagram showing another embodiment of the semiconductor memory of FIG. 1,
  • FIG. 6 is a waveform chart for explaining an example of the operation of the burst light stop circuit of FIG. 5,
  • FIG. 7 is a waveform diagram for explaining a single write operation in the semiconductor memory of FIG. 1,
  • FIG. 8 is a block diagram showing one embodiment of a computer system suitable for applying the semiconductor memory according to the present invention.
  • FIG. 9 is a schematic block diagram showing another embodiment of the semiconductor memory address according to the present invention.
  • FIG. 10 is a block diagram for explaining four embodiments in which only a part of the address is detected as an error.
  • FIG. 11 is a memory configuration diagram for explaining address error detection in case 1 of FIG.
  • FIG. 12 is a memory configuration diagram for explaining address error detection in case 4 of FIG.
  • FIG. 13 is a schematic waveform diagram for explaining an example of the operation of the semiconductor memory according to the present invention.
  • FIG. 14 is a schematic waveform diagram for explaining another example of the operation of the semiconductor memory according to the present invention.
  • FIG. 15 is a schematic waveform diagram for explaining still another example of the operation of the semiconductor memory according to the present invention.
  • FIG. 16 is a schematic configuration diagram showing one embodiment of the error detection circuit according to the present invention.
  • FIG. 17 is a diagram showing another embodiment of the semiconductor memory according to the present invention. It is a block diagram,
  • FIG. 18 is a waveform chart for explaining the operation of another embodiment of the semiconductor memory according to the present invention.
  • FIG. 19 is a block diagram showing still another embodiment of the semiconductor memory according to the present invention.
  • FIG. 20 is a waveform chart for explaining an example of the operation of the semiconductor memory of FIG.
  • FIG. 21 is an operation explanatory diagram for explaining the operation of the semiconductor memory to which the present invention is not applied;
  • FIG. 22 is an operation diagram for explaining the operation of the semiconductor memory to which the present invention is applied.
  • FIG. 23 is a command map diagram showing one embodiment of the semiconductor memory according to the present invention.
  • FIG. 24 is a circuit diagram showing one embodiment of a command error detection circuit according to the present invention.
  • FIG. 25 is a waveform chart for explaining still another example of the operation of the semiconductor memory according to the present invention.
  • FIG. 26 is a waveform chart for explaining still another example of the operation of the semiconductor memory according to the present invention.
  • FIG. 27 is a block diagram showing another embodiment of the system using the semiconductor memory according to the present invention.
  • FIG. 28 is a waveform chart for explaining an example of the operation of the system shown in FIG. 27.
  • FIG. 29 is a waveform chart for explaining another example of the operation of the system shown in FIG. 27.
  • FIG. 30 illustrates an example of still another operation of the semiconductor memory according to the present invention. It is a waveform diagram for clarification,
  • FIG. 31 is a timing chart for explaining an example of a write operation in a conventional semiconductor memory.
  • FIG. 32 is a timing chart for explaining another example of the write operation in the conventional semiconductor memory.
  • FIG. 33 is an evening diagram for explaining another example of the write operation in the conventional semiconductor memory.
  • FIG. 34 is a timing chart for explaining another example of the write operation in the conventional semiconductor memory.
  • FIG. 1 is a block diagram of one embodiment of the semiconductor memory according to the present invention.
  • the semiconductor memory shown in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor manufacturing technique.
  • the semiconductor memory chip 1 of this embodiment is provided with an error detection circuit (ED or 19) for detecting an error in an address and a command.
  • a control circuit (CL or 18) for performing the control logic and generating the timing signal is provided with a burst write stop circuit (BWH or 181).
  • BWH or 181 burst write stop circuit
  • the error detection circuit 19 sets the error signal er to a high level, for example, and sends the signal er to the burst write stop circuit 18 1.
  • the burst write stop circuit 18 1 suppresses the burst write to the memory cell by maintaining the write enable signal we-m at, for example, an input level, and performs writing by setting the terminal WRH to, for example, a high level. Notify the device that there was no message.
  • circuit configurations are the same as those of a semiconductor memory such as an ordinary SDRAM. That is, a memory array (MA or 10), a row decoder (RD or 11), a column decoder (0 or 12), a sense amplifier and 10 buses (SA or 13), and an address buffer which receives an address Ai. (AB or 14), refresh counter (RC or 15), column address counter (CAC or 16) for burst operation, output buffer ( ⁇ B or 17 1) that inputs and outputs data DQ, and input It has a buffer (IB or 172), a circuit (CL or 18) that inputs the clock CLK and the command Cmd, and the like.
  • the memory array MA includes dynamic memory cells arranged in a matrix, and according to the figure, memory cells arranged in the same column. Are connected to a word line (not shown) for each column, and the data input / output terminals of the memory cells arranged in the same row are connected to a complementary data line (not shown) for each row.
  • One of the word lines (not shown) of the memory array MA is driven to a selected level in accordance with a result of decoding a row address signal by a row (row) decoder RD.
  • a complementary data line (not shown) of the memory array MA is coupled to the sense amplifier SA and an I / O line of a column selection circuit included therein.
  • the sense amplifier SA is an amplifier circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from a memory cell.
  • the column selection circuit therein includes a switch circuit for selecting the complementary data lines individually and conducting to the complementary I / O lines. The column switch circuit is selectively operated according to the result of decoding the column address signal by the column decoder CD.
  • the SDRAM has a plurality of memory banks, a plurality of memory arrays MA, row decoders RD, sense amplifiers SA, and column selection circuits are provided in correspondence with each memory bank.
  • the complementary I / ⁇ line is shared for each memory bank and connected to the output terminal of an input buffer IB having a write buffer and the input terminal of an output buffer OB including a main amplifier.
  • the terminal DQ is not particularly limited, but is a data input / output terminal for inputting or outputting, for example, data DO-D15 consisting of 16 bits.
  • the terminal WHR is also used for a data strobe signal for outputting a read signal in a read operation, in addition to the above-described operation.
  • the address signal supplied from the address input terminal Ai is temporarily held in an address buffer AB, and among the above address signals input in time series, a row-related address signal is held in a row address latch, and This is transmitted to the row decoder RD.
  • the column address signal is held in a column address counter C A C also serving as a column address latch, and transmitted to a column decoder CD 9.
  • the refresh counter RC generates a line address at the time of automatic refresh (Automatic Refresh) and self refresh (Self Refresh).
  • the column address signal is supplied as preset data of the column address count CAC, and a column address signal as the preset data or a value obtained by sequentially incrementing the column address signal in the burst mode specified by a command or the like. Is output to the column decoder CD.
  • the control circuit CL holds various operation mode information including a mode register.
  • the row decoder RD has a plurality of memory banks as described above, only the row decoder RD corresponding to the specified bank operates to perform the operation of selecting the read line.
  • the control circuit CL is particularly limited However, in addition to the clock signal CLK, the clock enable signal CKE, chip select signal / CS, column address strobe signal / CAS, input address strobe signal / RAS, and write control signal / WE and other external control signals. , / DM and DQS and the address signal via the mode register are supplied to control the operation mode of the SDRAM and the operation of the above circuit block based on the level change and timing of those signals. And an input buffer corresponding to each signal.
  • the clock signal CLK is input to the synchronization circuit DLL included in the circuit CL via the clock buffer, and an internal clock is generated.
  • the internal clock is not particularly limited, the internal clock is output using the output timing of the output buffer #B and the terminal WRH as a strobe signal.
  • the clock signal CLK passed through the clock buffer is supplied to an input buffer IB and a column address counter CAC.
  • the chip select signal / CS instructs the start of the command input cycle by its low level.
  • the chip select signal / CS is high (chip not selected), other inputs have no meaning.
  • internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by changes to the chip non-selection state.
  • the / RAS, / CAS, and / WE signals have different functions from the corresponding signals in normal DRAM, and are significant when defining the command cycle described later.
  • the clock enable signal CKE indicates the validity of the next clock signal. If the signal CKE is at a high level, the rising edge of the next clock signal CLK is valid, and if it is at a low level, it is invalid. It is said.
  • an external control signal / OE for controlling the output enable for the output buffer OB is provided, such a signal / ⁇ E is also supplied to the control circuit CL, and the signal is, for example, a high level. At times, the output buffer OB is brought into a high output impedance state.
  • FIG. 2 is a waveform diagram for explaining an example of the burst write operation of the semiconductor memory circuit of FIG.
  • a burst write command cmd and a write address Ai are provided.
  • data 1 to data 4 are continuously provided from a terminal DQ corresponding to a burst length of 4.
  • a mouthpiece activation command ACT is given before the burst write command cmd (write) (not shown).
  • the command and address are checked by the error detection circuit ED, and if an error is detected, the error signal er goes high. At a predetermined timing thereafter, it is determined whether or not the write enable signal wem to the memory cell is transited to the enable high level.
  • the write enable signal WE-m is maintained at the low level, and the writing of data 1 to 4 into the memory cell is suppressed. If the error signal er is at low level, the write enable signal wem is set to high level to write data 1 to data 4 to the memory cell.
  • At least the first data 1 is temporarily stored in a buffer included in the input buffer IB or the sense amplifier S A, and waits so as not to reach the memory cell.
  • the data path to the memory cell is formed only after the write enable signal w e -m transitions to the noy level.
  • FIG. 3 shows a circuit diagram of a main part of one embodiment of the semiconductor memory shown in FIG.
  • FIG. 1 shows the configuration of a more specific embodiment of the write system circuit.
  • a switch 134 is provided between the sense amplifier 1311 and the complementary bit line of the memory array 10. The switch 134 is controlled by a write enable signal we-in formed by the burst write stop circuit B WH.
  • the first write data of the burst write input from the terminal DQ is the input buffer 17 2, the sub-I 0 1 3 2 in the sense amplifier circuit 13, and the input I 0 line 1 io 1
  • the latch is latched by the sense amplifier 13 1 through the power switch 13 3.
  • the column switch 133 selected by the column decoder 12 is in the ON state.
  • the write enable signal we_m is at the low level, the switch 134 is shut off (OFF state), and the first write data does not reach the memory cells of the memory array 10.
  • the signal sac is a sense amplifier activation signal.
  • FIG. 4 is a waveform diagram for explaining an example of the operation of the burst write stop circuit 18 1 of FIG.
  • the write enable signal wem changes from the high level to the low level, and the switch 134 is turned off.
  • the row activation has been completed at this point, and the read data is latched in the sense amplifier 131. That is, the stored information of a large number of dynamic memory cells connected to the selected mode line is transmitted to the sense amplifier 131, and amplified by the switch 1334. The amplified storage information is rewritten to the dynamic memory cell.
  • the burst write signal we_bst is reset in the circuit of this embodiment.
  • the address / command error detection has been completed, and the error signal er is in response to either the high level or the low level.
  • the write enable signal WE-m becomes the high level again and the write to the memory cell is permitted (write).
  • the write enable signal WE-m remains at the low level, and writing is not permitted (halt). In the case of this halt, the terminal WRH in Fig. 1 becomes high level, and the master device receiving this takes action such as re-executing the write.
  • the signal er When the burst write mode ends, for example, after the word line is deactivated, the signal er is reset to low level, and as a result, the latch of the burst write stop circuit 18 1 is reset and temporarily set to low level as described above.
  • the write enable signal we-m is reset to high level.
  • FIG. 5 shows a main part circuit configuration diagram of another embodiment of the semiconductor memory of FIG.
  • a plurality of latches 132-1-1, 132-2 and the like are provided in the sub-input circuit 13 of the sense amplifier 13.sub.1.
  • a gate circuit controlled by the write enable signal we1 m is provided at the output of the column decoder 12.
  • the first write data of the burst write input from the terminal DQ passes through the input buffer 172 to the plurality of sub-inputs provided in the sub-inputs 1312 of the sense amplifier 1311. Latched to one of the output circuits 1332_1.
  • the write enable signal we-m is at the low level, and the output operation of the column decoder 12 is stopped, so that the switch 13 is shut off. Therefore, the first write data does not reach the sense amplifier 13 1 and the memory cells of the memory array 10. In the case of a DRAM, the row activation has been completed, and the sense amplifier 13 1 has latched the read data from the memory array 10.
  • Subsequent write data 2, data 3, and data 4 are latched to the sub input / output circuits 132-2, 132-2-3 (not shown), and 132-4 (not shown), respectively. In this way, the number of latches and the local I-line corresponding to the burst length are formed.
  • the column switch 13 33 is shut off in response to the write enable signal we-m being at the low level, as described above. Does not reach the memory cell.
  • the write data is transferred to the local I 0 line 1 i 0 1 to 1 Via i04 (not shown), it is written to the memory cell in parallel.
  • FIG. 6 is a waveform diagram for explaining an example of the operation of the burst write stop circuit 181 in FIG.
  • the result of address / command error detection is determined at the timing of time t2 when the first data 2 is received, and the write enable signal we-m transitions to high level to write to the memory cell. It is determined whether to permit. at the time Thus, the write data has reached the sub I0 part. Therefore, in response to the high level of the write enable signal we- m, the column switch 13 33 is turned on, data 1 and 2 are written almost simultaneously, and data 3 and data 4 are input at the same time. The data is written via the sense amplifier 13 1 according to the timing.
  • the write enable signal we_m remains at the mouth level, and the column switch 133 remains off regardless of the high level of the selection signal Y14.
  • the write data 1 to 4 input from the terminal DQ reach only the above-mentioned latches 13 2 _ 1 to 13 2 _ 4, and writing to the memory cell is prevented.
  • FIG. 7 is a waveform chart for explaining a single-write operation in the semiconductor memory of FIG.
  • the single write operation the internal signal WE- sg 1 becomes high level, the internal signal W e- bst remains low.
  • the operation is stopped and an address / command error occurs even though the above-described semiconductor memory has an error detection circuit ED. No detection is performed.
  • the error signal er remains at the low level
  • the write enable signal wem remains at the high level
  • the function of preventing writing to the memory cell is stopped.
  • the write data is transferred to the memory cell over a data path. Is formed immediately after a single write command is input, so that writing can be completed in one cycle.
  • the error detection circuit ED attempts to operate during single-write operation, the operation speed is reduced by that much. The problem that the memory cycle is lengthened by stopping the error detection circuit and the write prevention circuit as described above can be avoided.
  • FIG. 8 is a block diagram showing one embodiment of a computer system suitable for applying the semiconductor memory according to the present invention.
  • the system uses the semiconductor memory (MM) 1 according to the present invention as a main memory, and has a memory controller (M CH) 3 between the semiconductor memory 1 and the central processing unit 2, an I 0 controller (I CH) 4, And a large-capacity hard disk storage (LM) 5 connected to the I0 controller 4.
  • the central processing unit 2 includes a CPU 21 and a cache memory (Che) 22.
  • the CPU 21 further includes an internal register (REG) 211.
  • accesses to the main memory are collectively performed in units larger than the data processing unit handled by the central processing unit 2.
  • the access is basically a burst operation. A high-speed and highly reliable semiconductor memory can be obtained.
  • a highly versatile semiconductor memory that can be applied to other types of systems that do not include a cache can be obtained.
  • a system that does not include a cache often emphasizes low cost, and high reliability is not required. Therefore, if the semiconductor memory of the first embodiment of the present invention is used, the performance matching the characteristics of the system can be achieved. Is obtained.
  • access to the large-capacity hard disk storage device 5 is generally performed in a larger data unit (N ⁇ m ⁇ L ⁇ m 2) bytes.
  • FIG. 9 is a schematic block diagram showing another embodiment of the semiconductor memory address according to the present invention. This embodiment is directed to a configuration for detecting an error in only a part of the address signal.
  • an address signal A_d designates a device (semiconductor memory chip), and an address signal A-b designates a bank.
  • (A-d, A-b) designates a memory mat MA1 (or MA2). It is specified.
  • the address signals A-ru and A-r1 specify a row address, that is, a word line. Of these, the address signal A-ru specifies the sub-blocks SB1 to SB4, and the address signal A-r1 specifies the sub-block SB1. Specify the position of the guide line in ⁇ SB4.
  • the address signal A—c specifies a column address, that is, a bit line. The memory cell at the intersection of the selected word line and the selected bit line will be selected.
  • FIG. 10 is a block diagram of four embodiments for detecting an error in only a part of the address.
  • the column address signal A-c is not detected (no error check).
  • column address Do not check signal A-c and address signal A-r1 that specifies the position of the lead line in the sub-block (no error check).
  • case 3 only the memory mat is inspected for the device and the bank by the designated address signals A-d and A_b (with error check).
  • case 4 only the row sub-block A-ru is inspected (with error check).
  • each address signal A-ru must be the same. The reason for this will be explained later.
  • FIG. 11 is a memory configuration diagram for explaining address error detection in case 1 of FIG.
  • address error detection is performed in case 1, what types of address errors can occur will be explained.
  • the test in case 1 above the test of the address signal A-c for selecting a bit line is omitted, and therefore, the wrong bit in the same word line WL0 in the same memory mat MA1 is output. It cannot detect errors writing to lines, for example, memory cells in BL2 instead of BL1.
  • the operation system 0S usually manages data in units called pages, and the size of one page is, for example, the size of memory cells connected to one pad line.
  • the system will not go down due to localized damage alone. That is, as shown in FIG. 11, for example, a fragment of process A exists on a plurality of word lines in page units. The same goes for the fragment of process B.
  • a fragment of file A loaded from a mass hard disk storage device is present on multiple word lines in page units. In such a state, for example, even if the data in the word line WL0 is destroyed, the processing can be continued only by terminating the process A.
  • an error occurs that destroys the data in other process areas, especially if this is a power area. It leads to system down.
  • the operation system IIS manages an illegal address access, but cannot deal with a hardware address error occurring in a semiconductor memory.
  • FIG. 12 is a memory configuration diagram for explaining address error detection in case 4 of FIG.
  • address error detection is performed in case 4, what kind of address error can occur is shown. Inspection in case 4 only guarantees that the write destination is in the sub-block, for example SB1. For example, if applications 1 to 3 are managed to use only sub-blocks SB 1 to SB 3 and operation system ⁇ S area, respectively, only sub-block SB 4 is used. If only 1 is completed, the processing can be continued.
  • the number of target addresses for performing error detection can be reduced. be able to.
  • the target address by determining the target address according to the data management method, it is possible to reduce the probability of an error leading to a system down. That is, according to the second embodiment of the present invention, a high-speed and highly reliable semiconductor memory can be realized.
  • FIG. 13 is a schematic waveform diagram for explaining an example of the operation of the semiconductor memory according to the present invention.
  • the semiconductor memory shown in the figure is particularly limited. It is not intended for the addressless method.
  • a row-related activation command (act) and a port address signal (R1) are input, and at time t3, a column-related address signal C1 and a write command are given.
  • a write data 1 is also given.
  • the address signal R1 given in the command of the above act is A-ru1, A-r11, A-d1, A-b1.
  • the address C1 given in the write command is A—c1, A—d1, and A—b1.
  • the reception error of the address signal R1 is detected by comparing the addresses taken twice at the times t1 and t1a.
  • the operation of the row-based activation device itself starts from the time t1.
  • the address signal is fetched again at the delayed time t1a.
  • the address signal itself sent from the host side is affected by noise and becomes low level.
  • an error in the address signal such that the signal to be received is determined to be at the high level can be detected.
  • the memory access in an environment where noise is present is stopped, the master device is notified of this, and the memory access is prompted again.
  • a latch circuit for holding an address signal input to the error detection circuit ED with a time difference and a circuit for determining a comparison match are provided.
  • the latch circuit may use a latch circuit provided in the address buffer AB in combination.
  • FIG. 14 is a schematic waveform diagram for explaining another example of the operation of the semiconductor memory according to the present invention.
  • This embodiment is the same as the embodiment of FIG. 13 except that the reception error of the endless signal R1 is detected at times t1 and t2.
  • the time t 1 a at which the second address signal is fetched is close to the time t 1 and is a time generated by the delay circuit inside the semiconductor memory.
  • t 2 is Generated at the falling and rising edges of the lock. That is, time t2 is 1 clock or one clock away from time t1.
  • FIGS. 13 and 14 a method of detecting an address reception error by comparing addresses taken twice is shown in accordance with the second embodiment, but is not limited thereto. However, it is also applicable to the case where error detection is performed for all addresses. More specifically, as described above, effects can be obtained when applied to the row system of the DRAM or when combined with the first embodiment.
  • FIG. 15 is a schematic waveform diagram for explaining still another example of the operation of the semiconductor memory according to the present invention.
  • an address to be inspected is sent twice, an act command and a write command, and an error is detected by comparing the two. This is effective when applied to case 4 of the second embodiment of the present invention.
  • Both the row address R 1 and the column address C 1 include an address A—rul, which is compared for error detection. As a result, the reception error can be detected without adding the address check information on the master device side.
  • FIG. 15 shows a case where two memory mats (A-dl, A-b1) and (A-d2, A-b2) are simultaneously activated. At this time, an example is shown in which the row address R2 of the second act command also includes the address A-ru1.
  • FIG. 16 is a schematic configuration diagram of an embodiment of the error detection circuit according to the present invention.
  • a register (REG Ai) 191 for variably setting the range of some addresses to be inspected is included.
  • the value of the register 191 is logic 1, for example, the result of decoding the address signals A0 and A1 is inspected.
  • a reception error of the address signals A0 to A7 is detected.
  • the logic 1 and 1 logic 1 and 0 states of this register are set externally. Make it configurable.
  • the inspection range can be changed according to the purpose, such as whether to decrease the address inspection area and inspect the value after decoding instead, or increase the address inspection area and inspect the value immediately after reception. Similarly, it may be possible to change whether to check all write addresses / write commands or only a part of them according to the register state. Alternatively, it may be possible to change whether the write address / write command is checked or not.
  • FIG. 17 is a block diagram showing another embodiment of the semiconductor memory according to the present invention. This embodiment is an example of a circuit configuration corresponding to FIG.
  • the read / write memory cell is connected to a sub input / output circuit (sub 10) 132a via a Y switch (YSW) 133a.
  • FIG. 18 shows the operation of another embodiment of the semiconductor memory according to the present invention.
  • a waveform diagram for explanation is shown.
  • the outline of the write operation according to the third embodiment is shown.
  • the write address A i and the write command (write command) are given to the semiconductor memory prior to the write data 1, that is, earlier in time.
  • At least one of an address and a command error detection operation is started before receiving write data. That is, the error detection signal er of the address / command (A i / C md) transitions to the high level at the time te 1 earlier than the reception of the data 1 and immediately after the reception time t 1 of the data 1. At time te, the high level / low level of the write enable signal we-m is determined.
  • the method shown in the embodiment of FIG. 14 in which the reception error detection of the acknowledgment address signal R1 is performed by comparing the addresses captured at one time is effective. is there. That is, the second comparison address capture and error detection can be concealed during the period from the reception of the write command and address to the reception of the write data, while the decoding of the address and command is performed after the first reception of the address. Since it starts, there is no deterioration in the write operation speed. Also, the master device adds address check information. You don't have to.
  • FIG. 19 is a block diagram showing still another embodiment of the semiconductor memory according to the present invention.
  • This embodiment is an example in which the third embodiment is applied to a high-speed SRAM.
  • a write method called late write (Late Write) is applied in addition to the write data delay for the write command described in FIG.
  • the write address Ai is taken into the write address register (WAR 0) 24 1 at the timing generated by the input circuit 23, whereas the write data at the terminals DQ0 to DQ17 is Two evenings Imaging register evening (WREG0) 26 1, Write buffer (WBF 1) 271, (WBF 0) 272 at timing generated by (WREG 1) 262, that is, one clock delay from address Ai It is captured.
  • the address of the write address register (WAR 0) 24 1 and the data of the write buffer (WBF 0) 272 are written at the timing of the next write command.
  • the data is sent to the address register (WAR 1) 242 and the write buffer (WBF 1) 271 and the actual writing to the memory cell is started.
  • the write mask information supplied from the outside passes through the mask registers (MR 0) 2 51 and (MR 1) 2 52 similarly to the write address.
  • the address error detection operation is started by the circuit 22 before the write data is received, as described above.
  • Fig. 19 has the following additional features. That is, although information for determining an address / write command error is given as DQ 17 data at a timing one clock delayed from the address, the circuit 22 determines the number of information of the logical 1 of the address at the time of receiving the address. Check by XOR (exclusive OR) circuit Start. Based on the even or odd result of the number of logical 1 information at this address, an address error can be detected immediately after receiving the DQ 17 test information delayed by one clock.
  • An error in the write command indicates that the detection information at terminal DQ17 is the same even or odd as the number of information of logic 1 of the write address.For example, if the number of information of logic 1 is even, it is set to logic 0 and Is detected by the complementary even or odd, for example, logic 1 if the number of information is an even number and set to logic 0. Therefore, the terminal DQ17 is inverted and written to the memory cell as shown in FIG.
  • the address / command error detection result er is output from the circuit 22.
  • the mask register (MR 1) is output even if no external write mask is specified.
  • the information of 2 52 becomes logic 1.
  • the error detection signal we-m generated by the circuit 22 keeps the input level to prevent writing to the memory cell, and notifies the master device that the signal WRH has not been written. .
  • FIG. 20 is a waveform chart for explaining an example of the operation of the semiconductor memory of FIG.
  • the write enable signal we-m to the memory cell is generated by the circuit 21 in accordance with the high / low state of the error detection signal er, and only when the signal we-m is at the high level is the signal to the memory mat MA A write operation is performed.
  • the address error detection operation is started before the write data is received.
  • a high-speed and highly reliable semiconductor memory is provided. The effect is obtained. Also, since the data is given later in time than the address / command, the address / command check information for the master device is given. There is also obtained an effect that there is enough time to generate a report.
  • the structure of the late write system is used, but it is not always necessary to use the late write system.
  • the terminals DQO-DQ15 are used for data
  • the terminal DQ16 is used for data check information (parity information)
  • the terminal DQ17 is used for address / command detection information.
  • the present invention is not limited to these.
  • FIG. 21 is an operation explanatory diagram for explaining the operation of a semiconductor memory to which the present invention is not applied.
  • This figure shows a simplified time lapse when a write operation with address error detection similar to that of the semiconductor memory according to the present application is performed.
  • the master device sends a write address.
  • the semiconductor memory wants to take in the address as early as possible, but it is necessary to determine the reception timing in anticipation of variations in arrival times due to environmental fluctuations and the like.
  • address error detection starts. Wait for the result of this address error detection, and if no error is found, start the write operation.
  • FIG. 22 is an operation diagram for explaining the operation of the semiconductor memory to which the present invention is applied.
  • This figure shows another aspect of the first to third embodiments as compared with FIG. 21.
  • FIG. 19 simplifies the time lapse of the write operation accompanied by the address error detection as in FIG.
  • the address error detection and the first half of the write operation can be performed simultaneously and in parallel. Thus, high reliability can be achieved without impairing the high-speed writing operation.
  • the address is acquired twice at different times and By combining the method of detecting an address error by comparing with any one of the above-described first to third embodiments, terminals DQ 16 and DQ 17 as shown in FIG. High reliability can be realized without adding extra address check information and without impairing high speed.
  • To realize a highly reliable semiconductor memory it is necessary to detect not only an error in an address signal but also an error in a command. For example, if a read command is misinterpreted as a write command, an illegal write to the memory cell is performed, causing irreversible corruption of the stored information.
  • FIG. 23 is a command map of one embodiment of the semiconductor memory according to the present invention.
  • a certain feature is given to a bit pattern constituting the command. That is, the figure also shows the fourth embodiment of the semiconductor memory according to the present invention.
  • the command is interpreted by decoding, for example, four control signals (information bits) cmd0 to cmd3.
  • control signals cmd0 to cmd3 By using the 4-bit signals cmd0 to cmd3 in this way, up to 16 commands can be set.
  • the command is set so that even if one control signal is erroneously received, it does not become another command. Is devised to be assigned.
  • a write command (WR) is assumed when all the bits cmd0 to cmd3 are logic 0. If there is only one logical one, it is a command that does not correspond to any command. Of the 16 types, the remaining 11 types except for the above 5 types are assigned to other commands. With such a configuration, two or more signals must be logic 1 for commands other than write.
  • the probability that a command other than a write, for example, a read command, is erroneously interpreted as a write command can be extremely small, that is, both logical 1s are logical 0s. The probability of being misrepresented is greatly reduced, resulting in a highly reliable semiconductor memory.
  • command information can be transmitted effectively with fewer terminals or signal lines as compared with a case where command inspection information is separately added.
  • 16 (2 to the fourth power) combinations of signals minus four no-commands (combinations in which one is a logical 1) is 1 2
  • signals cmd 0 to cmd 2 are used as command information
  • the remaining signal cmd 3 is used as command check information (parity bit). Only commands can be transmitted.
  • the check by the check circuit is performed as in the case where the command check information (parity bit) is added. There is no signal delay caused by time, and there is no loss of high speed.
  • FIG. 24 is a circuit diagram of one embodiment of the command error detection circuit according to the present invention. If the command is a no-command due to a decoding operation in a logic circuit receiving the signals cmd0 to cmd3, the command error detection signal e-cmd # goes low. The signal WRH generated in combination with the address error detection signal e-ad notifies the master device that the write operation has not been performed due to, for example, erroneous reception of the write command.
  • FIG. 25 is a waveform chart for explaining still another example of the operation of the semiconductor memory according to the present invention.
  • This embodiment is directed to a case where a dedicated pin for a write inhibit notification signal WHR is provided as in the semiconductor memories of FIGS. 1 and 17.
  • WHR write inhibit notification signal
  • the signal WR H is set to low level when an error is detected and a write of data 2 is performed for the write operation of data 2 without error detection, and an error is detected.
  • a write operation is not performed (no write), it is set to high level.
  • the presence / absence of the WRH can be specified by the above-mentioned command, and a register for controlling the enable / disable of the WRH is provided in the semiconductor memory of the present invention, though not shown, although not shown.
  • a register for controlling the enable / disable of the WRH is provided in the semiconductor memory of the present invention, though not shown, although not shown.
  • by setting the register state externally it may be possible to set whether or not to return a WRH signal in response to a write command.
  • FIG. 26 is a waveform chart for explaining still another example of the operation of the semiconductor memory according to the present invention.
  • This embodiment is directed to a case where a dedicated pin for the write inhibit notification signal WHR is not provided as in the semiconductor memories of FIGS. 1 and 17.
  • the signal WRH is transmitted using the data bus DQ0.
  • the master device is connected to terminal DQ 0
  • the output circuit may be set to the output high impedance state after the output of data 4 so that the high level / low level from the DQ 0 pin sent from the semiconductor memory receives (WR H).
  • FIG. 27 is a block diagram showing another embodiment of the system using the semiconductor memory according to the present invention. This embodiment is directed to a case where a dedicated pin for a write inhibit notification signal WHR is not provided unlike a semiconductor memory. In this embodiment, the signal WRH is transmitted through a timing signal line.
  • the memory controller 3 connected to the central processing unit and the semiconductor memory 1 of the present invention have two timings in addition to the transmission line for the address / command (A i, C md) and data DQ.
  • the signal TMC is connected to the signal line of TMM.
  • the signal TMC is a timing for the semiconductor memory 1 to capture a signal sent from the master device to the semiconductor memory 1 side.
  • the signal TMM is timing for the master device to capture a signal sent from the semiconductor memory 1 to the master device.
  • the signal WRH can be transmitted using the signal line of the signal TMM.
  • FIG. 28 is a waveform chart for explaining an example of the operation of the system shown in FIG. 27.
  • a write address / command (write) and write data 1 are received at a timing synchronized with the signal TMC, and the signal WRH is transmitted to the master device using the signal line of the signal TMM.
  • FIG. 29 is a waveform chart for explaining another example of the operation of the system shown in FIG. 27 ⁇ .
  • the read address / command (read) is received at the timing synchronized with the signal TMC, and the read data 1 is transmitted to the master device at the timing synchronized with the signal TMM. Send.
  • FIG. 30 is a waveform chart for explaining still another example of the operation of the semiconductor memory according to the present invention. This embodiment is directed to a write operation in a case where the present embodiment is applied to a DDRSDMA and the above-described embodiments are combined.
  • the address R1 of the row system activation command ACT is captured twice at the rising and falling edges of the clock, and these are compared to generate the input address error detection signal er_R1. This operation is the same as in FIG.
  • the first data of D is temporarily stopped in the write buffer, and after confirming that there is no address / command error from the signals er-1 R1 and er-C1, the data from the write buffer to the memory cell To form a write data path. This operation is the same as in FIG.
  • a highly reliable and high-speed semiconductor memory capable of detecting a write error without deteriorating the write operation speed.
  • a semiconductor device according to the present invention in which means for detecting an error in a write address and a write command, preventing data from being written to an invalid memory cell, and notifying a master device that writing has not been performed is provided on-chip.
  • the body memory a highly reliable and high-speed semiconductor memory capable of detecting a write error without deteriorating the write operation speed can be realized.
  • the invention made by the present inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and departs from the gist of the invention. Needless to say, various changes can be made within the range that does not exist.
  • a specific circuit for detecting an error such as an address signal using a parity bit, or a specific circuit for receiving an address signal command two or more times and comparing them to detect an error is described in various embodiments. Can be taken.
  • the semiconductor memory to which the present invention is applied is, in addition to the above-mentioned DRAM and SRAM, a ferroelectric memory capable of maintaining stored information even when the power is cut off, or a device that stores electric charge in a floating gate. It may be a non-volatile memory (flash memory) that holds information.
  • the semiconductor integrated circuit device receives a device address in addition to the memory and, when recognizing that the device itself has been selected, receives input data or various signals or performs a certain operation such as outputting a result of the operation.
  • the present invention can be similarly applied to various semiconductor integrated circuit devices constituting peripheral circuits of a digital signal processing system such as a microcomputer. Industrial applicability
  • the present invention is not limited to a semiconductor integrated circuit device which receives address signals and commands, receives write data, and outputs read data as in a semiconductor memory. It can be widely used for various semiconductor integrated circuit devices that operate in response to data or control signals.

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Abstract

L'invention porte sur un dispositif de circuit intégré à semi-conducteur doté d'un dispositif permettant de détecter une erreur d'au moins une adresse d'écriture ou d'une commande d'écriture, tout en effectuant simultanément et parallèlement une opération d'écriture. Selon le résultat de détection, le dispositif empêche que les données ne soient écrites dans une mauvaise cellule de mémoire, et informe un dispositif principal que l'opération d'écriture n'a pas été effectuée.
PCT/JP2002/001659 2002-02-25 2002-02-25 Dispositif de circuit integre a semi-conducteur WO2003071550A1 (fr)

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JP2003570360A JPWO2003071550A1 (ja) 2002-02-25 2002-02-25 半導体集積回路装置
PCT/JP2002/001659 WO2003071550A1 (fr) 2002-02-25 2002-02-25 Dispositif de circuit integre a semi-conducteur

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101178562B1 (ko) * 2010-11-02 2012-09-03 에스케이하이닉스 주식회사 커맨드 제어회로 및 이를 포함하는 반도체 메모리 장치 및 커맨드 제어방법

Citations (5)

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Publication number Priority date Publication date Assignee Title
JPS5211829A (en) * 1975-07-18 1977-01-29 Hitachi Ltd Memory control unit
JPH0397747U (fr) * 1990-01-22 1991-10-08
JPH11296391A (ja) * 1998-04-09 1999-10-29 Sony Corp 半導体記憶装置
JP2000195253A (ja) * 1998-12-25 2000-07-14 Internatl Business Mach Corp <Ibm> Ｄｒａｍ及びｄｒａｍのデ―タ・アクセス方法
JP2002015580A (ja) * 2000-06-29 2002-01-18 Toshiba Corp 半導体集積回路

Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
JPS5211829A (en) * 1975-07-18 1977-01-29 Hitachi Ltd Memory control unit
JPH0397747U (fr) * 1990-01-22 1991-10-08
JPH11296391A (ja) * 1998-04-09 1999-10-29 Sony Corp 半導体記憶装置
JP2000195253A (ja) * 1998-12-25 2000-07-14 Internatl Business Mach Corp <Ibm> Ｄｒａｍ及びｄｒａｍのデ―タ・アクセス方法
JP2002015580A (ja) * 2000-06-29 2002-01-18 Toshiba Corp 半導体集積回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101178562B1 (ko) * 2010-11-02 2012-09-03 에스케이하이닉스 주식회사 커맨드 제어회로 및 이를 포함하는 반도체 메모리 장치 및 커맨드 제어방법
US8566685B2 (en) 2010-11-02 2013-10-22 Hynix Semiconductor Inc. Command control circuit, integrated circuit having the same, and command control method

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