WO2003056541A1 - Systeme de commande de circuit d'attaque d'affichage - Google Patents

Systeme de commande de circuit d'attaque d'affichage Download PDF

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Publication number
WO2003056541A1
WO2003056541A1 PCT/JP2001/011549 JP0111549W WO03056541A1 WO 2003056541 A1 WO2003056541 A1 WO 2003056541A1 JP 0111549 W JP0111549 W JP 0111549W WO 03056541 A1 WO03056541 A1 WO 03056541A1
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WO
WIPO (PCT)
Prior art keywords
memory
image
interface
image data
data
Prior art date
Application number
PCT/JP2001/011549
Other languages
English (en)
Japanese (ja)
Inventor
Goro Sakamaki
Takashi Ooyama
Sigeru Oota
Kei Tanabe
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to JP2003556980A priority Critical patent/JPWO2003056541A1/ja
Priority to PCT/JP2001/011549 priority patent/WO2003056541A1/fr
Publication of WO2003056541A1 publication Critical patent/WO2003056541A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0261—Improving the quality of display appearance in the context of movement of objects on the screen or movement of the observer relative to the screen

Definitions

  • the present invention relates to a control technique for controlling the picture ⁇ mode of the 3 ⁇ 4 ⁇ device, and in particular, a still image or a moving picture on a liquid crystal device, an organic EL ⁇ :
  • the present invention relates to a guidance control system that controls an image mode of a recording device to be recorded.
  • a liquid crystal / display device an organic EL device, a plasma device, or a release / release device is known as this type of device.
  • the liquid crystal display device which is a typical example of a liquid crystal device, and the liquid crystal display device using the liquid crystal device as an example, will be described using the liquid crystal display device as an example.
  • a motion picture (hereinafter, also simply referred to as a motion picture) has been written on a near tongue machine. Since the purpose of the «electronic tongue machine is to mainly play still images (hereinafter also referred to simply as still images) including text, its sound control circuit is a still image ⁇ Text ⁇ System ⁇ I ⁇ ⁇ Has only one interface, does not have a built-in video interface. Therefore, it is difficult to perform 3 ⁇ 4 ⁇ of moving images that can be smoothed by a small-sized coma control circuit.
  • Fig. 21 is a block diagram of a ⁇ ⁇ circuit of t ⁇ ⁇ ⁇ si tongue machine having a motion picture-compatible interface, which is a 3 ⁇ 4 3 ⁇ 4 »control circuit and 3 ⁇ 4 / display device examined by the inventor before the present invention. It is a block diagram explaining ⁇ !.
  • the horseshoe control circuit system 1 includes an audio interface (AU I) 2, a high frequency interface (HFI) 3, an image processor 4', a memory 5 and a liquid crystal controller 1 which is a display horse control circuit.
  • Reference ⁇ 9 is microphone microphone (M / C), 10 is speaker (S / P), 12 is antenna (ANT), and 13 is liquid crystal panel (liquid crystal display: LCD).
  • the image processor 4 comprises a digital signal processor (DSP) 411 and a baseband processor 41 having an ASIC 412 and a microcomputer MPU.
  • the audio interface (AUI) 2 controls the ear of the audio input from the microphone 9 and the output of audio to the speaker 10.
  • LCD controller driver and (LCD-CDR) 6 works with the built-in clock in the driver. Therefore, the writing of image data and the operation are performed completely asynchronously.
  • Fig. 22 is a pictorial view showing an example of the motion of the movie in the system shown in Fig. 21.
  • Figure 22 shows a 3 ⁇ 43 ⁇ 4 picture of the ⁇ tongue machine, a still image
  • FIG. 23 is a block diagram for explaining a configuration example of a liquid crystal controller driver and its peripheral circuits in the system shown in FIG. LCD Controller ⁇ Dryo
  • LCD-CDR 6 6 indicates a write address circuit 61, a recording address circuit 62, and a bit map composed of RAM ⁇ memory (memory 3) ⁇ memory (M) 63, liquid crystal, gate circuit (DR) 64, built-in clock A generation circuit (CLK) 65 is provided.
  • the data (DB1 7-0) from the image processor 4, baseband processor 41 is written from the system interface (SSZIF) 7 to the built-in memory M.
  • the write address at this time is the write address circuit (SAG) 61 of the system 'interface signal CS (chip select), RS (register select) WR (write) ⁇
  • SAG write address circuit
  • CS chip select
  • RS register select
  • WR write
  • ⁇ The readout of the data of oscillation is read from the display memory (M) 63 in accordance with the address stored in the recording address band circuit (DAG) o 3 ⁇ 4 ⁇ address ⁇ 3 ⁇ 4 built-in clock 3 ⁇ 4 ⁇ circuit (CLK)
  • DAG recording address band circuit
  • DAG recording address band circuit
  • SSZIF system 'interface
  • FIG. 24 is a schematic diagram for explaining »of ⁇ 3 ⁇ 4 of a moving image in a drawing of a tongue tongue using a liquid crystal controller and dry screen of the system shown in FIG.
  • Readout line by display operation ( ⁇ spring: pixel selection line) LR is read out from the head by 1 ⁇ according to the built-in query.
  • System Inta-I-Hue The writing of display data from memory (SS / IF) 7 to the memory M is performed independently of the operation. For this reason, the write line by the system interface (SS / IF) 7 overtakes the read line LR by the action. That is, there are 3 ⁇ 4 ⁇ write line LW, 3 ⁇ 4 ⁇ read line LR and force 3 ⁇ 4 ⁇ ii ⁇ .
  • the object of the present invention is to reduce the power consumption by not having the flicker at the time of moving picture and squeezing the moving picture function of the quality, and to reduce the power consumption by using a dedicated control system.
  • the present invention uses a system interface in the still image mode as the second function and a movie interface interface as the first function in addition to the system interface in the still image mode, and the time period further required
  • a system interface in the still image mode as the second function
  • a movie interface interface as the first function in addition to the system interface in the still image mode
  • the IB3 ⁇ 4 device has at least one frame of image data storage area and a 3 ⁇ 4 / display control circuit for supplying 3 ⁇ 4 / display data to the display device.
  • 3 ⁇ 4 ⁇ Synchronized to movement and move 1 o'clock Let F 1 be M.
  • the editing control circuit has a vertical synchronization signal input of the moving image, and the editing ⁇ ⁇ : the transition of the writing and reading of the moving image 3 ⁇ 4 data to the memory. It is assumed that the control is based on the vertical sync signal which is preferred from the sleep sync signal input.
  • control circuit has an enable signal ⁇ that specifies an area in which the 1133 ⁇ 4 image is to be transferred to the device 3 ⁇ 4 ⁇ .
  • the thing is 3 ⁇ 4.
  • an in-one call signal specifying an area to which the still image in the area to display 3 ⁇ 4 of the so-called “3 still image” of the ⁇ 3 ⁇ device is specified.
  • M be human power.
  • the camera controller is connected to the image processor by the first means for writing the image data corresponding to the animation data into the memory. Make it special.
  • the ⁇ 33 ⁇ 43 ⁇ 43 ⁇ 4 ⁇ 4 control device is further coupled to a so-called image processor by a second function for writing Fujimi image data, which is regarded as still image data, into the recognition memory. Do.
  • the Ryukyu 1 function includes the vertical synchronization signal supplied from the picture processor to the male control circuit, and the i a 3 ⁇ 4 direct synchronization code has been written to the memory. ls Special feature is that it is used as a signal to indicate the readout table of the image signal. In (9) and (8), it is assumed that the ⁇ ⁇ 1 function further includes a horizontal synchronization signal and a dot clock.
  • the 53 ⁇ 4 slaughter control device has a first function for writing knitting image data corresponding to moving picture data into the knitting memory, and one self-image data considered to be still image data. It is assumed that it is combined with the knitting image processor by the second function to write to the image.
  • the edit ai function includes the vertical synchronization signal supplied from the image processor to the adjustment / indication control circuit, and the direct synchronization signal is transmitted to the adjustment memory. It is assumed that [i] is a signal to indicate the reading station of the written one's own image signal.
  • (1 2) including a recording panel and a memory for storing image data to be supplied to a so-called 5 ⁇ 4 ⁇ 3 ⁇ 4 panel, and providing the image data and timing to the editing panel.
  • the vertical sync signal is supplied from the image processor to indicate a signal for writing the image data corresponding to the moving image data into the memory. I will
  • ⁇ ⁇ control system of the present invention it is possible to display high quality moving images, and to display moving image interfaces and still image interfaces. Low power consumption can be achieved by switching according to the still image mode).
  • FIG. 1 is an explanatory view of the complete constitution of one difficult example of the present invention.
  • FIG. 2 is a schematic diagram illustrating ⁇ of »of the moving image of 3 ⁇ 4 ⁇ 4 ⁇ 4 of the portable Hi tongue using the configuration of an example of the horseshoe control system according to the present invention.
  • FIG. 3 shows the liquid crystal control according to the present invention. It is a block diagram explaining the circuit structure of a roller. Driver, and its related circuit.
  • Fig. 4 is a schematic diagram showing the motion of a moving image ⁇ ⁇ of a moving image of a crane tongue using a configuration of a difficult example of the 3 ⁇ 4 ⁇ ⁇ control system according to the present invention as an operation with a moving image. .
  • FIG. 1 is an explanatory view of the complete constitution of one difficult example of the present invention.
  • FIG. 2 is a schematic diagram illustrating ⁇ of »of the moving image of 3 ⁇ 4 ⁇ 4 ⁇ 4 of the portable Hi tongue using the configuration of an example of the horseshoe control system according to the
  • FIG. 5 is an explanatory view of the configuration and operation of a liquid crystal controller / driver without a moving image interface and a built-in memory for clarifying the effects of the example of the present invention.
  • Fig. 6 is a schematic diagram for explaining the appearance of a still image ⁇ by the liquid crystal con- trol roller and the driver in Fig. 5.
  • FIG. 7 is an explanatory view of the configuration and operation of a liquid crystal controller driver that performs data processing using a system interface and a built-in memory to explain the effect of the difficult example of the present invention.
  • FIG. 8 is an overhead view for explaining the still picture recording by the liquid crystal controller 'driver of FIG. 7; FIG.
  • FIG. 9 is an explanatory view of the merits and demerits of the configuration of the present invention, showing the configuration of FIG. 7 and the configuration of FIG.
  • FIG. 10 is an explanatory diagram of a circuit configuration of a driver chip in which the liquid crystal controller / driver of the present invention is embodied.
  • FIG. 11 is an explanatory view of the configuration and operation of an example of a liquid crystal controller and driver which has a system interface and an application interface and performs data by built-in memory.
  • FIG. 12 is a schematic diagram for explaining the freshness of the stationary j by the liquid crystal controller driver of FIG.
  • Fig. 13 is an explanatory view showing the switching operation of the system interface and the application interface in the form of a display.
  • FIG. 14 is an explanatory view of another example of the present invention.
  • FIG. 15 is a diagram for explaining the eaves of moving image data in the moving image buffering operation according to the circuit configuration of FIG.
  • FIG. 16 is a block diagram for explaining an example of a circuit configuration for implementing a moving image according to the present invention.
  • Fig. 17 is a pattern diagram for explaining the situation of the liquid crystal controller in Fig. 16. The situation of the first stop only to the selected area by the driver.
  • FIG. 18 is an explanatory view of moving image data of each data car 3 ⁇ 4 ⁇ for explaining the effect of the present invention.
  • FIG. 19 is an explanatory view of still another example of the present invention.
  • FIG. 20 is an explanatory view of still another example of the present invention.
  • Figure 21 is a part of the control system that has been studied by the present inventor before the present invention.
  • Fig. 22 is a block diagram illustrating " ⁇ . Fig. 22 is shown in Fig. 21
  • FIG. 11 is a schematic diagram showing an example of the operation of n ⁇ f at the
  • FIG. 23 is a block diagram for explaining an example configuration of the liquid crystal controller driver and its peripheral circuits in the system shown in FIG.
  • FIG. 24 is a diagram for explaining »of the moving image S ⁇ 1 in the drawing of the tongue-lifting machine using the liquid crystal controller / driver of the system shown in FIG.
  • FIG. 1 is an explanatory view of the whole configuration of the example of the present invention, and it is an interface for moving picture corresponding to the first function which is HI of the 3 ⁇ 4 ⁇ 4 ⁇ 4 control system according to the present invention.
  • FIG. 8 is a block diagram for explaining an example of the configuration of a Zeon Yu Tong machine having a moving picture (including a first port to be processed).
  • An audio interface (AUI) 2 similar to that shown in FIG. 20, a high-frequency interface (HFI) 3, an image processor 4 which is an image data processing unit, and a memory 5 are memories.
  • AMI audio interface
  • HFI high-frequency interface
  • image processor 4 which is an image data processing unit
  • memory 5 are memories.
  • the memory 5 is a frame memory (bit map memory) for storing at least one image frame worth of image data (bit map memory), and in the following description, the graphic RAM is also referred to.
  • ⁇ System ⁇ I / 0 bus ⁇ Interface (SSZIF) 7 is also described as System interface 7 or Movie interface.
  • the baseband processor 41 which has a digital signal 'processor (DSP) 411 and an ASIC 412 and a microcomputer MPU in the image processor 4, a video processing processor (MPEG) 421 and a liquid crystal 3 ⁇ 4 ⁇ control It has an application processor (APP) 42 which has a speaker (LCDC) 422.
  • Reference numeral 9 denotes a microphone (MZC 9 and 10 a speaker (S / P), 11 a video camera (CZM), 12 an antenna (ANT), and 13 a liquid crystal panel (liquid crystal display: L CD)
  • AS IC 412 is the other ⁇ Telephone system configuration ⁇ Has necessary peripheral circuit functions.
  • the image processor 4 may be formed of a single silicon substrate such as silicon (a silicon substrate may be formed into a chip), and each of the base processor 41 and the application processor 42 may have one silicon substrate. (It may be formed in a tip force.
  • FIG. 2 is a schematic view for explaining the freshness of a moving image ⁇ ® in display translation of a mobile phone using an example of the display control system according to the present invention.
  • the ⁇ operation is performed by the sync signal sync sync signal V SYNC, the horizontal sync H SYNC, the dot clock DOTCLK required for the operation, and the 3 ⁇ 4 ⁇ data is synchronized to the 3 ⁇ 4 ⁇ operation.
  • 6 memory (internal RAM: M) Write to 5 As a result, 13 ⁇ 4 from ⁇ 3 ⁇ 4 in (a) of FIG. 2 to ⁇ 3 ⁇ 4 in (b) is performed from the beginning of the ⁇ , and switching from 1M does not occur.
  • FIG. 3 is a block diagram for explaining the circuit configuration of the liquid crystal controller and driver according to the present invention and related circuits.
  • LCD-CDR liquid crystal controller and driver
  • SAG serial address generation circuit
  • DAG display address ⁇ circuit
  • M 3 ⁇ 4 ⁇ memory
  • DR liquid crystal dedicated circuit
  • the readout of the new data is read from the built-in memory (M) 63 and applied to the liquid crystal display (DR) 64 in accordance with the address D A read from the video data signal.
  • M built-in memory
  • DR liquid crystal display
  • FIG. 4 is a diagram for explaining the action of the moving picture in the drawing ⁇ of the ⁇ tongue machine using the difficult example of the 3 ⁇ 43 ⁇ 43 ⁇ 4 ⁇ control system of the present invention as the working of the moving picture interface.
  • Writing of recording and recording from the system 'interface (SSZIF) 7 is written to 3 ⁇ 4 ⁇ memory (M) 63 according to the dot clock DOTCLK from the video interface (MP / IF) 8 in FIG.
  • SSZIF system 'interface
  • M 3 ⁇ 4 ⁇ memory
  • Fig. 4 (a) indicates the data read line
  • LW indicates the data write line
  • LEND in (C) of Fig. 4 indicates a winter winter line.
  • the time t 0 indicates the start point of the surface final line 3 ⁇ 4 ⁇ , and the time t 0 indicates the start of the surface final line 3 ⁇ 4 ⁇ .
  • FIG. 5 shows the configuration and operation of the liquid crystal controller ⁇ driver without the moving image interface and the built-in memory for comparing and comparing the effects of the example of the present invention.
  • FIG. 6 is a schematic view for explaining the state of still image display by the liquid crystal controller driver of FIG.
  • the liquid crystal controller 'DR LCD' has a line memory (LM) 63 as a memory M.
  • LM line memory
  • FIG. 7 is an explanatory view of the configuration of the liquid crystal controller driver for performing data by the system interface and the built-in memory to clarify the effect of the embodiment of the present invention and the operation thereof.
  • FIG. 8 is a view for explaining the state of a still picture by the liquid crystal controller / driver shown in FIG.
  • a bit map memory (M) 63 which is a RAM memory similar to that of FIG. 3, is incorporated as a built-in memory ( ⁇ ) 63 as a memory.
  • FIG. 9 is an explanatory view of the merits and demerits of the configuration of FIG. 7 and the configuration of FIG. 5 and the configuration of FIG. 5 with J ⁇ K.
  • the configuration 1 shown in FIG. 9 that is, only the system interface and the 3 ⁇ 4 ⁇ memory (RAM)
  • the built-in memory (RAM) enables the still image 3 ⁇ 4 ⁇ mode and the movie 3 ⁇ 4 ⁇ mode.
  • FIG. 2 to FIG. 23 in FIG. 2 to FIG. In the configuration of 2 in FIG. 9, that is, the configuration with the video interface and the line memory, it always requires the data ⁇ including the still image 3 ⁇ 4 which can be flicker free.
  • the built-in memory and moving picture interface shown in FIG. 9 3 are provided, and still picture mode and moving picture mode are switched. According to the configuration of the example, it is possible to use a video server that has no flickering, and it is possible to reduce the power consumption with a minimum of data car.
  • FIG. 10 is an explanatory diagram of a circuit configuration of a driver chip, which is a specific example of the liquid crystal controller 'driver' which constitutes the control system of the present invention.
  • the still image data to this drive 600, text data, etc. are written to baseband.processor 4 1 to the system interface 6 0 1 Internal address counter (AC) Memory indicated by address 6 0 6 That is, it is written as data to graphic RAM (GRAM) 610.
  • the recording operation is as follows. That is, internal black?
  • the timing circuit 6 2 2 generates the timing and display address necessary for the clock / production based on the clock signal that was generated by the clock ⁇ ⁇ circuit (C P G) 630.
  • the graphic RAM (GRAM) 610 in 3 ⁇ 4 ⁇ address reads out the 3 ⁇ 4 ⁇ data, and the liquid crystal, which is necessary for the liquid crystal display. Send to Nell.
  • the operation mode switching register (DM) 6 2 1 RAM access switching register (RM) 605 is used to switch between movie recording mode and still picture mode.
  • motion picture data (PD 1 7-0), vertical sync signal VSYNC, soft sync synch No. HS Y N C, dot clock DCLK, data enable signal E NA BLE application processor 4 Enter two forces, the external recording system-6200.
  • the operation of the address counter (AC) 606 is switched to the dot clock DCL :, de-enablement (a signal from ENABLE) by the RAM access switching register (RM) 605, and graphic RAM.
  • GRAM Switch the data bus to 1 6 0 to (data (PD 1 7-0)
  • the motion / RAM access operation is performed using the system interface 6 0 1 and the internal clock «circuit (CPG) Switched from 630 to the external display interface module 620 that is an animation interface.
  • reference 602 is a gate driver 'interface (serial)
  • 603 is an index register (IR)
  • 640 is a control register (CR) (CR)
  • 6 0 7 is a bi-perpendation circuit that performs processing on a bit basis
  • 6 0 8 is a read (read) read out circuit
  • 6 0 9 is a write (write) read out circuit.
  • reference numerals 6 2 3 6 4 2 6 6 6 6 are latch circuits
  • 6 2 5 are AC circuits
  • 6 2 s 7 are slaughter circuits, and so on.
  • 640 is a gamma (y) adjustment circuit
  • 650 is a P all adjustment ⁇ ⁇ circuit, which constitutes a data processing circuit to the liquid crystal panel. Note that since the bit operation! 0-7 is a unit that performs bit-based operation processing and bit-based reordering operation, the: function not required is omitted.
  • Table 1 shows the mode ⁇ I state of the RA1V [access switching register (RM) 6 0 5 described in FIG. 10]. In Table 1, this register is referred to as a RAM access mode register. Table 1
  • Table 2 also describes ⁇ operation switching register (DM) 6 0 described in Figure 10.
  • Table 3 shows RAM access switching register (RM) and display operation switching
  • the RAM access switching register (RM) has a built-in table.
  • the ⁇ operation switching register (DM register) shown in Table 2 is a 2-bit 13 ⁇ 43 ⁇ 4 switch, and switches the ⁇ operation mode. This DM register's status is described in "DM status".
  • FIG. 11 is an illustration of the configuration and operation of the liquid crystal controller with a built-in memory and a data controller with a built-in memory with the system interface and interface.
  • FIG. 12 is a schematic view for explaining 1 1 of still images shown by the liquid crystal controller driver of FIG.
  • the system interface (baseband interface) 4 1 for inputting still image data etc.
  • the application interface-interface 4 2 for moving image interface 3 ⁇ 4 ⁇
  • Vertical sync signal VS YN C is a timing signal that indicates the ⁇ start of the »operation
  • the sync signal H SYNC is a timing signal indicating the line cycle of operation
  • ⁇ dot clock D 0 TCLK is a clock in pixel units, and becomes a clock for 3 ⁇ 4 ⁇ operation by the image interface or application 'interface (APP) 42 .
  • This dot clock DOTCLK also serves as a write signal for 3 ⁇ 4 ⁇ memory (M) 63. Data is synchronized with this dot clock DOTCLK to perform image data.
  • the enable signal ENABLE is a signal that indicates that each pixel data is available. This enable signal is written to memory (M) 63 only when the enable signal is enabled.
  • FIG. 13 is an explanatory view showing the switching operation of the system interface and the application interface in a state of 3 ⁇ 43 ⁇ 43 ⁇ 43 ⁇ 4.
  • the time to do the movie 3 ⁇ 4 ⁇ should be less from the time to do the movie 3 ⁇ 4 ⁇ on the crane ⁇ . For this reason, when the number of still images occupying a large number of times, the system operates with low power due to "system interface face + internal face ⁇ ".
  • each register (RM, DM) is switched as activated to enable the application 'interface (movie interface). This will minimize the period of time to use the data power interface and reduce the power consumption of the entire system.
  • the system of this system is edible only from the system interface. You may choose to perform instruction I ⁇ via IJ.
  • FIG. 14 is an explanatory diagram of another embodiment of the present invention, and is a block diagram for explaining a circuit configuration for performing the motion picture information-flickering operation.
  • t Bm 5 explained in Fig. 6 and Fig. 6
  • a movie during (application 'interface ⁇ ) is ⁇ data in the line memory Exiled ⁇ 1 with the accommodated ⁇ cracking. Therefore, it is necessary to keep the »schedule constant.
  • Fig.15 shows the video data in the video buffering operation by the circuit configuration of Fig.14.
  • the data ⁇ il must be conducted over the same period of four frames, so «3 ⁇ 4 Force goes down.
  • moving image buffering is used to store all moving image data in the built-in RAM memory
  • data is only output when U®'s data is recorded, and the recorded data in the built-in memory is fffed.
  • the data stored in the memory is read out and recorded without data 3 ⁇ 4 t from the system side.
  • the number of motion picture data is reduced to 1 ⁇ 4 of the motion picture frame of the above example at 15 frames per second and a frame frequency of 6 0 Hz.
  • the present invention is applicable only to the selected area of the moving picture data 3 ⁇ 4 ⁇ area when the moving picture display area MP DA is inserted into the RAM data 3 ⁇ 4 ⁇ area (still picture 3 ⁇ 4 ⁇ area) SSDA as described above. It is also possible to drive 13 ⁇ 43 ⁇ 4 ⁇ data.
  • FIG. 16 is a block diagram for explaining a difficult example of the circuit configuration for obtaining the animation according to the present invention. It is a lock figure.
  • FIG. 17 is a schematic view for explaining »of still image display only on the selected area by the liquid crystal controller driver shown in FIG.
  • the moving picture area including the still image of MPDAJ2W and the constant area from SDA always include data from the moving picture interface. Because of this, the data vehicle will lose power, and the power will increase. In the selected fiber of this difficult example, the data from the movie interface will be ⁇ Area Only recorded data of MPDA can be ⁇ .
  • still image data is written to the memory and placed in the memory, and the motion image data, such as 3 ⁇ 4 ⁇ data, is written only to the part of the memory instructed by the ENABL ⁇ signal.
  • the still image and the moving image are combined on the 3 ⁇ 4 ⁇ memory, and simultaneously read out to the 3 ⁇ 4 ⁇ pB temple to be performed on the liquid crystal panel 13.
  • h is not limited to :: device of crane 3 ⁇ 4 ⁇ 3 ⁇ 4 machine, but also applies to large-sized display devices such as basin controls, display monitors, etc.
  • FIG. 18 is a Jti 3 clear view of moving picture data ⁇ 43 ⁇ 4 ⁇ 4 of each data for explaining the effect of the present invention.
  • FIG. 18 shows a liquid crystal panel size of 176 ⁇ 2 40 dots, a moving picture size of QC IF size (144 ⁇ 176 dots), a moving picture frame number of 15 frames per second (fps), and a frame frequency of 60 Hz with 3 ⁇ 4 ⁇
  • the comparison is As can be seen from FIG.
  • the data is (b) reduced by approximately 25% against (a) movie buffer only 3 ⁇ 4 ⁇ , (c) movie bulletin selection area 3 ⁇ 43 ⁇ 43 ⁇ 43 ⁇ 4 (a) )
  • ⁇ A reduction of about 15% is possible.
  • FIG. 19 is an explanatory view of still another example of the present invention, and is a schematic diagram for explaining the 3 ⁇ 4 ⁇ rewriting of the still image region in the moving image 1.
  • the liquid crystal controller driver according to the present invention switches between still image interface and moving image interface with a register, and in FIG. It is possible to make it possible to do the motion picture buffering as described, and also to rewrite the still picture area in the motion picture.
  • Rewrite of recording data by ⁇ ⁇ ⁇ is ⁇ 2 4 ⁇ ⁇ 4 ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇
  • FIG. 20 is an explanatory view of still another example of the present invention, and is a block diagram for explaining an example of the configuration of the liquid crystal controller driver and its peripheral circuits in the system.
  • the application processor 42 is uttered to the configuration shown in FIG. Then, from the application processor 42, the ⁇ timing of each address of the write address «circuit (S AG) controlling the writing of the memory (M) and the address circuit (DAG) controlling the reading of the memory (M) is dropped. It controlled by the direct synchronization signal VS YNC.
  • S AG write address «circuit
  • DAG address circuit
  • Other configurations and operations are the same as those described in FIG.
  • the vertical synchronization signal VS YN C from the application processor 42 to the memory (M) is used to write the image data write address (controls the point in time and reads the written data).
  • the image can be synchronized to the timing of the image by controlling the ⁇ 1 ⁇ time point of the image with the vertical synchronization signal VS YN C as well, and the image 3 ⁇ 4 ⁇ can not be made from the middle of the image. There is no 3 ⁇ 4 ⁇ flicker in ⁇ .
  • the present invention has been described by a difficult example, the present invention is not to be I ⁇ in the configuration of the above-mentioned difficult example, and various elements may be used without pronounced of the ⁇ ! Iia concept of the present invention. It goes without saying that it is food.
  • the picture of the moving picture 3 ⁇ 4 ⁇ is synchronized with the frame, there is no flickering display during updating, and the number of cars St data of the blurring data at the moving picture can be reduced. Power consumption can be reduced.
  • control is performed by switching between the still image 'text system' I / O bus' interface and the external ⁇ interface that inputs ⁇ moving image data from image data processing and accessing the image memory.
  • the still image 'text system' I / O bus' interface and the external ⁇ interface that inputs ⁇ moving image data from image data processing and accessing the image memory.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

L'invention concerne un système de commande de circuit d'attaque d'affichage, qui comprend une interface de bus d'image immobile/de texte/de système/E/S et une interface d'image mobile (interface d'affichage externe), ainsi qu'un registre permettant de commuter le fonctionnement de l'affichage de façon sélective en fonction d'un contenu affiché sur un affichage (mode affichage) et un registre permettant de commuter l'accès d'une RAM dans laquelle le nombre de fois nécessaires au transfert d'une image mobile est diminué et la production de papillotement d'écran est évitée au moment de l'affichage d'une image mobile tout en supprimant la consommation de puissance par présentation des données d'affichage sur l'affichage par l'intermédiaire d'une mémoire d'images même en mode d'affichage d'image mobile.
PCT/JP2001/011549 2001-12-27 2001-12-27 Systeme de commande de circuit d'attaque d'affichage WO2003056541A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003556980A JPWO2003056541A1 (ja) 2001-12-27 2001-12-27 表示駆動制御システム
PCT/JP2001/011549 WO2003056541A1 (fr) 2001-12-27 2001-12-27 Systeme de commande de circuit d'attaque d'affichage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2001/011549 WO2003056541A1 (fr) 2001-12-27 2001-12-27 Systeme de commande de circuit d'attaque d'affichage

Publications (1)

Publication Number Publication Date
WO2003056541A1 true WO2003056541A1 (fr) 2003-07-10

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PCT/JP2001/011549 WO2003056541A1 (fr) 2001-12-27 2001-12-27 Systeme de commande de circuit d'attaque d'affichage

Country Status (2)

Country Link
JP (1) JPWO2003056541A1 (fr)
WO (1) WO2003056541A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003263140A (ja) * 2001-12-27 2003-09-19 Hitachi Ltd 表示駆動制御回路
JP2006079013A (ja) * 2004-09-13 2006-03-23 Nec Corp 液晶表示部制御装置、方法及び液晶表示部制御装置を用いた携帯電話機
JP2006235640A (ja) * 2001-12-27 2006-09-07 Renesas Technology Corp 表示駆動制御回路
JP2006330755A (ja) * 2001-12-27 2006-12-07 Renesas Technology Corp 静止画像変更方法
JP2006330754A (ja) * 2001-12-27 2006-12-07 Renesas Technology Corp 表示システムおよびこの表示システムを用いた携帯電話装置
JP2012230395A (ja) * 2010-01-20 2012-11-22 Semiconductor Energy Lab Co Ltd 表示装置

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JPH1165542A (ja) * 1997-08-26 1999-03-09 Seiko Epson Corp 画像信号処理装置
JPH1185119A (ja) * 1997-09-10 1999-03-30 Hoshiden Philips Display Kk モニタ装置のマルチシンク回路
JP2001222249A (ja) * 1999-11-29 2001-08-17 Seiko Epson Corp Ｒａｍ内蔵ドライバ並びにそれを用いた表示ユニットおよび電子機器
EP1164571A1 (fr) * 1999-11-29 2001-12-19 Seiko Epson Corporation Pilote a ram integree, unite d'affichage associee audit pilote et dispositif electronique

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JPH09281933A (ja) * 1996-04-17 1997-10-31 Hitachi Ltd データドライバ及びこれを用いた液晶表示装置，情報処理装置
JP2001202053A (ja) * 1999-11-09 2001-07-27 Matsushita Electric Ind Co Ltd 表示装置及び情報携帯端末
JP2003263140A (ja) * 2001-12-27 2003-09-19 Hitachi Ltd 表示駆動制御回路

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Publication number Priority date Publication date Assignee Title
JPH1165542A (ja) * 1997-08-26 1999-03-09 Seiko Epson Corp 画像信号処理装置
JPH1185119A (ja) * 1997-09-10 1999-03-30 Hoshiden Philips Display Kk モニタ装置のマルチシンク回路
JP2001222249A (ja) * 1999-11-29 2001-08-17 Seiko Epson Corp Ｒａｍ内蔵ドライバ並びにそれを用いた表示ユニットおよび電子機器
EP1164571A1 (fr) * 1999-11-29 2001-12-19 Seiko Epson Corporation Pilote a ram integree, unite d'affichage associee audit pilote et dispositif electronique

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003263140A (ja) * 2001-12-27 2003-09-19 Hitachi Ltd 表示駆動制御回路
JP2006235640A (ja) * 2001-12-27 2006-09-07 Renesas Technology Corp 表示駆動制御回路
JP2006330755A (ja) * 2001-12-27 2006-12-07 Renesas Technology Corp 静止画像変更方法
JP2006330754A (ja) * 2001-12-27 2006-12-07 Renesas Technology Corp 表示システムおよびこの表示システムを用いた携帯電話装置
JP2006079013A (ja) * 2004-09-13 2006-03-23 Nec Corp 液晶表示部制御装置、方法及び液晶表示部制御装置を用いた携帯電話機
US8957881B2 (en) 2010-01-20 2015-02-17 Semiconductor Energy Laboratory Co., Ltd. Display device
JP2012230395A (ja) * 2010-01-20 2012-11-22 Semiconductor Energy Lab Co Ltd 表示装置
US9443482B2 (en) 2010-01-20 2016-09-13 Semiconductor Energy Laboratory Co., Ltd. Display device
US10089946B2 (en) 2010-01-20 2018-10-02 Semiconductor Energy Laboratory Co., Ltd. Display device
US10580373B2 (en) 2010-01-20 2020-03-03 Semiconductor Energy Laboratory Co., Ltd. Display device
US11081072B2 (en) 2010-01-20 2021-08-03 Semiconductor Energy Laboratory Co., Ltd. Display device
US11462186B2 (en) 2010-01-20 2022-10-04 Semiconductor Energy Laboratory Co., Ltd. Display device
US11790866B1 (en) 2010-01-20 2023-10-17 Semiconductor Energy Laboratory Co., Ltd. Display device

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