WO2003056541A1

WO2003056541A1 - Display drive control system

Info

Publication number: WO2003056541A1
Application number: PCT/JP2001/011549
Authority: WO
Inventors: Goro Sakamaki; Takashi Ooyama; Sigeru Oota; Kei Tanabe
Original assignee: Renesas Technology Corp.
Priority date: 2001-12-27
Filing date: 2001-12-27
Publication date: 2003-07-10
Also published as: JPWO2003056541A1

Abstract

A display drive control system incorporating a still image/text/system/I/O bus interface and a moving image interface (external display interface) and comprising a register for switching display operation selectively according to a content being displayed on a display (display mode) and a register for switching access of an RAM in which the number of times for transferring a moving image is decreased and generation of flickering of screen is avoided at the time of displaying a moving image while suppressing power consumption by presenting display data on the display via an image memory even in moving image display mode.

Description

Description 3⁄43⁄4 隱 control system

[Technical field]

The present invention relates to a control technique for controlling the picture ^^ mode of the 3⁄4 ^ device, and in particular, a still image or a moving picture on a liquid crystal device, an organic EL ^: The present invention relates to a guidance control system that controls an image mode of a recording device to be recorded.

[Background technology]

Usually, the dot matrix

It consists of a display panel with pixels and a ^ control circuit for supplying an image signal to the recording panel to make a still image or a moving image. A liquid crystal / display device, an organic EL device, a plasma device, or a release / release device is known as this type of device. Here, the liquid crystal display device, which is a typical example of a liquid crystal device, and the liquid crystal display device using the liquid crystal device as an example, will be described using the liquid crystal display device as an example.

A motion picture (hereinafter, also simply referred to as a motion picture) has been written on a near tongue machine. Since the purpose of the «electronic tongue machine is to mainly play still images (hereinafter also referred to simply as still images) including text, its sound control circuit is a still image · Text · System · I · · Has only one interface, does not have a built-in video interface. Therefore, it is difficult to perform 3⁄4 ^ of moving images that can be smoothed by a small-sized coma control circuit.

Fig. 21 is a block diagram of a ヽ隱 circuit of t ^ ^ ^ si tongue machine having a motion picture-compatible interface, which is a 3⁄4 3⁄4 »control circuit and 3⁄4 / display device examined by the inventor before the present invention. It is a block diagram explaining ^ !. The horseshoe control circuit system 1 'includes an audio interface (AU I) 2, a high frequency interface (HFI) 3, an image processor 4', a memory 5 and a liquid crystal controller 1 which is a display horse control circuit. La · driver, (LCD-CDR) 6 ', still picture' text · system. I / O bus' interface (SSZIF) 7 etc. Reference ^ 9 is microphone microphone (M / C), 10 is speaker (S / P), 12 is antenna (ANT), and 13 is liquid crystal panel (liquid crystal display: LCD).

The image processor 4 'comprises a digital signal processor (DSP) 411 and a baseband processor 41 having an ASIC 412 and a microcomputer MPU. The audio interface (AUI) 2 controls the ear of the audio input from the microphone 9 and the output of audio to the speaker 10.

To record on the LCD panel 13, read the image data from the memory 5 and perform the necessary processing with the microcontroller 413 PU 413 and use the still image · text · system · I / 0 bus interface interface SS / IF 7 The LCD controller, driver (LCD-CDR) 6, is written to the 3⁄4 RAM in the controller. In motion picture recording mode, it is possible to obtain 10 to 15® (frame) power per second. In this system, the system '1' 0 bus force is reduced to 80 series interface. Hereinafter, the still picture 'text system' I / O bus' interface (SS / IF) 7 may be abbreviated as system interface 7.

The operation of the LCD controller driver and (LCD-CDR) 6 works with the built-in clock in the driver. Therefore, the writing of image data and the operation are performed completely asynchronously.

Fig. 22 is a pictorial view showing an example of the motion of the movie in the system shown in Fig. 21. Figure 22 shows a 3⁄43⁄4 picture of the ^ tongue machine, a still image

(Still picture) A state in which a motion picture (Mo t pict ur e) 3⁄4 ^ is performed in the 赫 region is shown. This ^ is the same as in the following. The writing of the image data to the 3⁄4⁄4 ^ RAM in the liquid crystal controller driver (LCD – CDR) 6 takes place completely independent of the operation. As described above, since the writing of the image data and the reading of the relevant image data for the liquid crystal panel LCD are performed, the moving image shown in (a) of FIG. Mo V ingpicture 1) ヽ β 3⁄4 to 動画 2 (Moving picture 2) of ヽ同 c (c) is in the middle of the picture as shown in (b) of FIG. There is a

In the middle of the screen, the movie is performed ^, movie 1 (Mo video picture 1) and movie 2 (Moving picture 2) are performed simultaneously in the same display. As shown in (b) of the figure, the boundaries between the moving picture 1 and moving picture 2 in the eyebrows are noticeable, and there is an age at which it becomes visible as flickering of the picture. As you can see, still pictures, texts and systems 'IZO bus' interface SSZIF only makes it difficult to make 3⁄4 ^ of movies high fi ^{1. For} videos »3⁄4 ^ It is necessary to write the image data in synchronization with the operation.

FIG. 23 is a block diagram for explaining a configuration example of a liquid crystal controller driver and its peripheral circuits in the system shown in FIG. LCD Controller · Dryo

(LCD-CDR) 6, indicates a write address circuit 61, a recording address circuit 62, and a bit map composed of RAM ~ memory (memory 3) ^ memory (M) 63, liquid crystal, gate circuit (DR) 64, built-in clock A generation circuit (CLK) 65 is provided. The data (DB1 7-0) from the image processor 4, baseband processor 41 is written from the system interface (SSZIF) 7 to the built-in memory M.

The write address at this time is the write address circuit (SAG) 61 of the system 'interface signal CS (chip select), RS (register select) WR (write) ^ The readout of the data of oscillation is read from the display memory (M) 63 in accordance with the address stored in the recording address band circuit (DAG) o 3⁄4 ^ address ^ 3⁄4 built-in clock 3⁄4 ^ circuit (CLK) This operation is synchronized with the clock shown in «65. The operation by this built-in clock and the operation by the system 'interface (SSZIF) 7 are performed at completely unrelated 同期 synchronization).

FIG. 24 is a schematic diagram for explaining »of β3⁄4 of a moving image in a drawing of a tongue tongue using a liquid crystal controller and dry screen of the system shown in FIG. Readout line by display operation (^ spring: pixel selection line) LR is read out from the head by 1 ^ according to the built-in query. System Inta-I-Hue The writing of display data from memory (SS / IF) 7 to the memory M is performed independently of the operation. For this reason, the write line by the system interface (SS / IF) 7 overtakes the read line LR by the action. That is, there are 3⁄4 ^ write line LW, 3⁄4 ^ read line LR and force 3⁄4 ^ ii ^.

As shown in (c) of Fig. 24 for the write line, read line, and force, the dynamic im ^ i state of Fig. 24 (a) is shown in the moving picture 3⁄4 ^ state of Fig. 24 (b). When changing, flicker occurs on ^ on this line. On a screen of 60 frames per second, you need to shoot 15 images per second ^, and once every four frames {@ 3⁄43⁄4 ”. This ί3⁄4 occurs four times per second, resulting in four flickers per second. This flicker is one of the key tones to be found in this type of 3⁄4 equipment L, Nako.

In addition, when the LCD controller or driver is activated to avoid the flickering of the screen as described above, the power consumption of the 3⁄4 ^ device becomes effective, especially in a 麟 terminal such as a 歸 «I tongue machine. It is not desirable. The object of the present invention is to reduce the power consumption by not having the flicker at the time of moving picture and squeezing the moving picture function of the quality, and to reduce the power consumption by using a dedicated control system.

Country Disclosure]

In order to realize the above object, the present invention uses a system interface in the still image mode as the second function and a movie interface interface as the first function in addition to the system interface in the still image mode, and the time period further required The only problem is that the power consumption has been reduced by switching to the still image interface (system 'interface) so as to operate the motion picture interface only. The following is a brief description of the control system according to the present invention.

(1), voice interface, high frequency interface, still image · text · system · I / 0 bus · interface and external 3⁄4 ^ interface to input moving image data, The IB3⁄4 device has at least one frame of image data storage area and a 3⁄4 / display control circuit for supplying 3⁄4 / display data to the display device. 3⁄4 ^ Synchronized to movement and move 1 o'clock Let F ¹ be M.

(2), (1), 編 ⁄ ⁄ / 示隱隱 ⁄ 己隱が隱回路己回路回路回路回路龍テキストテキストシステム · · · · · I · 0 bus · interface · external display interface display data Let l and w be memory write and read select connection 3⁄4 ^ Operation change register and memory access change register are assumed to be:.

In (3) and (1), the editing control circuit has a vertical synchronization signal input of the moving image, and the editing β ^: the transition of the writing and reading of the moving image 3⁄4 data to the memory. It is assumed that the control is based on the vertical sync signal which is preferred from the sleep sync signal input.

In any one of (4) and (1) to (3), the control circuit has an enable signal λΛ that specifies an area in which the 1133⁄4 image is to be transferred to the device 3⁄4 ^. The thing is 3⁄4.

In any one of (5) and (1) to (3), an in-one call signal specifying an area to which the still image in the area to display 3⁄4 of the so-called “3 still image” of the 籠 3 ^ device is specified. Let M be human power.

(6), including an eyelid panel and a memory for storing image data to be supplied to the editing panel, and supplying so-called image data and timing to the ta3⁄4 ^ panel

3⁄4 ^ 隱 control circuit, JI 33⁄4 ^! And an image processor for storing the self-organized image data in the memory 151 of the image control circuit.

The camera controller is connected to the image processor by the first means for writing the image data corresponding to the animation data into the memory. Make it special.

In (7) and (6), the は 33⁄43⁄43⁄4⁄4 control device is further coupled to a so-called image processor by a second function for writing Fujimi image data, which is regarded as still image data, into the recognition memory. Do.

In (8) and (7), the Ryukyu 1 function includes the vertical synchronization signal supplied from the picture processor to the male control circuit, and the i a 3⁄4 direct synchronization code has been written to the memory. ls Special feature is that it is used as a signal to indicate the readout table of the image signal. In (9) and (8), it is assumed that the 爾碟 1 function further includes a horizontal synchronization signal and a dot clock.

(1 0) 3⁄4 / display panel and memory for storing image data to be supplied to the so-called panel, and supplying self-image data and 3⁄4 timing to the editing panel 3⁄43⁄43⁄4⁄4 control circuit, 籠 53⁄4 / To the recognition memory of the guidance and reading control circuit! It has an image processor that stores its own image data,

The 53⁄4 slaughter control device has a first function for writing knitting image data corresponding to moving picture data into the knitting memory, and one self-image data considered to be still image data. It is assumed that it is combined with the knitting image processor by the second function to write to the image.

In (11) and (10), the edit ai function includes the vertical synchronization signal supplied from the image processor to the adjustment / indication control circuit, and the direct synchronization signal is transmitted to the adjustment memory. It is assumed that [i] is a signal to indicate the reading station of the written one's own image signal.

(1 2), including a recording panel and a memory for storing image data to be supplied to a so-called 5⁄4⁄3⁄4 panel, and providing the image data and timing to the editing panel.備 33⁄4 ^ 備 control circuit's memory to the memory of the so-called image processor to store image data,

The vertical sync signal is supplied from the image processor to indicate a signal for writing the image data corresponding to the moving image data into the memory. I will

According to the ^ 隱 control system of the present invention as described above, it is possible to display high quality moving images, and to display moving image interfaces and still image interfaces. Low power consumption can be achieved by switching according to the still image mode).

Brief description of the picture]

FIG. 1 is an explanatory view of the complete constitution of one difficult example of the present invention. FIG. 2 is a schematic diagram illustrating ^ of »of the moving image of 3⁄4⁄4⁄4 of the portable Hi tongue using the configuration of an example of the horseshoe control system according to the present invention. FIG. 3 shows the liquid crystal control according to the present invention. It is a block diagram explaining the circuit structure of a roller. Driver, and its related circuit. Fig. 4 is a schematic diagram showing the motion of a moving image βϊ ^ of a moving image of a crane tongue using a configuration of a difficult example of the 3⁄4 ^ 隱 control system according to the present invention as an operation with a moving image. . FIG. 5 is an explanatory view of the configuration and operation of a liquid crystal controller / driver without a moving image interface and a built-in memory for clarifying the effects of the example of the present invention. Fig. 6 is a schematic diagram for explaining the appearance of a still image ^ by the liquid crystal con- trol roller and the driver in Fig. 5. FIG. 7 is an explanatory view of the configuration and operation of a liquid crystal controller driver that performs data processing using a system interface and a built-in memory to explain the effect of the difficult example of the present invention. FIG. 8 is an overhead view for explaining the still picture recording by the liquid crystal controller 'driver of FIG. 7; FIG. 9 is an explanatory view of the merits and demerits of the configuration of the present invention, showing the configuration of FIG. 7 and the configuration of FIG. FIG. 10 is an explanatory diagram of a circuit configuration of a driver chip in which the liquid crystal controller / driver of the present invention is embodied. FIG. 11 is an explanatory view of the configuration and operation of an example of a liquid crystal controller and driver which has a system interface and an application interface and performs data by built-in memory. FIG. 12 is a schematic diagram for explaining the freshness of the stationary j by the liquid crystal controller driver of FIG. Fig. 13 is an explanatory view showing the switching operation of the system interface and the application interface in the form of a display. FIG. 14 is an explanatory view of another example of the present invention. FIG. 15 is a diagram for explaining the eaves of moving image data in the moving image buffering operation according to the circuit configuration of FIG. FIG. 16 is a block diagram for explaining an example of a circuit configuration for implementing a moving image according to the present invention. Fig. 17 is a pattern diagram for explaining the situation of the liquid crystal controller in Fig. 16. The situation of the first stop only to the selected area by the driver. FIG. 18 is an explanatory view of moving image data of each data car 3⁄4 ^ for explaining the effect of the present invention. FIG. 19 is an explanatory view of still another example of the present invention. FIG. 20 is an explanatory view of still another example of the present invention. Figure 21 is a part of the control system that has been studied by the present inventor before the present invention. Fig. 22 is a block diagram illustrating "^. Fig. 22 is shown in Fig. 21 FIG. 11 is a schematic diagram showing an example of the operation of n ^ f at the time of movie ^ ^ in the system. Second

FIG. 23 is a block diagram for explaining an example configuration of the liquid crystal controller driver and its peripheral circuits in the system shown in FIG. FIG. 24 is a diagram for explaining »of the moving image S ^ 1 in the drawing of the tongue-lifting machine using the liquid crystal controller / driver of the system shown in FIG.

3⁄4 开 for making light

Hereinafter, the third embodiment of the present invention will be explained to the staff with reference to the medical image of the embodiment. FIG. 1 is an explanatory view of the whole configuration of the example of the present invention, and it is an interface for moving picture corresponding to the first function which is HI of the 3⁄4⁄4⁄4 control system according to the present invention. FIG. 8 is a block diagram for explaining an example of the configuration of a Zeon Yu Tong machine having a moving picture (including a first port to be processed). An audio interface (AUI) 2 similar to that shown in FIG. 20, a high-frequency interface (HFI) 3, an image processor 4 which is an image data processing unit, and a memory 5 are memories. And 3⁄4 ^ control circuit LCD controller · driver (LCD-CDR) 6, second function still image · text 'system · I / O bus interface (SSZIF) 7 (ie still image data (Including the second position to be forced) and the like.

The memory 5 is a frame memory (bit map memory) for storing at least one image frame worth of image data (bit map memory), and in the following description, the graphic RAM is also referred to. · System · I / 0 bus · Interface (SSZIF) 7 is also described as System interface 7 or Movie interface.

And, in addition to the baseband processor 41, which has a digital signal 'processor (DSP) 411 and an ASIC 412 and a microcomputer MPU in the image processor 4, a video processing processor (MPEG) 421 and a liquid crystal 3⁄4 ^ control It has an application processor (APP) 42 which has a speaker (LCDC) 422. Reference numeral 9 denotes a microphone (MZC 9 and 10 a speaker (S / P), 11 a video camera (CZM), 12 an antenna (ANT), and 13 a liquid crystal panel (liquid crystal display: L CD) AS IC 412 is the other ^ Telephone system configuration ^ Has necessary peripheral circuit functions. In addition, the image processor 4 may be formed of a single silicon substrate such as silicon (a silicon substrate may be formed into a chip), and each of the base processor 41 and the application processor 42 may have one silicon substrate. (It may be formed in a tip force.

21. In the tongue-and-loop system shown in Fig. 21, the “Bandband processor provided in ^ ^ is lacking in video processing in this BBP. This baseband.processor B In addition to the application processor A sub-MPU is known as (APP) and an application processor (APP) 42 shown in Fig. 1 has a built-in MPEG processor (MP RG) 421 for performing MPEG video processing and the like. In addition, application processor (APP) 4 2 performs image data to LCD controller 'Drino (L CD-CDR) 6 with moving picture interface (MPZIF) 8. Still image data and text 3⁄4 ^ data is the second Similar to the system shown in FIG. 21, the liquid crystal controller / driver (LCD-CDR) 6 is $ S3 via the system 'interface (SS / IF) 7.

FIG. 2 is a schematic view for explaining the freshness of a moving image φ® in display translation of a mobile phone using an example of the display control system according to the present invention. In the movie tracker MP / IF 8, the ^ operation is performed by the sync signal sync sync signal V SYNC, the horizontal sync H SYNC, the dot clock DOTCLK required for the operation, and the 3⁄4 ^ data is synchronized to the 3⁄4 ^ operation. A liquid crystal controller using LCD (CD-CD) with 3⁄4 data by the data enable signal (ENA BLE), and a data enable signal (ENA BLE). 6 memory (internal RAM: M) Write to 5 As a result, 13⁄4 from β 3⁄4 in (a) of FIG. 2 to β 3⁄4 in (b) is performed from the beginning of the ίβ, and switching from 1M does not occur.

FIG. 3 is a block diagram for explaining the circuit configuration of the liquid crystal controller and driver according to the present invention and related circuits. In the figure, the same reference as in FIG. 1 corresponds to the same opinion. Liquid crystal controller and driver (LCD-CDR) 6, for example, single semi-conductor substrate like single crystal silicon (chip force by ^ CMOS CMOS process It has a serial address generation circuit (SAG) 61, a display address ^^ circuit (DAG) 62, a 3⁄4 ^ memory (M) 63, and a liquid crystal dedicated circuit (DR) 64.書き込み Writing data is fi ^ ed to the data bus (PD17-0). At this time, the write address DA is 55 in the 赫 address «circuit (DAG) 62 based on the video interface signal (VSY NC, HSYNC, DOTCLK).

The readout of the new data is read from the built-in memory (M) 63 and applied to the liquid crystal display (DR) 64 in accordance with the address D A read from the video data signal.書き込み The data write address and read address are both ^ 3⁄4 as a video interface.

FIG. 4 is a diagram for explaining the action of the moving picture in the drawing β of the ^^ tongue machine using the difficult example of the 3⁄43⁄43⁄4 隱 control system of the present invention as the working of the moving picture interface. Writing of recording and recording from the system 'interface (SSZIF) 7 is written to 3⁄4 ^ memory (M) 63 according to the dot clock DOTCLK from the video interface (MP / IF) 8 in FIG. The

Data is read out according to the video interface (VSYNC, HSYNC, DOT CLK). Since writing and reading of image data are performed based on the same signal, they are performed with the same one ^. In Fig. 4 (a), LR indicates the data read line, and LW indicates the data write line. Also, LEND in (C) of Fig. 4 indicates a winter winter line.

The time t ₀ indicates the start point of the surface final line 3⁄4 ^, and the time t ₀ indicates the start of the surface final line 3⁄4 ^. As a result, there is no separation between moving picture 1 and moving picture 2 as described in FIG. It does not occur. The writing address and reading address need only be kept constant at one line i: Next, the still picture mode will be described.

Fig. 5 shows the configuration and operation of the liquid crystal controller · driver without the moving image interface and the built-in memory for comparing and comparing the effects of the example of the present invention. FIG. Further, FIG. 6 is a schematic view for explaining the state of still image display by the liquid crystal controller driver of FIG. The liquid crystal controller 'DR LCD' has a line memory (LM) 63 as a memory M.

In this configuration, since there is no RAM memory such as bitmap memory, even in still picture 3⁄4 ^ mode, as shown in (a), (13), Data must continue to be $ 53⁄4 to the LCD controller 'Dr LCD-C DR 6'. Therefore, it is difficult to reduce power consumption by data transfer. In addition, since the car data is different for each moving picture 3⁄4 ^, the circuit according to the present invention can be written in synchronization with the 3⁄4 ^ operation (s m d 3⁄4 3⁄4.

FIG. 7 is an explanatory view of the configuration of the liquid crystal controller driver for performing data by the system interface and the built-in memory to clarify the effect of the embodiment of the present invention and the operation thereof. FIG. 8 is a view for explaining the state of a still picture by the liquid crystal controller / driver shown in FIG. In the configuration shown in FIG. 7, a bit map memory (M) 63, which is a RAM memory similar to that of FIG. 3, is incorporated as a built-in memory (Μ) 63 as a memory.

As shown in FIG. 8, after writing one minute of image data to this built-in memory (M) 63, to read the data of the concerned memory (Μ) 63 by the built-in clock. There is no need to re- ^ still image data. This reduces power consumption in the data. Based on this idea, in a difficult example of the present invention, the configuration of FIG. 7 is overlooked in still image recording and the configuration shown in FIG. is there. For switching between the still picture mode and the moving picture mode, a register is provided, and mode switching is performed according to the state of this register.

9 is an explanatory view of the merits and demerits of the configuration of FIG. 7 and the configuration of FIG. 5 and the configuration of FIG. 5 with J ± K. In the configuration 1 shown in FIG. 9, that is, only the system interface and the 3⁄4 ^ memory (RAM), the built-in memory (RAM) enables the still image 3⁄4 ^ mode and the movie 3⁄4 ^ mode. In any picture ^ 3⁄4 ^ mode, you can minimize the power of β ^ β. As shown in FIG. 2 to FIG. 23 in FIG. 2 to FIG. In the configuration of 2 in FIG. 9, that is, the configuration with the video interface and the line memory, it always requires the data β including the still image 3⁄4 which can be flicker free. In order to save energy, it is difficult to reduce energy consumption. On the other hand, according to the invention of the present invention, the built-in memory and moving picture interface shown in FIG. 9 3 are provided, and still picture mode and moving picture mode are switched. According to the configuration of the example, it is possible to use a video server that has no flickering, and it is possible to reduce the power consumption with a minimum of data car.

Next, a specific system configuration and its operation for realizing switching between the 3⁄4 ^ mode of the moving picture 3 and the still picture 4 in the moving picture interface and the system interface according to the present invention will be described.

FIG. 10 is an explanatory diagram of a circuit configuration of a driver chip, which is a specific example of the liquid crystal controller 'driver' which constitutes the control system of the present invention. The still image data to this drive 600, text data, etc. are written to baseband.processor 4 1 to the system interface 6 0 1 Internal address counter (AC) Memory indicated by address 6 0 6 That is, it is written as data to graphic RAM (GRAM) 610. The recording operation is as follows. That is, internal black? The timing circuit 6 2 2 generates the timing and display address necessary for the clock / production based on the clock signal that was generated by the clock ^ ^ circuit (C P G) 630.

At this timing, the graphic RAM (GRAM) 610 in 3⁄4 ^ address reads out the 3⁄4 ^ data, and the liquid crystal, which is necessary for the liquid crystal display. Send to Nell. The operation mode switching register (DM) 6 2 1 RAM access switching register (RM) 605 is used to switch between movie recording mode and still picture mode.

In motion picture mode, motion picture data (PD 1 7-0), vertical sync signal VSYNC, soft sync synch No. HS Y N C, dot clock DCLK, data enable signal E NA BLE application processor 4 Enter two forces, the external recording system-6200. 3⁄4 ^ Operation switching register (DM) 6 2 1 using timing generator circuit 6 2 2 from internal clock を to synchronous signal (VSY) Switch to NC, HSE N C) and Mi the necessary timing code.

In addition, the operation of the address counter (AC) 606 is switched to the dot clock DCL :, de-enablement (a signal from ENABLE) by the RAM access switching register (RM) 605, and graphic RAM. (GRAM) Switch the data bus to 1 6 0 to (data (PD 1 7-0) By this, the motion / RAM access operation is performed using the system interface 6 0 1 and the internal clock «circuit (CPG) Switched from 630 to the external display interface module 620 that is an animation interface.

In FIG. 10, reference 602 is a gate driver 'interface (serial), 603 is an index register (IR), 640 is a control register (CR) (CR) , 6 0 7 is a bi-perpendation circuit that performs processing on a bit basis, 6 0 8 is a read (read) read out circuit, 6 0 9 is a write (write) read out circuit. is there. Further, reference numerals 6 2 3 6 4 2 6 6 6 6 are latch circuits, 6 2 5 are AC circuits, 6 2 s 7 are slaughter circuits, and so on. Configure And, 640 is a gamma (y) adjustment circuit, and 650 is a P all adjustment Μίί ^ circuit, which constitutes a data processing circuit to the liquid crystal panel. Note that since the bit operation! 0-7 is a unit that performs bit-based operation processing and bit-based reordering operation, the: function not required is omitted.

Next, I will show you the! ^ Field of the switching register of the system interface and the application interface. Table 1 shows the mode ^ I state of the RA1V [access switching register (RM) 6 0 5 described in FIG. 10]. In Table 1, this register is referred to as a RAM access mode register. table 1

Perform RM RAM access

Interface

0 System interface ^ -S / VSYNC interface ^ "S

1 RGB interface " Table 2 also describes ^ operation switching register (DM) 6 0 described in Figure 10.

5 mode ^ Indicates status. In Table 2, the operation mode register

I am selfish with this evening.

4 1

And Table 3 shows RAM access switching register (RM) and display operation switching

An illustration of the state of the various ^ operation modes depending on the combination of registers (DM) ^

It is.

As shown in Table 1, the RAM access switching register (RM) has a built-in table.

Display memory (graphic RAM) An interface for accessing GRAM Switch the The I ^ of this RAM access switching register (RM register) can be described by "RM! ^ I state". When "RM = 0", the display data is written to the memory GRAM only from the system interface. It becomes possible. When “RM = 1”, it is possible to write to memory GRAM only from the application 'interface (moving picture interface, RGB interface in Table 1). '

The 赫 operation switching register (DM register) shown in Table 2 is a 2-bit 13⁄43⁄4 switch, and switches the 标 operation mode. This DM register's status is described in "DM status". When "DM = 0 0", operation is performed using the internal clock. In addition, "DM = 0 1" record operating mosquitoes ^ ¹ and dividing by the moving interface one face (RG B Interferon over the scan) is when. When “DM = 10”, the operation is based on the VS YN C interface, and the operation is performed by only the VS YN C signal at the RGB interface and the built-in block. Note that “DM = 1 1” is prohibited.

In this way, switching of the interface is controlled by controlling the two registers (RAM register, DM register) of the RAM access switching register and the memory switching register. As described collectively in Table 3, switching between the 2⁄4 ^ operation in the state of two registers makes it possible to operate in various modes. In Table 3, “DM ^ I state” is described as (DM 1 − 0 = 0 0) o

Figure 11 is an illustration of the configuration and operation of the liquid crystal controller with a built-in memory and a data controller with a built-in memory with the system interface and interface. Further, FIG. 12 is a schematic view for explaining 1 1 of still images shown by the liquid crystal controller driver of FIG. In this example, the system interface (baseband interface) 4 1 for inputting still image data etc., and the application interface-interface 4 2 for moving image interface 3⁄4 ^ Built-in RAM memory (recording memory M) 6 3

Vertical sync signal VS YN C is a timing signal that indicates the β start of the »operation, The sync signal H SYNC is a timing signal indicating the line cycle of operation ヽ dot clock D 0 TCLK is a clock in pixel units, and becomes a clock for 3⁄4 ^ operation by the image interface or application 'interface (APP) 42 . This dot clock DOTCLK also serves as a write signal for 3⁄4 ^ memory (M) 63. Data is synchronized with this dot clock DOTCLK to perform image data. Note that the enable signal ENABLE is a signal that indicates that each pixel data is available. This enable signal is written to memory (M) 63 only when the enable signal is enabled.

That is, as shown in FIG. 12, the RAM data area of still

Moving to S S D rice one pull ί saying No. ENAB L Ε force of the A, the area Ru Der video 赫領 area MPDA! Data PD17-0 Power record. In addition, the back porch period (ΒΡ3−0) and the front porch period (FP3−0) are provided on the upper and lower sides of the screen, and the power is provided for 3⁄4 ^ period (NL4−0) therebetween.

FIG. 13 is an explanatory view showing the switching operation of the system interface and the application interface in a state of 3⁄43⁄43⁄43⁄4. System interface-'Face motion p still image FS; ^; application interface motion video ^ ^ 1,,] ^? 2, · · · · · · · · · · · · force » It shows. The time to do the movie 3⁄4 ^ should be less from the time to do the movie 3⁄4 ^ on the crane 霞. For this reason, when the number of still images occupying a large number of times, the system operates with low power due to "system interface face + internal face ^".

Then, only when the movie 3⁄4 ^ is performed, each register (RM, DM) is switched as activated to enable the application 'interface (movie interface). This will minimize the period of time to use the data power interface and reduce the power consumption of the entire system. In addition, including the ^ of the register, the system of this system is edible only from the system interface. You may choose to perform instruction I ^ via IJ.

FIG. 14 is an explanatory diagram of another embodiment of the present invention, and is a block diagram for explaining a circuit configuration for performing the motion picture information-flickering operation. t Bm 5 explained in Fig. 6 and Fig. 6 And in the image display system, a movie during (application 'interface麵時) is ^ data in the line memory Exiled ^ ¹ with the accommodated ^亍cracking. Therefore, it is necessary to keep the »schedule constant. In this difficult case, even when using the movie interface (application interface (Α Ρ 4 4) 4 2), all data is stored in RAM memory (M) 6 3 and the stored data is It reads out according to the sync signal (VS Y N C, H SYNC, D OT C LK, ENA BLE) input by the video interface (63) and outputs it to the liquid crystal panel, which is output. Access switching to the built-in RAM memory (M) 63 is performed using the access mode register (RM register) 605.

Fig.15 shows the video data in the video buffering operation by the circuit configuration of Fig.14.

-This is a trial drawing to explain «of». In moving images that use only line memories as described in Fig. 5, moving image data must be constantly maintained. In the current ^^^ system, the number of frames (frames) per second in the movie 3⁄4 ^ is 10-15. Therefore, if the number of frames in one second is 60 frames, Si® if will be performed once in 4 frames. That is, four frame periods have the same β.

If the animation with the current tongue-and-loop machine is performed in the configuration shown in Figs. 5 and 6, the data ^ il must be conducted over the same period of four frames, so «3⁄4 Force goes down. In this example, since moving image buffering is used to store all moving image data in the built-in RAM memory, data is only output when U®'s data is recorded, and the recorded data in the built-in memory is fffed. In the subsequent 1⁄3 ^ period, the data stored in the memory is read out and recorded without data 3⁄4 t from the system side. As a result, the number of motion picture data is reduced to 1⁄4 of the motion picture frame of the above example at 15 frames per second and a frame frequency of 6 0 Hz.

'The present invention is applicable only to the selected area of the moving picture data 3⁄4 ^ area when the moving picture display area MP DA is inserted into the RAM data 3⁄4 ^ area (still picture 3⁄4 ^ area) SSDA as described above. It is also possible to drive 13⁄43⁄4 画 data.

FIG. 16 is a block diagram for explaining a difficult example of the circuit configuration for obtaining the animation according to the present invention. It is a lock figure. FIG. 17 is a schematic view for explaining »of still image display only on the selected area by the liquid crystal controller driver shown in FIG.

If you do not use moving picture performance or puffing, or if you want to use the liquid crystal panel to perform moving pictures, the moving picture area including the still image of MPDAJ2W and the constant area from SDA, always include data from the moving picture interface. Because of this, the data vehicle will lose power, and the power will increase. In the selected fiber of this difficult example, the data from the movie interface will be赫 Area Only recorded data of MPDA can be β.

In the area, still image data is written to the memory and placed in the memory, and the motion image data, such as 3⁄4 ^ data, is written only to the part of the memory instructed by the ENABL Ε signal. As a result, the still image and the moving image are combined on the 3⁄4 ^ memory, and simultaneously read out to the 3⁄4 ^ pB temple to be performed on the liquid crystal panel 13. As described above, according to this example, it is possible to selectively specify the moving image ^; area, and it becomes possible to move the moving image ^ with the minimum data corresponding to the moving image area. In addition, h is not limited to :: device of crane 3⁄4⁄3⁄4 machine, but also applies to large-sized display devices such as basin controls, display monitors, etc.

FIG. 18 is a Jti 3 clear view of moving picture data ⁄ 43⁄4⁄4 of each data for explaining the effect of the present invention. In addition, FIG. 18 shows a liquid crystal panel size of 176 × 2 40 dots, a moving picture size of QC IF size (144 × 176 dots), a moving picture frame number of 15 frames per second (fps), and a frame frequency of 60 Hz with 3⁄4 ^ The comparison is As can be seen from FIG. 18, (a) 176 x 240 x 60 frames = 2.5 M sec for i ^ (without built-in memory) with movie interface only; (b) movie buffering for 3⁄4 176 x 240 X 15 frames = 633 k times feii / s, (c) Movie pf, selected with iRlJ image: 1 44 x 1 76 x 15 frames = 380 k times less cars.

Therefore, the data is (b) reduced by approximately 25% against (a) movie buffer only 3⁄4 ^, (c) movie bulletin selection area 3⁄43⁄43⁄43⁄4 (a) ) For the video interface only: ^ A reduction of about 15% is possible.

FIG. 19 is an explanatory view of still another example of the present invention, and is a schematic diagram for explaining the 3⁄4 ^ rewriting of the still image region in the moving image 1. As specifically described in FIG. 10, the liquid crystal controller driver according to the present invention switches between still image interface and moving image interface with a register, and in FIG. It is possible to make it possible to do the motion picture buffering as described, and also to rewrite the still picture area in the motion picture.

As shown in Figure 19, even when displaying a movie in recording,

It is necessary to use an icon mark (H 10, radio wave, etc.) as in the case of the machine. Here, we will show an example of making a still image area of an image into a picture as an example. Rewrite of recording data by となる is 時 2 4 他の 4 行う行う行う ^ 他の ⁄ ⁄ ようようようようようようようようようようようようよう静止動画静止動画動画動画動画動画動画動画モードレジスタレジスタレジスタレジスタレジスタレジスタレジスタSwitching is performed using the memory switching register (DM) and the RAM access switching register (RM) Furthermore, this switching can be performed by switching between operation and memory.

For this reason, in this example, as shown in the operation pulse of FIG.

Switch RM) to “system interface” as “= 0”, and 3⁄4 / show data of still image 3⁄43⁄4 region! ^? At the end of the if period of this still picture area, the RAM access switching register (RM) is set to “= 1”. In the still image recording area of; ^ 删 between TS, 3⁄4 ^ Operation switching register (DM) is set to “= 1”, and the moving image interface outputs ^; As a result, even in the middle of a row, it becomes possible to make the still picture attractive area difficult, and a more flexible H state can be realized. FIG. 20 is an explanatory view of still another example of the present invention, and is a block diagram for explaining an example of the configuration of the liquid crystal controller driver and its peripheral circuits in the system. In this embodiment, the application processor 42 is uttered to the configuration shown in FIG. Then, from the application processor 42, the ^^ timing of each address of the write address «circuit (S AG) controlling the writing of the memory (M) and the address circuit (DAG) controlling the reading of the memory (M) is dropped. It controlled by the direct synchronization signal VS YNC. Other configurations and operations are the same as those described in FIG.

In the configuration of this example, the vertical synchronization signal VS YN C from the application processor 42 to the memory (M) is used to write the image data write address (controls the point in time and reads the written data). The image can be synchronized to the timing of the image by controlling the 垂直 1 ^ time point of the image with the vertical synchronization signal VS YN C as well, and the image 3⁄4 ^ can not be made from the middle of the image. There is no 3⁄4 ^ flicker in β.

Although Lh, the present invention has been described by a difficult example, the present invention is not to be I ^ in the configuration of the above-mentioned difficult example, and various elements may be used without reminiscent of the ^! Iia concept of the present invention. It goes without saying that it is food.

Available for

According to the present invention, since the picture of the moving picture 3⁄4 ^ is synchronized with the frame, there is no flickering display during updating, and the number of cars St data of the blurring data at the moving picture can be reduced. Power consumption can be reduced.

Also, control is performed by switching between the still image 'text system' I / O bus' interface and the external ^ interface that inputs φ moving image data from image data processing and accessing the image memory. By being configured to be, it is possible to select the 3⁄4 ^ mode according to the display content.

Furthermore, by switching the corresponding interface between the movie mode and the still image mode, it is possible to use the functions of each interface for the entire system. It is possible to reduce the force. .

Claims

-'Im

1. Audio interface, high frequency interface, still image 'text • System · I ZO bus' interface, external display interface to scan moving image data, image for at least one frame It has an image ^^ memory with a data storage area and a 3⁄4 ^ ^ control circuit that supplies ^ data to the 3⁄4 ^ device, and it synchronizes with the 3⁄4 ^ operation of the 3⁄4 ^ device in the still image area. To do 3⁄4 ^: 3⁄4 ^!隱 control system.

2. Foreword 33⁄4 ^, ® control circuit, H self-image · text · system · I / 0 bus

• Select an interface and an external interface for writing and reading the memory 3⁄43⁄4 memory. Having a memory switching register and a memory switching register. Control system of 1 word to say.

3. So-called “53⁄4” / “屠” circuit has vertical sync signal “ΛΛ” terminal of moving image, and the timing of writing and reading of moving picture data to arrangement ^^ memory | 33⁄4 rectilinear sync signal input The control system described in (1), which is controlled by the vertical synchronization signal input from.

4. The H.sub.3.sub.3.sub./4.sub.3.sub.4 control circuit is any one of 1 to 3 which has an enabling signal input preference for specifying a region for displaying / displaying a 33.sup. Word 33⁄4 W EIil control system.

5. It is assumed that it has an enable signal input for specifying a region to which “^” of the still image in the region of the β 33 self-organized still image of the device should be designated as any one of 1 to 3. Display drive control system.

6. A 隱 slaughter control circuit including a panel and a memory for storing image data to be supplied to the orchid panel and supplying image data and »timing to the so-called B 3⁄4 ^ panel; And an image processor for storing the image data into the self-memory,

The H3⁄4⁄4⁄ control device is characterized in that it is combined with a self-image processor by a first function for writing the self-image data corresponding to moving image data to the memory.

7. The I 53⁄43⁄43⁄4⁄4 control device further assumes that it is combined with a so-called image processor by a second function for writing the still-image data to be stored into the knitting memory. The control system of 33⁄4 in claim 6.

8. The edit 1 function includes the vertical synch 号 which is supplied from the edit image processor to the edit 53⁄4 ^ 卿, and the coma direct synch 1 is written in 1 3 memory. The control system according to claim 7, which is viewed as a signal for indicating a readout of an image signal.

9. The 3⁄4 ^ coma control system according to claim 8, wherein it is assumed that the first edition further includes a horizontal synchronization signal and a dot clock.

1 0. Display panel and display memory control circuit that includes the memory to store the image data to be supplied to the 隱 a3⁄4 パネル panel to the 1133⁄ panel and provides the self-image data and the timing. 33 4 ^ 11 隱 control circuit to 11 self-memory 11) has an image processor for storing self-image data,

The specialized control device writes the first function to write the image data corresponding to the moving picture data to the memory, and the self-image data to be recorded as the still image data to the memory. The second function is to be combined with the knitting image processor by means of a 3⁄4 ^ tail control system.

1 1. The Hani function includes the vertical synchronization signal supplied from the knitting image processor to the so-called control circuit, and the straight sleep synchronization signal reads the Fujimi image signal written in the 3rd edition! A system according to claim 10, characterized in that it is signaled to indicate ^.

1 2. A display control circuit that includes a panel note and a memory that stores image data to be supplied to a so-called 3⁄4 panel, and supplies a self-portrait image data and recording timing to the 歸 33⁄4 ^ panel;編 Control circuit 3 Having an image processor to store image data into memory

麵 ^ 3⁄4 ^ Endurance control device is supplied by the vertical sync signal or H self image processor to indicate the §3⁄4 table for writing the self-organizing image data corresponding to the moving image data into the self-organizing memory. A 3⁄43⁄4 隱 control system.