JP3826159B2 - Display drive control circuit - Google Patents

Description

  The present invention relates to a display drive control technique for controlling an image display mode of a display device, and more particularly to a display device that displays a still image or a moving image on a liquid crystal display device, an organic EL display device, or other dot matrix type display devices. The present invention relates to a display drive control device that controls an image display mode.

  In general, a dot matrix type display device includes a display panel having a large number of pixels arranged in a two-dimensional matrix, and a display control circuit for supplying image signals to the display panel to display still images and moving images. The As this type of display device, a liquid crystal display device, an organic EL display device, a plasma display device, a field emission display device, or the like is known. Here, an outline of an image display system will be described by taking a liquid crystal display device which is a typical display device and a mobile phone using the liquid crystal display device as a display unit as an example.

  In recent years, there has been an increasing demand for displaying a moving image (hereinafter also simply referred to as a moving image) on a display screen of a mobile phone. However, since the conventional mobile phone is mainly intended to display a still image including text (hereinafter also simply referred to as a still image), the drive control circuit includes a still image, text system, I / O, It has only an interface circuit and does not have a built-in interface circuit for moving images. For this reason, the conventional drive control circuit can display a moving image, but it is difficult to display a moving image with high image quality that can be observed smoothly. Hereinafter, the interface circuit is simply referred to as an interface.

  FIG. 21 is a block diagram illustrating an example of a drive circuit system configuration of a mobile phone that does not have a moving image compatible interface, which is an example of a display drive control circuit and a display device that have been studied by the inventors before the present invention. The drive control circuit system 1 'includes an audio interface (AUI) 2, a high frequency interface (HFI) 3, an image processor 4', a memory 5, and a liquid crystal controller / driver (LCD-CDR) 6 'as a display drive control circuit, a still image. • Text system • I / O bus interface (SS / IF) 7 etc. Reference numeral 9 is a microphone (M / C), 10 is a speaker (S / P), 12 is an antenna (ANT), and 13 is a liquid crystal panel (liquid crystal display: LCD).

  The image processor 4 'includes a digital signal processor (DSP) 411, a baseband processor 41 having an ASIC 412 and a microcomputer MPU. An audio interface (AUI) 2 controls the input of audio from the microphone 9 and the output of audio to the speaker 10.

  For display on the liquid crystal panel 13, the image data is read from the memory 5, the necessary processing is performed by the microcomputer MPU 413, and the liquid crystal controller / driver using the still image / text / system / I / O bus / interface SS / IF7. (LCD-CDR) The data is written to the display RAM in 6 '. In the moving image display mode, 10 to 15 screens (frames) are rewritten per second. In this system, a system / I / O bus represented by an 80-system interface is used. Hereinafter, the still image / text / system / I / O bus interface (SS / IF) 7 may be abbreviated as the system interface 7.

  The display operation by the liquid crystal controller / driver (LCD-CDR) 6 'is performed by a built-in clock in the driver. For this reason, the writing of image data and the display operation are performed completely asynchronously.

  FIG. 22 is an explanatory diagram schematically showing an example of the screen update operation when moving images are displayed in the system shown in FIG. FIG. 22 shows a display screen of a mobile phone, and shows a state in which a moving picture (Motion picture) is displayed in a still picture (Still picture) display area. This drawing display is the same in the following drawings. The writing of the image data into the display RAM in the liquid crystal controller / driver (LCD-CDR) 6 'is performed completely irrespective of the display operation. As described above, since the writing of the image data and the reading of the image data for display on the liquid crystal panel LCD are performed independently (asynchronously), from the moving picture 1 (Moving picture 1) shown in FIG. The screen update to the moving picture 2 (Moving picture 2) of (c) may be performed from the middle of the screen as shown in (b) of FIG.

  When the moving image is updated from the middle of the screen, the moving image 1 (Moving picture 1) and the moving image 2 (Moving picture 2) coexist in the same display and are updated. For this reason, as shown in FIG. 22B, the boundary between the moving image 1 and the moving image 2 being displayed is conspicuous, and it may be visually recognized as flickering on the screen, which is not preferable from the viewpoint of display quality. . As described above, it is difficult to display a moving image with high quality only by using a still image / text / system / I / O bus / interface SS / IF. In order to display a moving image, it is necessary to write image data in synchronization with the display operation.

  FIG. 23 is a block diagram illustrating a configuration example of the liquid crystal controller / driver and its peripheral circuits in the system shown in FIG. A liquid crystal controller / driver (LCD-CDR) 6 ′ includes a write address generation circuit 61, a display address generation circuit 62, a display memory (M) 63 which is a bitmap image memory composed of RAM, a liquid crystal drive circuit (DR) 64, A built-in clock generation circuit (CLK) 65 is included. Display data (DB17-0) from the baseband processor 41 of the image processor 4 'is written into the built-in display memory M from the system interface (SS / IF) 7.

  The write address at this time is generated by the write address generation circuit (SAG) 61 based on the system interface signal CS (chip select) and RS (register select) WR (write). In the display operation, display data is read from the display memory (M) 63 in accordance with the display address generated by the display address generation circuit (DAG). The display address generation is performed in synchronization with the clock generated by the built-in clock generation circuit (CLK) 65. The operation by the built-in clock and the operation by the system interface (SS / IF) 7 are performed completely unrelated (asynchronously).

  FIG. 24 is a schematic diagram for explaining how the moving image is updated on the screen of the mobile phone using the liquid crystal controller / driver of the system shown in FIG. The display readout line (scanning line: pixel selection line) LR by the display operation is sequentially read from the head at a constant speed according to the built-in clock. Writing display data from the system interface (SS / IF) 7 to the memory M is performed regardless of the display operation. For this reason, the write line LW by the system interface (SS / IF) 7 may pass the display read line LR by the display operation. That is, the display write line LW and the display read line LR may cross each other.

  When the writing line and the reading line intersect as shown in FIG. 24C, the intersection changes when the display changes from the moving image display state of FIG. 24A to the moving image display state of FIG. The display flickers on the lines that are displayed. If a moving image is displayed at 15 frames per second in a screen display of 60 frames per second, the screen needs to be updated once every 4 frames. In this case, four screen updates occur per second, and four flickers occur per second. This screen flicker has been one of the problems to be solved in this type of display device.

  Further, if a configuration for avoiding screen flicker as described above is added to the liquid crystal controller / driver, the power consumption of the display device is increased, which is not preferable particularly in a portable terminal such as a cellular phone. An object of the present invention is to provide a display drive control system that reduces power consumption by suppressing power consumption due to the addition of a high-quality moving image display function without screen flicker during moving image display.

  In order to achieve the above object, the present invention uses a moving image compatible interface as a first function in addition to a system interface in a still image mode as a second function, and further supports a moving image only during a necessary period. The feature is that the power consumption is reduced by switching to the still image interface (system interface) so as to operate. The outline of the configuration example of the display drive control apparatus according to the present invention will be described as follows.

(1) An image display memory having an image data storage area for at least one frame, a still image / text / system / I / O bus interface, an external display interface for inputting moving image data from the image data processing device And a display driving circuit for supplying display data to the display device.

(2) In (1), a display operation switching register and memory access for selectively connecting display data of the still image / text / system / I / O bus interface and external display interface to writing and reading of the image display memory And a switching register.

(3) In (1), a vertical synchronizing signal input terminal for moving images is provided, and the timing of writing and reading moving image display data to and from the image display memory is controlled by a vertical synchronizing signal input from the vertical synchronizing signal input terminal. To do.

In (4), (1) to (3), an enable signal input terminal for designating an area for displaying the moving image on the screen of the display device is provided.

(5) In (1) to (3), there is provided an enable signal input terminal for designating a region for updating a part of a still image in a region for displaying the still image on the screen of the display device.

(6) A first port to which moving image data is transferred and a second port to which still image data is transferred are provided.

(7) a memory for storing image data to be supplied to the display panel;
A first port to which moving image data as the image data stored in the memory is transferred, and a second port to which still image data as the image data stored in the memory is transferred.

(8) a memory for storing image data to be supplied to the screen of the display panel, a first port to which moving image data is transferred as the image data stored in the memory, and a signal indicating the head of the screen An external signal terminal to be supplied,
The moving image data transfer is started in synchronization with the signal supplied to the external terminal.

(9) In (8), a second port to which still image data is transferred as the image data stored in the memory is further provided.

(10) a memory for storing image data to be supplied to the screen of the display panel, a port to which moving image data is transferred as the image data stored in the memory, and the moving image data in a desired area of the memory And an external terminal for receiving a signal instructing to write to.

(11) a memory for storing image data to be supplied to the display panel, a first port to which moving image data is transferred as the image data stored in the memory, and the image data stored in the memory Designate one of the second port and the moving image data supplied to the first port and the still image data supplied to the second port to transfer the image data to the memory when the still image data is transferred A first control register is provided.

(12) a clock generation circuit for generating an internal operation clock, a memory for storing image data to be supplied to the display panel, and moving image data transferred as the image data stored in the memory in synchronization with a synchronization signal A second port to which still image data is transferred as the image data stored in the memory, and a first control register for controlling a read operation of the image data from the memory. ,
The still image data supplied to the second port can be written to the memory in synchronization with the internal operation clock;
The first control register designates one of a reading operation synchronized with the synchronization signal and a reading operation synchronized with the internal clock signal for reading the image data from the memory.

  According to the display drive control device of the present invention configured as described above, high-quality moving images can be displayed, and the moving image interface and the still image interface are switched according to the display content (moving image mode / still image mode). Therefore, low power consumption can be realized.

  According to the present invention, since the update screen at the time of moving image display is synchronized with the frame, there is no flickering of the display during the update, and the number of transfer data of the display data at the time of moving image display can be reduced. It is possible to reduce power consumption in the entire system using the drive control device.

  In addition, switching between the still image / text / system / I / O bus interface and the external display interface for inputting moving image data from the image data processing device and the access to the image display memory are independently controlled. Thus, a display mode that matches the display content can be selected.

  Furthermore, by switching the corresponding interface between the moving image display mode and the still image display mode, the power consumption of the entire system can be reduced by effectively utilizing the functions of the respective interfaces.

  Embodiments of the present invention will be described below in detail with reference to the drawings of the embodiments.

  FIG. 1 is an explanatory diagram of the overall configuration of an embodiment of the present invention. An interface corresponding to a moving image (that is, a first to which moving image data is transferred) is used as a first function as an example of a display drive control device according to the present invention. 1 is a block diagram illustrating an embodiment of a drive circuit system configuration of a mobile phone having a port). The drive control device 1 includes an audio interface (AUI) 2, a high frequency interface (HFI) 3, an image processor 4 as an image data processing device, a memory 5 as an image display memory, and display drive control similar to those shown in FIG. A liquid crystal controller / driver (LCD-CDR) 6 as a circuit, a still image / text / system / I / O bus interface (SS / IF) 7 as a second function (that is, a first image data is transferred) 2 ports).

  The memory 5 is a frame memory (bitmap memory) that stores display data for at least one frame of an image, and is hereinafter also referred to as a graphic RAM. In the description of the embodiment, the still image / text / system / I / O bus interface (SS / IF) 7 may be described as the system interface 7 or the moving image interface.

  The image processor 4 includes a video signal processor (MPEG) 421 and a liquid crystal display controller (LCDC) 422 in addition to a digital signal processor (DSP) 411, an ASIC 412 and a baseband processor 41 having a microcomputer MPU. And an application processor (APP) 42. Reference numeral 9 is a microphone (M / C9, 10 is a speaker (S / P), 11 is a video camera (C / M), 12 is an antenna (ANT), and 13 is a liquid crystal panel (liquid crystal display: LCD). The ASIC 412 has peripheral circuit functions necessary for other mobile phone system configurations, and the image processor 4 may be formed on a single semiconductor substrate (chip) such as single crystal silicon, or the base hand processor 41. Each of the application processors 42 may be formed on one semiconductor substrate (chip).

  The baseband processor BBP generally provided in the mobile phone system shown in FIG. In addition to this baseband processor BBP, a sub MPU called an application processor (APP) is known. The application processor (APP) 42 in FIG. 1 incorporates an MPEG processor (MPRG) 421 for performing MPEG moving image processing and the like. The application processor (APP) 42 transfers image data to the liquid crystal controller / driver (LCD-CDR) 6 through the moving image interface (MP / IF) 8. Still image display data and text display data are transferred to the liquid crystal controller / driver (LCD-CDR) 6 via the system interface (SS / IF) 7 as in the system shown in FIG.

  FIG. 2 is a schematic diagram for explaining a state of screen update of a moving image on a display screen of a mobile phone using an embodiment of the display drive control apparatus of the present invention. In the moving image interface MP / IF8, a display operation is performed by synchronization signals (vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, dot clock DOTCLK) necessary for the display operation, and display data signals (for example, 18 described later) are synchronized with the display operation. Display data is written in the display memory (built-in RAM: M) 63 of the liquid crystal controller / driver (LCD-CDR) 6 by a bit: PD17-PD0 (hereinafter referred to as PD17-0) and a data enable signal (ENABLE). Thus, the screen update from the screen display of FIG. 2A to the screen display of FIG. 2B is performed from the top of the screen, and switching from the middle of the screen does not occur.

  FIG. 3 is a block diagram for explaining the moving image display operation using the moving image interface of the circuit configuration of the liquid crystal controller / driver according to the present invention and related circuits. In the figure, the same reference numerals as those in FIG. 1 correspond to the same functional parts. The liquid crystal controller / driver (LCD-CDR) 6 is formed on a single semiconductor substrate (chip) such as single crystal silicon by a known CMOS manufacturing process, and includes a write address generation circuit (SAG) 61, a display address, and the like. A generation circuit (DAG) 62, a display memory (M) 63, and a liquid crystal drive circuit (DR) 64 are included. The display data is written from the data bus (PD17-0). The write address WA at this time is generated by the write address generation circuit (SAG) 61 based on the dot clock DOTCLK and the enable signal ENABLE in the moving image interface signals (VSYNC, HSYNC, DOTCLK, ENABLE).

  That is, the write address generation circuit (SAG) 61 has a counter that counts the dot clock DOTCLK according to the active level of the enable signal ENABLE, and the output of the counter is used as the write address WA. The enable signal ENABLE is set to the active level at the beginning of the moving image display area and is set to the inactive level at the end of the moving image display area. The counter of the write address generation circuit 61 is reset at the active level of the enable signal ENABLE, and starts counting the dot clock DOTCLK.

  As shown in FIG. 2, when the moving image display area is displayed in the center portion of the display panel, the liquid crystal controller / driver 6 has a register for storing the first address and the last address of the portion corresponding to the moving image area of the display memory. Provided. In this case, the output of the counter in the write address generation circuit 61 is added to the head address to become a write address.

  The display data is read from the built-in memory (M) 63 according to the display address DA generated from the display address generation circuit (DAG) 62 based on the moving image interface signal, and is given to the liquid crystal drive circuit (DR) 64. The display address generation circuit 62 is initialized with the active level of VSYNC and HSYNC, and has a counter for counting dot clocks. The output of the counter is used as the display address DA. That is, the display data write address WA and the read address DA are both generated based on the moving image interface signal.

  FIG. 4 is a schematic diagram for explaining the state of the moving image screen update on the display screen of the mobile phone using one embodiment of the display drive control system of the present invention as a display operation on the moving image interface. The display data is written from the system interface (SS / IF) 7 to the display memory (M) 63 according to the dot clock DOTCLK and the enable signal ENABLE from the moving image interface (MP / IF) 8 in FIG.

  The display data is read according to the moving image interface signal (VSYNC, HSYNC, DOTCLK). The writing of image data and the reading of display are performed with the same constant speed because they operate based on the same signal. In FIG. 4A, LR indicates a display data read line, and LW indicates a display data write line. In addition, LEND in FIG. 4C indicates the last line.

  Time t0 indicates the screen start line display time, and time t1 indicates the screen last line display start time. As a result, the writing and display reading of the display data do not pass each other during one-screen display, so that there is no boundary between the moving image 1 and the moving image 2 as described in FIG. 23 and the screen flickers. Absent. It is only necessary that the write address and the display read address are always kept at an interval of one line or more.

  In FIG. 4, although it appears that a write operation and a read operation to the memory displayed at the same time are occurring, the write operation is actually performed in the first half in one operation cycle, and the read operation is performed in the second half. I want to be understood. However, when the display memory 63 is a two-port memory having a write port and a read port, it is possible to perform a write operation and a read operation simultaneously.

  Next, the still image display mode will be described. FIG. 5 is an explanatory view of the configuration and operation of a liquid crystal controller / driver that does not have a moving image interface and a built-in memory for explaining the effects of the embodiment of the present invention. FIG. 6 is a schematic diagram for explaining how still images are displayed by the liquid crystal controller / driver of FIG. The liquid crystal controller / driver (LCD-CDR) 6 has a line memory (LM) 63 ′ as the memory M.

  In this configuration, since there is no RAM memory such as a bitmap memory, even in the still image display mode, as shown in FIGS. 6A, 6B,. • It must continue to be transferred to the driver (LCD-CDR) 6. Therefore, it is difficult to reduce the power consumption due to the power of data transfer. In addition, since the transfer data is different for each screen in the moving image display, the circuit of the present invention (see FIG. 3) that can be written in synchronization with the display operation is effective.

  FIG. 7 is a diagram for explaining the configuration and operation of a liquid crystal controller / driver that performs data transfer using a system interface and a built-in memory for comparing and explaining the effects of the embodiment of the present invention. FIG. 8 is a schematic diagram for explaining how still images are displayed by the liquid crystal controller / driver of FIG. In the configuration shown in FIG. 7, a bitmap memory (M) 63 that is a RAM memory similar to that in FIG.

  As shown in FIG. 8, after the image data for one screen is written in the built-in memory (M) 63, the still image data is transferred again to read the data in the memory (M) 63 by the built-in clock. There is no need to do. For this reason, power consumption in data transfer can be reduced. Based on this concept, in the embodiment of the present invention, the configuration shown in FIG. 7 is used in the still image display mode, and the configuration shown in FIG. 5 is made to function in the moving image display mode. For switching between the still image display mode and the moving image display mode, a register described later is provided, and the mode is switched according to the state of this register.

  FIG. 9 is an explanatory diagram of merits and demerits showing the structure of the present invention in comparison with the structure of FIG. 7 and the structure of FIG. In FIG. 9 (1), that is, the configuration including only the system interface and the display memory (RAM), since the display memory (RAM) is built in, the image display mode can be selected from the still image display mode and the moving image display mode. The amount of display data transferred can be minimized. However, the flickering of the display screen as described with reference to FIGS. 20 to 23 occurs.

  In the configuration of (2) in FIG. 9, that is, a configuration including a moving image interface and a line memory, it is possible to display a screen without flickering, but power consumption is required because constant data transfer is required including still image display. Therefore, it is difficult to reduce power consumption. On the other hand, according to the configuration of the embodiment of the present invention in which the built-in memory and the moving image interface shown in (3) of FIG. 9 are provided and the still image display mode and the moving image display mode are switched, the display screen is displayed. It is possible to update video without flickering and to achieve low power consumption with minimal data transfer.

  Next, a description will be given of a specific system configuration and operation for realizing switching of each display mode between the moving image display and the still image display in the moving image interface and the system interface according to the present invention.

  FIG. 10 is an explanatory diagram of a circuit configuration of a driver chip that embodies a liquid crystal controller / driver constituting the display drive control apparatus of the present invention. Still image data, text data, etc. to the driver chip 600 are written from the baseband processor 41 to the system interface 601 and displayed on the memory of the address indicated by the internal address counter (AC) 606, ie, the graphic RAM (GRAM) 610. Written as data. This display operation is as follows. That is, based on the clock signal generated by the internal clock generation circuit (CPG) 630, the timing generation circuit 622 generates the timing and display address necessary for the display operation.

  Display data is read from the graphic RAM (GRAM) 610 at this timing and display address, converted to a voltage level necessary for liquid crystal display, and sent to the liquid crystal panel. Switching between the moving image display mode and the still image display mode is performed by a display operation switching register (DM) 621 and a RAM access switching register (RM) 605.

  In the moving image display mode, moving image display data (PD17-0), vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, dot clock DOTCLK, and data enable signal ENABLE are input from the application processor 42 to the external display interface 620. The display operation switching register (DM) 621 switches the timing in the timing generation circuit 622 from the built-in clock reference to the synchronization signal (VSYNC, HSYNC), and generates a necessary timing signal. The timing generation circuit 622 includes the display address generation circuit shown in FIG. 3, but is not described in order to avoid complexity of the drawing.

  The RAM access switching register (RM) 605 switches the operation of the write address counter (AC) 606 to a signal generated from the dot clock DOTCLK and the data enable signal ENABLE. Then, the data bus to the graphic RAM (GRAM) 610 is switched to display data (PD17-0). Thus, the display operation and the RAM access operation are switched from the system interface 601 and the internal clock generation circuit (CPG) 630 to the external display interface module 620 that is a moving image interface.

  In FIG. 10, reference numeral 602 is a gate driver interface (serial), 603 is an index register (IR), 604 is a control register (CR), 607 is a bit operation circuit that performs arithmetic processing in units of bits, and 608 is read. A (read) data latch circuit 609 is a write data latch circuit. Reference numerals 623, 624 and 626 are latch circuits, 625 is an AC circuit, 627 is a drive circuit, and constitutes a display drive circuit (here, a liquid crystal drive circuit) 64. Reference numeral 640 denotes a gamma (γ) adjustment circuit, and reference numeral 650 denotes a gradation voltage generation circuit, which constitutes a display data processing circuit for the liquid crystal panel. Note that the bit operation circuit 607 performs arithmetic processing in units of bits and rearrangement operations in units of bits, and can be omitted if this function is not required.

  Next, the details of the system interface and application interface switching registers will be described. Table 1 shows the mode setting state of the RAM access switching register (RM) 605 described with reference to FIG. In Table 1, this register is expressed as a RAM access mode register.

  Table 2 also shows the mode setting state of the display operation switching register (DM) 605 described with reference to FIG. In Table 2, this register is represented as a display operation mode register.

Table 3 is an explanatory diagram of various display operation mode states according to the combination setting of the RAM access switching register (RM) and the display operation switching register (DM).

  As shown in Table 1, the RAM access switching register (RM) sets switching of an interface for accessing the built-in display memory (graphic RAM) GRAM. The setting of the RAM access switching register (RM register) will be described in “RM setting state”. When “RM = 0”, display data can be written into the memory GRAM only from the system interface. When “RM = 1”, writing to the memory GRAM is possible only from the application interface (moving image interface, RGB interface in Table 1).

  The display operation switching register (DM register) shown in Table 2 is a 2-bit setting, and switches the display operation mode. This DM register setting will be described in “DM setting state”. When “DM = 00”, a display operation is performed using a built-in clock. When “DM = 01”, the display operation is performed by the moving image interface (RGB interface). When “DM = 10”, the display operation is performed by the VSYNC interface, and the display operation is performed only by the VSYNC signal and the built-in block at the time of the RGB interface. Note that the setting of “DM = 11” is prohibited.

  As described above, the switching of the interface is controlled independently using the two registers (RAM register and DM register) of the RAM access switching register and the display operation switching register. As summarized in Table 3, it is possible to operate in various display modes by switching the display operation in the setting state of the two registers. In Table 3, “DM setting state” is represented as (DM1-0 = 00).

  FIG. 11 is a diagram for explaining the configuration and operation of an embodiment of a liquid crystal controller / driver that includes a system interface and an application interface and performs data transfer using a built-in memory. FIG. 12 is a schematic diagram for explaining how still images are displayed by the liquid crystal controller / driver of FIG. In this embodiment, both a system interface (baseband interface) 41 for inputting still image data and the application interface 42 which is a moving image interface have their data stored in a built-in RAM memory (display memory M) 63 as a display memory. Stored in

  The vertical synchronization signal VSYNC is a timing signal indicating the head of the display operation, the horizontal synchronization signal HSYNC is a timing signal indicating the line cycle of the display operation, and the dot clock DOTCLK is a clock in units of pixels, and is based on the moving image interface, that is, the application interface (APP) 42 This is the reference clock for display operation. The dot clock DOTCLK also serves as a write signal for the display memory (M) 63. The application processor 42 transfers image data in synchronization with the dot clock DOTCLK. The enable signal ENABLE is a signal indicating that each pixel data is valid. Only when the enable signal ENABLE is valid, the transfer data is written into the display memory (M) 63.

  That is, as shown in FIG. 12, the moving image display data PD17-0 is displayed in the moving image display area MPDA in which the enable signal ENABLE is valid in the RAM data display area (still image display area) SSDA of the screen. Is done. Note that a back porch period (BP3-0) and a front porch period (FP3-0) are provided above and below the screen, and a display period (NL4-0) is provided therebetween.

  FIG. 13 is an explanatory diagram showing the switching operation between the system interface and the application interface in the state of the display screen. The still image FS is displayed by the operation of the system interface, and the moving images MP1, MP2,... MP10,. In a mobile phone, the time for displaying a moving image should be less than the time for displaying. For this reason, at the time of displaying a still image occupying the majority, “system interface + display by internal clock” enables operation with low power consumption.

  Then, only when displaying a moving image, the application interface (moving image interface) is enabled by switching the registers (RM, DM) as described above. As a result, it is possible to minimize the usage period of the interface that uses the data transfer power and to reduce the power consumption of the entire system. It should be noted that the instruction setting of this system, including register settings, is possible only from the system interface. However, instruction setting via another route may be performed.

  FIG. 14 is an explanatory diagram of Embodiment 2 of the present invention, and is a block diagram for explaining a circuit configuration for executing a moving image buffering operation. In the image display system described with reference to FIGS. 5 and 6, display is performed by sequentially storing display data in a line memory when displaying a moving image (when using an application interface). For this reason, it is necessary to continuously transfer display data. In this embodiment, even when the moving image interface (application interface (APP) 42) is used, all display data is stored in the RAM memory (M) 63, and the stored display data is input by the moving image interface (63). Reading is performed in accordance with signals (VSYNC, HSYNC, DOTCLK, ENABLE), and output to the liquid crystal panel to display it. The access mode register (RM register) 605 switches the access to the built-in RAM memory (M) 63.

  FIG. 15 is a schematic diagram for explaining the state of transfer of moving image data in the moving image buffering operation with the circuit configuration of FIG. In the moving image display using only the line memory as described in FIG. 5, the moving image data must be transferred at all times. In the current mobile phone system, the number of frames (frames) per second when displaying a moving image is 10-15. For this reason, when the number of display frames per second is 60 frames, the screen is updated once every four frames. That is, the same screen is displayed for the four frame periods.

  If a moving picture on a current mobile phone is performed with the configuration described with reference to FIGS. 5 and 6, data transfer must be performed over the same frame display period of 4 frames, so that power consumption increases due to the data transfer. In this embodiment, since moving image buffering for storing all moving image data in the built-in RAM memory is performed, data transfer is performed only when the screen is updated, and display data in the built-in memory is updated. In the subsequent display period of the same screen, the display data stored in the memory is read and displayed without performing data transfer from the system side. As a result, the number of transfer times of the moving image data is reduced to ¼ compared to the conventional case at the moving image 15 frames / second and the frame frequency of 60 Hz in the above example.

  The present invention transfers the moving image data only to the selected area of the moving image data display area when the moving image display area MPDA is inserted into the RAM data display area (still image display area) SSDA of the screen as described above. You can also. FIG. 16 is a block diagram for explaining an embodiment of a circuit configuration for realizing moving image transfer according to the present invention. FIG. 17 is a schematic diagram for explaining how still images are displayed only in selected areas by the liquid crystal controller / driver of FIG.

  When moving image buffering is not used, it is necessary to always transfer display data from the moving image interface including the still image display area SSDA other than the moving image display area MPDA when displaying a moving image using a part of the liquid crystal panel. For this reason, the number of data transfers increases and power consumption increases. In the selected area transfer method of this embodiment, only display data in the moving picture display area MPDA can be transferred as display data transferred from the moving picture interface.

  In the selected area transfer method, still image data is written in advance in the display memory, and display data is written from the moving image interface only in the portion of the display memory designated by the ENABLE signal. As a result, the still image and the moving image are synthesized on the display memory, and simultaneously read out during the display operation and displayed on the liquid crystal panel 13. As described above, according to this embodiment, the moving image display area can be selectively specified, and moving image display can be performed with the minimum data transfer corresponding to the moving image area, thereby reducing power consumption during data transfer. can do. Note that the above is not limited to a display device of a mobile phone, and can be similarly applied to a large-size display device such as a personal computer or a display monitor.

  FIG. 18 is a comparative explanatory view of the number of moving image data transfers in each of the data transfer methods for explaining the effect of the present invention. FIG. 18 shows a comparison between liquid crystal display devices having a liquid crystal panel size of 176 × 240 dots, a moving image size of QCIF size (144 × 176 dots), a moving image frame rate of 15 frames / second (fps), and a frame frequency of 60 Hz. Is. As can be seen from FIG. 18, (a) 176 × 240 × 60 frames = 2.5M times transfer / second in the case of only the moving image interface (no built-in memory), (b) 176 × 240 × 15 frames in the moving image buffering method. = 633 k times transfer / second, (c) In the moving image buffering method + selected moving image area transfer method, 144 × 176 × 15 frames = 380 k times transfer / second.

  Therefore, the data transfer amount is reduced by about 25% in the case of (b) moving image buffering method (a) only with the moving image interface, and (c) moving image buffering method + selected moving image area transfer method is (a) moving image A reduction of about 15% is possible compared to the case of only the interface.

  FIG. 19 is an explanatory diagram of Embodiment 3 of the present invention, and is a schematic diagram for explaining a display rewriting method for a still image area during moving image display. As described in detail with reference to FIG. 10, the liquid crystal controller / driver of the present invention is capable of switching between the still image interface and the moving image interface with a register, and capable of moving image buffering as described in FIG. Thus, it is possible to rewrite the display of the still image area during the moving image display.

  As shown in FIG. 19, it is necessary to update the icon mark (clock, radio wave status) and the like on the mobile phone even when a moving image is displayed on the display screen. Here, an example is shown in which the incoming mail display SIS is displayed in the still image display area of the screen. The display data is rewritten by the video buffering method when the screen is updated. In other periods, only the display operation is performed. As described above, the still image display mode and the moving image display mode are performed by registers (display operation switching register (DM), RAM access switching register (RM)). Further, this switching can be performed independently between the display operation and the access to the memory.

  For this reason, in this embodiment, as shown in the operation waveform of FIG. 19, the RAM access switching register (RM) is set to “= 0” for the RAM access only in the period other than the time of updating the moving image display screen. Switch and update the display data in the still image display area. At the end of the still image display area update period TS, the RAM access switching register (RM) is set to “= 1”. In the still image display area update period TS, the display operation switching register (DM) is set to “= 1” and the display is continued from the moving image interface. As a result, the still image display area can be updated even during moving image display, and a more flexible display mode can be realized.

  FIG. 20 is an explanatory diagram of Embodiment 4 of the present invention, and is a block diagram for explaining a configuration example of a liquid crystal controller / driver and its peripheral circuits when the VSYNC interface shown in Tables 2 and 3 is adopted. Then, the write address generation circuit (SAG) that controls the writing of the memory (M) is controlled from the system interface 7 and the address generation timing of the display address generation circuit (DAG) that controls the reading of the memory (M) is controlled. The application processor 42 is controlled by the vertical synchronization signal VSYNC.

  In this case, the display address generation circuit (DAG) has a counter that is reset at the VSYNC active level and counts the clock signal generated from the built-in clock circuit CLK, and the output of this counter is used as the display address DA. In the case of this configuration, it is possible to display moving image data with almost no change to the conventional system. The moving image data writing speed from the system interface 7 side needs to be sufficiently faster than the display operation based on the clock signal from the built-in clock generation circuit CLK. Other configurations and operations are the same as those described in FIG.

  In the configuration of this embodiment, by controlling the start point of reading of display data written by the vertical synchronization signal VSYNC from the application processor 42 to the display memory (M), the image display is set to the screen scanning timing. It can be synchronized, and the image is not updated from the middle of the screen. Therefore, flickering of the screen during the screen update does not occur.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited to the configurations of the above embodiments, and various modifications can be made without departing from the technical idea of the present invention. Needless to say.

It is explanatory drawing of the whole structure of Example 1 of this invention. It is a schematic diagram explaining the mode of the screen update of the moving image in the display screen of a mobile telephone using the structure of Example 1 of the display drive control apparatus of this invention. FIG. 3 is a block diagram illustrating a circuit configuration of a liquid crystal controller / driver according to the present invention and related circuits. It is a schematic diagram explaining the state of the screen update of the moving image on the display screen of the mobile phone using the configuration of Example 1 of the display drive control apparatus of the present invention as the display operation on the moving image interface. It is explanatory drawing of the structure and operation | movement of a liquid crystal controller / driver which do not have a moving image interface and a built-in memory for comparing and explaining the effect of the Example of this invention. It is a schematic diagram explaining the mode of the still image display by the liquid crystal controller / driver of FIG. It is explanatory drawing of the structure and operation | movement of a liquid crystal controller driver which performs the data transfer by a system interface and built-in memory for comparing and explaining the effect of the Example of this invention. It is a schematic diagram explaining the mode of the still image display by the liquid crystal controller / driver of FIG. It is explanatory drawing of the merit and demerit which show the structure of this invention compared with the structure of FIG. 7, and the structure of FIG. It is explanatory drawing of the circuit structure of the driver chip which actualized the liquid crystal controller driver of this invention. It is explanatory drawing of the structure of the Example of the liquid crystal controller driver which has a system interface and an application interface, and performs the data transfer by built-in memory, and its operation | movement. It is a schematic diagram explaining the mode of the still image display by the liquid crystal controller / driver of FIG. It is explanatory drawing which showed the switching operation of a system interface and an application interface in the state of the display screen. It is explanatory drawing of Example 2 of this invention. It is a schematic diagram explaining the mode of transfer of the moving image data in the moving image buffering operation | movement by the circuit structure of FIG. It is a block diagram explaining one Example of the circuit structure which implement | achieves the moving image transfer by this invention. FIG. 17 is a schematic diagram illustrating a state of still image display only on a selected region by the liquid crystal controller / driver of FIG. 16. It is comparison explanatory drawing of the moving image data transfer number of each said data transfer system for demonstrating the effect of this invention. It is explanatory drawing of Example 3 of this invention. It is explanatory drawing of Example 4 of this invention. It is a block diagram explaining an example of the system configuration | structure of the drive circuit apparatus of the mobile telephone which does not have the interface corresponding to a moving image which is an example of the display drive control apparatus examined by this inventor before this invention. It is explanatory drawing which shows typically the operation example of the screen update at the time of the moving image display by the system configuration | structure shown in FIG. FIG. 22 is a block diagram illustrating a configuration example of a liquid crystal controller / driver and its peripheral circuits in the system configuration shown in FIG. 21. FIG. 24 is a schematic diagram for explaining how a moving image is updated on a screen of a mobile phone using a liquid crystal controller / driver in the system configuration shown in FIG. 23.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Drive control circuit apparatus, 2 ... Voice interface (AUI) 3 ... High frequency interface (HFI), 4 ... Image processor which is an image data processing device, 41 ... Baseband processor with microcomputer MPU, 411... Digital signal processor (DSP), 412... ASIC, 42... Application processor (APP), 421. (MPEG), 422... Liquid crystal display controller (LCDC), 5... Image display memory, 6... Liquid crystal controller driver (LCD-CDR) as a display drive control circuit, 7.・ Still image ・ Text system ・ I / O bus interface (SS / IF), Movie interface (MP / IF) , 9... Microphone (M / C), 10... Speaker (S / P), 11... Video camera (C / M), 12. ... liquid crystal panel (liquid crystal display: LCD), 621 ··· display operation switching register (DM), 605 ··· RAM access switching register (RM).

Claims (29)

A liquid crystal drive control device formed on a semiconductor chip,
A first data terminal to which video data is supplied;
A first terminal to which a vertical synchronization signal is supplied;
A second terminal to which a horizontal synchronizing signal is supplied;
A third terminal to which a dot clock is supplied;
A fourth terminal to which an enable signal is supplied;
A second data terminal to which still image data is supplied;
A clock generation circuit for generating an internal operation clock signal;
An external display interface circuit to which the first data terminal and the first terminal to the fourth terminal are connected;
A system interface circuit to which the second data terminal is coupled;
A memory for storing image data to be displayed on a display panel to be coupled to the liquid crystal drive control device;
A drive circuit coupled to the memory and supplying image data to the display panel in accordance with image data read from the memory;
When reading the image data from the memory, one of a first read operation synchronized with the internal operation clock signal and a second read operation synchronized with the vertical synchronization signal, the horizontal synchronization signal, and the dot clock is performed. A first register that can be specified;
When writing the image data to the memory, a first write operation for writing still image data supplied to the system interface circuit via the second data terminal to the memory, and the above-mentioned via the first data terminal. A second register capable of designating one of a second write operation for writing the moving image data supplied to the external display interface circuit to the memory;
A liquid crystal drive control device. In claim 1,
The enable signal has an active state and an inactive state,
The liquid crystal drive control device, wherein the moving image data supplied to the external display interface circuit via the first data terminal is written into the memory according to the active state of the enable signal. The claim 1, further comprising:
A liquid crystal drive control apparatus comprising a third register for designating a start address and a final address of an area in which the moving image data is written in the memory. In claim 1,
The liquid crystal drive control device, wherein the first register and the second register are set by a command supplied to the system interface circuit via the second data terminal. A first data terminal coupled to receive the video data;
A first terminal coupled to receive a vertical synchronization signal;
A second terminal coupled to receive a horizontal synchronization signal;
A third terminal coupled to receive a dot clock;
A fourth terminal coupled to receive the enable signal;
A second data terminal coupled to receive still image data;
A clock generation circuit for generating an internal clock signal;
A first interface circuit coupled from the first data terminal and the first terminal to the fourth terminal;
A second interface circuit coupled to the second data terminal;
A memory for storing image data to be displayed on the display panel;
A source driver coupled to the output of the memory and for supplying image data to the display panel based on the image data read from the memory;
A first state in which the memory can be read in synchronization with the internal clock signal, and a second state in which the memory can be read in synchronization with the vertical synchronization signal, horizontal synchronization signal, and dot clock. A first register section that can be set to
A first state in which the still image data supplied to the second interface circuit via the second data terminal can be written to the memory; and the first interface circuit via the first data terminal to the memory. A liquid crystal drive control device comprising: a second register unit capable of setting a second state in which the moving image data supplied to the second data can be written. In claim 5,
The enable signal has an active state and an inactive state,
The liquid crystal drive control device, wherein the moving image data supplied to the first interface circuit via the first data terminal is written to the memory during the active state of the enable signal. In claim 5, further:
A liquid crystal drive control apparatus having a third register unit for designating a start address and a final address of an area in which the moving image data is written in the memory. In claim 7,
The liquid crystal drive control device, wherein the first register unit, the second register unit, and the third register unit are set by a command supplied to the second interface circuit via the second data terminal. In claim 5,
The first register unit further has a third state in which the memory can be read in synchronization with the vertical synchronization signal and the internal clock signal,
A liquid crystal drive control device in which moving image data supplied to the second interface circuit via the second data terminal is written into the memory when the first register unit is in the third state. In claim 9,
The enable signal has an active state and an inactive state,
A liquid crystal drive control device in which the moving image data supplied to the first interface circuit via the first data terminal is written to the memory when the enable signal is in the active state. The claim 10, further comprising:
A liquid crystal drive control apparatus having a third register unit for designating both a start address and a final address of an area in which the moving image data is written in the memory. A first data terminal coupled to receive video data, a first terminal coupled to receive a vertical synchronization signal, a second terminal coupled to receive a horizontal synchronization signal, and a dot clock A first interface circuit having a third terminal coupled to and a fourth terminal coupled to receive the enable signal;
A second interface circuit having a second data terminal coupled to receive still image data;
A clock generation circuit for generating an internal clock signal;
A memory for storing image data to be displayed on the display panel;
A source driver coupled to the output of the memory and for supplying image data to the display panel based on the image data read from the memory;
A first state in which the memory can be read in synchronization with the internal clock signal, or a second state in which the memory can be read in synchronization with the vertical synchronization signal, horizontal synchronization signal, and dot clock. A first register having a state;
A first state in which the still image data supplied to the second interface circuit via the second data terminal can be written to the memory, or the first interface via the first data terminal to the memory. A liquid crystal drive control device comprising: a second register having a second state in which the moving image data supplied to the circuit can be written. In claim 12,
The first register further has a third state that allows the memory to be read in synchronization with the vertical synchronization signal and the internal clock signal;
A liquid crystal drive control device in which the second moving image data supplied to the second interface circuit via the second data terminal is written to the memory when the first register is in the third state. In claim 12,
The enable signal has an active state and an inactive state,
A liquid crystal drive control device in which the moving image data supplied to the first interface circuit via the first data terminal is written to the memory when the enable signal is in the active state. The claim 13, further comprising:
A liquid crystal drive control device having a third register for designating both a start address and a final address of an area in which the moving image data is written in the memory. A first data terminal coupled to receive video data, a first terminal coupled to receive a vertical synchronization signal, a second terminal coupled to receive a horizontal synchronization signal, and a dot clock A first interface circuit having a third terminal coupled to and a fourth terminal coupled to receive the enable signal;
A second interface circuit having a second data terminal coupled to receive still image data;
A clock generation circuit for generating an internal clock signal;
A memory for storing image data to be displayed on the display panel;
A source driver coupled to the output of the memory and for supplying image data to the display panel based on the image data read from the memory;
A first state in which the memory can be read in synchronization with the internal clock signal, or a second state in which the memory can be read in synchronization with the vertical synchronization signal, horizontal synchronization signal, and dot clock. A first register whose state can be set;
A first state in which the still image data supplied to the second interface circuit via the second data terminal can be written to the memory, or the first interface via the first data terminal to the memory. And a second register capable of setting a second state in which the moving image data supplied to the circuit is writable. In claim 16,
The first register can further set a third state that enables the memory to be read in synchronization with the vertical synchronization signal and the internal clock signal.
A liquid crystal drive control device in which the second moving image data supplied to the second interface circuit via the second data terminal is written to the memory when the first register is in the third state. The claim 17, further comprising:
A liquid crystal drive control apparatus comprising a third register capable of designating both a start address and a final address of an area in which the moving image data is written in the memory. A first data terminal coupled to receive video data, a first terminal coupled to receive a vertical synchronization signal, a second terminal coupled to receive a horizontal synchronization signal, and a dot clock A first interface circuit having a third terminal coupled to and a fourth terminal coupled to receive the enable signal;
A second interface circuit having a second data terminal coupled to receive still image data;
A clock generation circuit for generating an internal clock signal;
A memory for storing image data to be displayed on the display panel;
A source driver coupled to the output of the memory and for supplying image data to the display panel based on the image data read from the memory;
A first state in which the memory can be read in synchronization with the internal clock signal; a second state in which the memory can be read in synchronization with the vertical synchronization signal, horizontal synchronization signal and dot clock; Or a first register capable of setting a third state that allows the memory to be read in synchronization with the vertical synchronization signal and the internal clock signal;
A first state in which the still image data supplied to the second interface circuit via the second data terminal can be written to the memory, or the first interface via the first data terminal to the memory. And a second register capable of setting a second state in which the moving image data supplied to the circuit is writable. In claim 19,
A liquid crystal drive control device in which the second moving image data supplied to the second interface circuit via the second data terminal is written to the memory when the first register is in the third state. In claim 19,
The enable signal has an active state and an inactive state,
A liquid crystal drive control device in which the moving image data supplied to the first interface circuit via the first data terminal is written to the memory when the enable signal is in the active state. In claim 19, further:
A liquid crystal drive control apparatus comprising a third register capable of designating both a start address and a final address of an area in which the moving image data is written in the memory. A first data terminal coupled to receive the video data;
A first terminal coupled to receive a vertical synchronization signal;
A second terminal coupled to receive a horizontal synchronization signal;
A third terminal coupled to receive a dot clock;
A fourth terminal coupled to receive the enable signal;
A second data terminal coupled to receive still image data;
A clock generation circuit for generating an internal clock signal;
A first interface circuit coupled from the first data terminal and the first terminal to the fourth terminal;
A second interface circuit coupled to the second data terminal;
A memory for storing image data to be displayed on the display panel;
A source driver coupled to the output of the memory and for supplying image data to the display panel based on the image data read from the memory;
A first state in which the memory can be read in synchronization with the internal clock signal, and a second state in which the memory can be read in synchronization with the vertical synchronization signal, horizontal synchronization signal, and dot clock. A first bit that can be set to
A first state in which the still image data supplied to the second interface circuit via the second data terminal can be written to the memory; and the first interface circuit via the first data terminal to the memory. And a second bit capable of setting a second state in which the moving image data supplied to can be written. In claim 23,
The enable signal has an active state and an inactive state,
The liquid crystal drive control device, wherein the moving image data supplied to the first interface circuit via the first data terminal is written into the memory during the active state of the enable signal. 24.
A liquid crystal drive control device having a third bit for designating a start address and a final address of an area in which the moving image data is written in the memory. In claim 25,
The liquid crystal drive control device, wherein the first bit, the second bit, and the third bit are set by a command supplied to the second interface circuit via the second data terminal. In claim 23,
The first bit further has a third state that allows the memory to be read in synchronization with the vertical synchronization signal and the internal clock signal;
A liquid crystal drive control device in which moving image data supplied to the second interface circuit via the second data terminal is written to the memory when the first bit is in the third state. In claim 23,
The enable signal has an active state and an inactive state,
A liquid crystal drive control device in which the moving image data supplied to the first interface circuit through the first data terminal is written to the memory when the enable signal is in the active state. 24.
A liquid crystal drive control apparatus having a third bit for designating both a start address and a final address of an area in which the moving image data is written in the memory.

Images