WO2003049290A1 - Procede de traitement de puissance numerique de modulation de surface d'impulsion et son dispositif - Google Patents
Procede de traitement de puissance numerique de modulation de surface d'impulsion et son dispositif Download PDFInfo
- Publication number
- WO2003049290A1 WO2003049290A1 PCT/CN2002/000864 CN0200864W WO03049290A1 WO 2003049290 A1 WO2003049290 A1 WO 2003049290A1 CN 0200864 W CN0200864 W CN 0200864W WO 03049290 A1 WO03049290 A1 WO 03049290A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- output
- signal
- feedback
- double
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 12
- 238000005070 sampling Methods 0.000 claims abstract description 9
- 238000001914 filtration Methods 0.000 claims abstract description 8
- 238000001208 nuclear magnetic resonance pulse sequence Methods 0.000 claims description 13
- 230000010354 integration Effects 0.000 claims description 11
- 238000001228 spectrum Methods 0.000 claims description 7
- 238000003672 processing method Methods 0.000 claims description 5
- 230000009977 dual effect Effects 0.000 claims 1
- 239000002689 soil Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2175—Class D power amplifiers; Switching amplifiers using analogue-digital or digital-analogue conversion
Definitions
- the invention relates to a pulse area modulation digital power processing method and device. Background technique
- the sampling frequency is greater than twice the highest frequency component of the signal
- the signal can be completely recovered in the sense of band limitation, and the signal power is actually output. Due to the influence of various components, drivers, power supplies, temperature and other factors, the pulse is deformed, and this deformation is unpredictable. Therefore, the distortion of this power amplifier is too large in actual use, and even reaches TDH-10 at large signals. %.
- the pulse width modulation power amplifier can theoretically reproduce accurately and without distortion amplification.
- the top of the output pulse is inclined. As shown in FIG. 2, the actually formed pulse area SQ is not equal to the PWM ideal area S 0 . This difference will occur in each pulse, which eventually results in waveform distortion. The higher the frequency and the higher the power, the more severe the distortion.
- An object of the present invention is to provide a pulse area modulation digital power processing method and device, so as to overcome the defects of the prior art.
- a pulse area modulation digital power processing method is provided.
- a signal is converted into an amplified power output through a pre-circuit, a double-limit delay comparison circuit, a driving circuit, a switching circuit, and a filtering circuit.
- the output terminal of the switching circuit samples and outputs a feedback comparison signal to the double-limit delay comparison circuit.
- the output signal of the front circuit is compared with the feedback comparison signal in a double-limit delay comparison circuit.
- the double-limit delay comparison circuit When the feedback comparison signal is greater than the upper limit value, the double-limit delay comparison circuit outputs a low level, and when the feedback comparison signal is lower than the lower limit value When the double-limit delay comparison circuit outputs a high level;
- the driving circuit is controlled by the output level of the double-limit delay comparison circuit
- the power provided by the power supply is converted from the switching circuit into an amplified pulse sequence
- the amplified pulse sequence is filtered and output through a filtering circuit, and has amplified power output consistent with the signal;
- the integration circuit samples the output of the main switch circuit to obtain a feedback comparison signal.
- a pulse area modulation digital power processing device includes: a pre-circuit, a double-limit delay comparison circuit, an integrating circuit, a driving circuit, a switching circuit, a main power source, and a filtering circuit.
- the input signal of the input terminal of the front circuit, the output of the front circuit is connected to the input of the double-limit delay comparison circuit, the output of the double-limit delay comparison circuit is connected to the input of the driving circuit, and the output of the driving circuit is connected to the switching circuit
- the input of the switching circuit is amplified by the output power of the filter circuit.
- the input of the integrating circuit is connected to the output of the main switching circuit.
- the output of the integrating circuit is fed to the double-limit delay comparison circuit. It is fed to the main switching circuit and converted there into a pulse sequence with a signal spectrum.
- the feedback signal is sampled by the integration circuit at the output end of the main switching circuit to obtain a pulse sequence signal superimposed on the output whose average pulse area is consistent with the switching signal.
- the feedback signal is input to the double-limit delay comparison circuit.
- a low level is output when the feedback comparison signal is greater than a predetermined value ⁇ of the input signal, and a high level is output when the feedback comparison signal is less than a predetermined value ⁇ of the input signal.
- Figure 1 is the working principle of pulse width modulation digital power amplifier
- Figure 2 is the distortion cause of the pulse width modulation digital power amplifier
- FIG. 3 is a block diagram of a pulse area modulation digital power processing apparatus according to a first embodiment of the present invention
- Figure 4 is a schematic diagram of the working state of a dual-limit comparison circuit
- FIG. 5 is a block diagram of a pulse area modulation digital power processing apparatus according to a second embodiment of the present invention
- FIG. 6 is a block diagram of a pulse area modulation digital power processing apparatus according to a third embodiment of the present invention. detailed description
- the pulse area modulation digital power processing device has a pre-circuit 1, a double-limit delay comparison circuit 2, an integration circuit 7, a driving circuit 3, a switching circuit 4, and a filter circuit. 6.
- the power source 5 supplies power to the switching circuit 4.
- the signal S input from the input of the pre-circuit 1 is sent to the double-limit delay comparison circuit 2 through pre-processing.
- the integration circuit 7 sends a feedback comparison signal Y to the double-limit delay comparison circuit.
- the delay comparison circuit 2 compares and determines its output state. At any instant, when the feedback comparison signal is higher than S (t) + ⁇ (see Figure 4), the output of the double-limit delay comparison circuit 2 is low level. When the comparison signal is lower than S (t)- ⁇ , the output of the double-limit delay comparison circuit 2 is high level.
- the output of the double-limit delay comparison circuit 2 controls the switching element in the switching circuit 4 through the driving circuit 3, and the power supply 5
- the provided electric power is converted into an amplified pulse output having the characteristics of the input signal S, and is filtered and processed by the filter circuit 6 and output.
- the integration circuit 7 samples from the output of the main switching circuit 4 and outputs a feedback signal Y to the double-limit delay comparison circuit.
- the feedback signal Y output by the integration circuit 7 is the average output of the actual pulse area and the signal S- The same, superimposed on the presence or absence of the pulse and the corresponding fluctuation of the pulse.
- the pulse area modulation digital power processing device has a pre-circuit 1, a double-limit delay comparison circuit 2, an integration circuit 7, a driving circuit 3, a switching circuit 4, and a feedback network. 8 and filter circuit 6, the main power supply 5 provides power to the switching circuit 4.
- the feedback network 8 is taken from the output of the main switching circuit 4 In this way, it is fed back to the input terminal of the pre-circuit 1 to form negative feedback, which improves the effect of the digital power processing.
- the pulse area modulation digital power processing device has a pre-circuit 1, a double-limit delay comparison circuit 2, an integration circuit 7, a driving circuit 3, a switching circuit 4, and a feedback network. 8 and filter circuit 6, main power supply 5 provides power to switch circuit 4.
- the feedback network 8 samples from the output terminal of the filter circuit 6 and feeds it back to the input terminal of the pre-circuit 1 to form a negative feedback to improve the effect of the digital power processing.
- Pre-circuit This circuit usually consists of a low-input impedance operational amplifier with a gain of 1 and a linear operational amplifier with a certain gain. This pre-circuit makes the thermal noise very small and can amplify the input signal. The amplified signal is sent to the subsequent double-limit delay comparison circuit.
- Double-limit delay comparison circuit This circuit is a special comparison circuit.
- the usual comparison circuit is to directly compare the feedback signal with the input signal, while the comparison circuit of the present invention is the feedback signal and the overshoot signal + ⁇ "or with the 3 ⁇ 4 input signal. - ⁇ "Compare two potentials.
- the specific structure is: when the feedback signal is increased from small, the input signal is increased by ⁇ from this circuit, the feedback signal is not directly compared with the input signal, but it is delayed to the overshoot signal + ⁇ "comparison, if it is greater than the input signal + ⁇ " , The comparison circuit outputs a low level; when the feedback signal is reduced from large, the input signal is reduced by ⁇ , the feedback signal is not directly compared with the input signal, but it is delayed until the input signal- ⁇ "is compared, if it is less than the input signal - ⁇ ", the comparison circuit outputs a high level. Because the comparison circuit must be delayed to two limits of the signal ⁇ 4 to compare the output level, the comparison circuit of the present invention can be called a double-limit delay comparison circuit. The drive circuit is controlled by the output level of the double-limit comparison circuit.
- the function of the drive circuit is to control the on or off of the switching device. It is required that the drive circuit can provide a certain current and can absorb a certain current.
- the driving circuit is usually composed of a totem pole structure, and the driving circuit outputs signals to control the switching circuit.
- Switch circuit The output of the drive circuit controls the on or off of the switch circuit.
- Commonly used switching devices include metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate transistors (IGBTs). They are field-control devices that require low driving power and fast switching speeds. Such switching devices constitute half-bridge circuits or Full-bridge circuit.
- MOSFETs metal-oxide-semiconductor field-effect transistors
- IGBTs insulated-gate transistors
- the present invention is a power amplifier, which is to efficiently convert the power of a power supply into a signal power output through a switching circuit.
- the power supply circuit is a circuit that provides DC power for this purpose.
- the filter circuit used in the present invention can be a maximum flat low-pass filter circuit, or a Chebyshev function or elliptic function filter circuit.
- Feedback network Sampling by the integration circuit at the output of the main switching circuit, the output signal averaged with the pulse area and the pulse sequence signal consistent with the switching signal can be superimposed, that is, the feedback comparison signal output by the feedback network is sent to the double limit
- the delay comparison circuit compares with the signal ⁇ .
- the + ⁇ and- ⁇ are symmetrical, and the average value of the pulse area accurately represents the signal, so the distortion can easily reach 0.1%.
- the noise distribution is wide, the average amplitude is very low, and there is no constant frequency noise like the PWM digital power amplifier.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
- Dc-Dc Converters (AREA)
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/497,482 US7405615B2 (en) | 2001-12-03 | 2002-12-03 | Method of impulse acreage modulation digital power processing and its device |
JP2003550363A JP4264354B2 (ja) | 2001-12-03 | 2002-12-03 | パルス面積変調を用いたディジタル電力処理方法及び装置 |
AU2002354336A AU2002354336A1 (en) | 2001-12-03 | 2002-12-03 | A method of impulse acreage modulation digital power processing and its device |
EP02785017A EP1463204A4 (en) | 2001-12-03 | 2002-12-03 | METHOD FOR PROCESSING DIGITAL PULSE SURFACE MODULATION POWER AND DEVICE THEREOF |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB011397861A CN1195353C (zh) | 2001-12-03 | 2001-12-03 | 脉冲面积调制数字功率处理方法及装置 |
CN01139786.1 | 2001-12-03 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003049290A1 true WO2003049290A1 (fr) | 2003-06-12 |
Family
ID=4675413
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2002/000864 WO2003049290A1 (fr) | 2001-12-03 | 2002-12-03 | Procede de traitement de puissance numerique de modulation de surface d'impulsion et son dispositif |
Country Status (6)
Country | Link |
---|---|
US (1) | US7405615B2 (zh) |
EP (1) | EP1463204A4 (zh) |
JP (1) | JP4264354B2 (zh) |
CN (1) | CN1195353C (zh) |
AU (1) | AU2002354336A1 (zh) |
WO (1) | WO2003049290A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7405615B2 (en) | 2001-12-03 | 2008-07-29 | Hutang Fang | Method of impulse acreage modulation digital power processing and its device |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101017182B1 (ko) | 2008-03-26 | 2011-02-25 | 재단법인서울대학교산학협력재단 | 펄스면적변조를 이용한 고효율 선형 전력증폭기 시스템에서이산적인 진폭을 가지는 알에프 펄스열을 고효율로증폭하는 방법 및 장치 |
KR101566987B1 (ko) | 2014-12-17 | 2015-11-06 | 래드손(주) | 펄스 면적 변조 방법 및 이를 이용하는 펄스 면적 변조기 |
TWI800846B (zh) * | 2021-06-10 | 2023-05-01 | 瑞昱半導體股份有限公司 | 訊號處理器與訊號處理方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1995034941A1 (en) * | 1994-06-10 | 1995-12-21 | Northrop Grumman Corporation | Digital pulse width modulator with integrated test and control |
WO1998044626A2 (en) * | 1997-04-02 | 1998-10-08 | Karsten Nielsen | Pulse referenced control method for enhanced power amplification of a pulse modulated signal |
WO1999020004A1 (en) * | 1997-10-09 | 1999-04-22 | Atmel Corporation | Signal processing method and device |
WO2000007291A2 (en) * | 1998-07-24 | 2000-02-10 | Toccata Technology Aps | A method of attenuating zero crossing distortion and noise in an amplifier, an amplifier and uses of the method and the amplifier |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1365878A (fr) * | 1962-08-15 | 1964-07-03 | Appareil de transmission et transformation de signaux et procédé de transmission par emploi dudit appareil ou appareil similaire | |
JPS57121308A (en) * | 1981-01-21 | 1982-07-28 | Hitachi Ltd | Power amplifier |
JPS5967719A (ja) * | 1982-10-09 | 1984-04-17 | Nippon Gakki Seizo Kk | パルス幅変調回路 |
EP0184280B1 (en) * | 1984-11-02 | 1989-08-02 | Bose Corporation | Frequency-stabilized two-state modulation |
US5160896A (en) * | 1992-02-18 | 1992-11-03 | Harman International Industries, Incorporated | Class D amplifier |
US5815581A (en) * | 1995-10-19 | 1998-09-29 | Mitel Semiconductor, Inc. | Class D hearing aid amplifier with feedback |
US6476673B2 (en) * | 2000-07-12 | 2002-11-05 | Monolithic Power Systems, Inc. | Class D audio amplifier |
CN1195353C (zh) | 2001-12-03 | 2005-03-30 | 方虎堂 | 脉冲面积调制数字功率处理方法及装置 |
-
2001
- 2001-12-03 CN CNB011397861A patent/CN1195353C/zh not_active Expired - Lifetime
-
2002
- 2002-12-03 US US10/497,482 patent/US7405615B2/en not_active Expired - Lifetime
- 2002-12-03 AU AU2002354336A patent/AU2002354336A1/en not_active Abandoned
- 2002-12-03 WO PCT/CN2002/000864 patent/WO2003049290A1/zh active Application Filing
- 2002-12-03 JP JP2003550363A patent/JP4264354B2/ja not_active Expired - Fee Related
- 2002-12-03 EP EP02785017A patent/EP1463204A4/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1995034941A1 (en) * | 1994-06-10 | 1995-12-21 | Northrop Grumman Corporation | Digital pulse width modulator with integrated test and control |
WO1998044626A2 (en) * | 1997-04-02 | 1998-10-08 | Karsten Nielsen | Pulse referenced control method for enhanced power amplification of a pulse modulated signal |
WO1999020004A1 (en) * | 1997-10-09 | 1999-04-22 | Atmel Corporation | Signal processing method and device |
WO2000007291A2 (en) * | 1998-07-24 | 2000-02-10 | Toccata Technology Aps | A method of attenuating zero crossing distortion and noise in an amplifier, an amplifier and uses of the method and the amplifier |
Non-Patent Citations (1)
Title |
---|
See also references of EP1463204A4 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7405615B2 (en) | 2001-12-03 | 2008-07-29 | Hutang Fang | Method of impulse acreage modulation digital power processing and its device |
Also Published As
Publication number | Publication date |
---|---|
JP2005512489A (ja) | 2005-04-28 |
CN1195353C (zh) | 2005-03-30 |
EP1463204A1 (en) | 2004-09-29 |
US20050069049A1 (en) | 2005-03-31 |
EP1463204A4 (en) | 2008-11-26 |
US7405615B2 (en) | 2008-07-29 |
AU2002354336A1 (en) | 2003-06-17 |
CN1402430A (zh) | 2003-03-12 |
JP4264354B2 (ja) | 2009-05-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3899074B2 (ja) | Pwm負帰還によるデジタルpwm入力d級音響増幅器 | |
TW441170B (en) | A low noise low distortion class D amplifier | |
US7202734B1 (en) | Electronically tuned power amplifier | |
US7714649B1 (en) | High-efficiency linear amplifier using non linear circuits | |
KR20240036730A (ko) | 게이트 드라이브 회로 및 그 동작 방법 | |
US20100177536A1 (en) | Dc-dc power supply apparatus method for improving dc-dc power supply apparatus | |
CN1388643A (zh) | 信号放大方法,信号放大器以及与其相关的装置) | |
US20090302943A1 (en) | Class d amplifier | |
EP0483094A2 (en) | A pulse-width modulated, linear audio-power amplifier | |
JP2003527022A (ja) | 電源から直接的に音声を得る方法と装置 | |
JPH11204850A (ja) | ピエゾ駆動回路 | |
CN111900944A (zh) | 复合并联型无死区失真音频数字功率放大器 | |
CN110113012B (zh) | 一种提高线性功率放大器效率的电路拓扑及方法 | |
CN100492891C (zh) | 数字放大器 | |
CN207939479U (zh) | 一种推挽放大电路和交越失真消除装置 | |
WO2003049290A1 (fr) | Procede de traitement de puissance numerique de modulation de surface d'impulsion et son dispositif | |
CN110138186B (zh) | 功率开关器件驱动电路及电力电子设备 | |
US6320460B1 (en) | Class D amplifier | |
US6191650B1 (en) | Class d amplifier with pulse width modulation and a very low power consumption | |
CN110932677B (zh) | 一种新型高性能线性功率放大器 | |
JP2002151979A (ja) | Pwmオーディオ増幅装置 | |
CN108233683B (zh) | 一种单相交流信号功率放大控制系统 | |
CN218386793U (zh) | SiC MOSFET的辅助关断电路及驱动电路 | |
JP3973519B2 (ja) | 増幅器 | |
CN218243484U (zh) | 一种低电压大功率数字功放 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SK SL TJ TM TN TR TT TZ UA UG US UZ VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2003550363 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2002785017 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 2002785017 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10497482 Country of ref document: US |