WO2003026856A1 - Production method of laminated ceramic electronic component and electronic apparatus - Google Patents

Production method of laminated ceramic electronic component and electronic apparatus Download PDF

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Publication number
WO2003026856A1
WO2003026856A1 PCT/JP2002/008795 JP0208795W WO03026856A1 WO 2003026856 A1 WO2003026856 A1 WO 2003026856A1 JP 0208795 W JP0208795 W JP 0208795W WO 03026856 A1 WO03026856 A1 WO 03026856A1
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WIPO (PCT)
Prior art keywords
laminate
ceramic sheet
electronic component
groove
ceramic
Prior art date
Application number
PCT/JP2002/008795
Other languages
French (fr)
Japanese (ja)
Inventor
Muneyuki Sawada
Hidenori Katsumura
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to JP2003530475A priority Critical patent/JP4211606B2/en
Publication of WO2003026856A1 publication Critical patent/WO2003026856A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481Insulating layers on insulating parts, with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards

Definitions

  • the present invention relates to a method for manufacturing a multilayer ceramic electronic component having excellent planar accuracy for mounting chip components, semiconductors, and the like, and an electronic device using the electronic component.
  • a conventional method for manufacturing a multilayer ceramic electronic component will be described. First, an organic binder and a plasticizer are mixed with glass ceramic powder to obtain a first ceramic sheet. Next, a conductor pattern is formed on the surface of the first ceramic sheet, and the first ceramic sheet is laminated. Thereafter, a second ceramic sheet that is not sintered at the firing temperature of the first ceramic sheet is laminated above and below the first ceramic sheet to obtain a laminate. Next, after a slit is formed in the first ceramic sheet on the surface of the laminate, the laminate is fired at the firing temperature of the first ceramic sheet, and the unsintered second ceramic sheet is removed. Next, the laminate is divided by slits, and a multilayer ceramic electronic component is obtained.
  • the multilayer ceramic electronic component is mounted on a circuit board having an electrode pattern on the surface, and an electronic device is manufactured.
  • the second ceramic sheet is not sintered and hardly shrinks during firing, the first ceramic sheet that shrinks by sintering is restrained. Therefore, shrinkage of the first ceramic sheet can be suppressed, and a multilayer ceramic electronic component having excellent planar accuracy can be obtained with high productivity.
  • the end of the multilayer ceramic electronic component has an acute angle. Therefore, if the circuit board is bent when the electronic component is mounted on the circuit board, the end of the circuit board comes into contact with the circuit board, causing the multilayer ceramic electronic component to crack or chip. Occurs and the characteristics deteriorate. Disclosure of the invention
  • the first ceramic sheet is sandwiched between second ceramic sheets having a higher sintering temperature than the first ceramic sheet to obtain a laminate.
  • a groove leading to the first ceramic sheet is formed in the laminate such that the second ceramic sheet covers the upper end of the groove of the first ceramic sheet.
  • the laminate is fired at a temperature at which the first ceramic sheet sinters and the second ceramic sheet does not sinter.
  • the second ceramic sheet is removed, and the laminate is divided by the grooves, thereby producing a multilayer ceramic electronic component.
  • FIG. 1 is an enlarged sectional view of a main part of a multilayer ceramic electronic component according to Embodiment 1 of the present invention.
  • FIG. 2 is an enlarged sectional view of a main part of the multilayer ceramic electronic component according to the first embodiment.
  • FIG. 3 is an enlarged sectional view of a main part of the multilayer ceramic electronic component according to the first embodiment.
  • FIG. 4 is an enlarged sectional view of a main part of the multilayer ceramic electronic component according to the first embodiment.
  • FIG. 5 is a cross-sectional view of the multilayer ceramic electronic component according to Embodiments 1 and 2 of the present invention.
  • FIG. 6 is a side view of the electronic device according to the first and second embodiments.
  • FIG. 7 is an enlarged sectional view of a main part of a multilayer ceramic electronic component according to Embodiment 3 of the present invention.
  • FIG. 1 to 4 are enlarged cross-sectional views of a principal part for describing a manufacturing process of the multilayer ceramic electronic component according to the first embodiment of the present invention, and FIG.
  • the second ceramic sheet 1 2 first Seramitsukushi - has a higher sintering temperature than the sintering temperature of the sheet 1 1 is manufactured using the A 1 2 0 3.
  • the conductor pattern 13 is formed using Ag or Ag_Pt.
  • the laminate is provided with a slit-shaped groove 14a and a V-shaped groove 14b.
  • FIG. 6 is a side view of the electronic device according to the first embodiment.
  • the multilayer ceramic electronic component 60 shown in FIG. 5 is mounted on a circuit board 64 having an electrode pattern 63 on the surface.
  • a method for manufacturing the multilayer ceramic electronic component in the first embodiment will be described.
  • first ceramic sheets 11 and the conductor patterns 13 are alternately laminated, and the upper and lower surfaces are sandwiched between the second ceramic sheets 12 to produce an integrated laminate.
  • a conductor pattern 13 exists between at least one of the first ceramic sheet 11 and the second ceramic sheet 12.
  • a slit-like groove 14a reaching the first ceramic sheet 11 with a cutter blade or the like is formed at a predetermined position on the surface of the laminate, and subsequently, as shown in FIG.
  • the groove 14b is formed by pushing and opening the groove 14a with a mold having a V-shaped cross section. At this time, the tip of the mold reaches the first ceramic sheet 11.
  • the second ceramic sheet 12 covers the upper part of the inside of the groove 14a of the first ceramic sheet 11. Then, the upper end of the portion forming the groove 14a of the first ceramic sheet 11 is chamfered in a curved shape.
  • Similar grooves 14a and 14b are provided on the back surface of the laminate so as to face the grooves. Thereafter, the laminate is pressed, and the groove 14b is reduced as shown in FIG.
  • the laminated body is fired so that the first ceramic sheet 11 and the conductor pattern 13 are sintered, and the second ceramic sheet 12 is not sintered. Is done.
  • the second ceramic sheet 12 hardly shrinks because it is not sintered. Accordingly, shrinkage of the first ceramic sheet 11 to be sintered is suppressed, and a sintered body having excellent planar accuracy can be obtained.
  • the groove 14b of the first ceramic sheet 11 contracts because it has a greater degree of freedom than the other parts, and the groove 14b becomes larger again as shown in FIG.
  • the second ceramic sheet 12 is removed. Since the second ceramic sheet 12 is not sintered, it can be easily removed.
  • the IC 61 and the capacitor 62 are connected to the conductor pattern 13 on the surface having the conductor pattern 13, the laminate is divided by the grooves 14 a and 14 b, and the laminate shown in FIG. 5 is formed. A ceramic electronic component 60 is obtained.
  • the multilayer ceramic electronic component 60 is not only excellent in flatness accuracy but also has excellent strength against impact since the end portion is chamfered in a curved shape.
  • the laminated ceramic electronic component 60 is chamfered in a curved shape at its end. 4 can prevent damage.
  • the grooves 14a and 14b may be formed by another method.
  • a mold having a V-shaped cross section is pressed against a predetermined position on the surface of the laminate to form a groove having a V-shaped cross section.
  • the tip of the mold reaches the first ceramic sheet 11 and the second ceramic sheet 12 covers the inside of the groove of the first ceramic sheet 11.
  • the upper end of the groove forming portion of the first ceramic sheet 11 is chamfered in a curved shape.
  • a slit-like groove is provided with a knife or the like so as to further deepen the groove.
  • the conductor pattern 13 may be a circuit pattern such as a resistor pattern including the conductor pattern. (Embodiment 2)
  • the laminate formed in the same manner as in the first embodiment is fired in the same manner as in the first embodiment after the grooves 14a and 14b are formed.
  • the conductor pattern 13 is not formed between the first ceramic sheet 11 and the second ceramic sheet 12.
  • a metal paste is applied to the surface of the sintered body and is baked to form the conductor pattern 13.
  • electronic components such as ICs and capacitors are mounted on the conductor pattern 13.
  • the multilayer body is divided by the grooves 14a and 14b, and a multilayer ceramic electronic component 60 is obtained.
  • the electronic component 60 is mounted on a circuit board, and an electronic device is manufactured.
  • the obtained multilayer ceramic electronic component not only has excellent flatness accuracy, but also has a strength that is strong against impact because it has a chamfered end portion. . Further, even if bending occurs after mounting on the circuit board, the end of the laminated ceramic electronic component 60 is chamfered into a curved shape, so that damage can be prevented even if the laminated ceramic electronic component 60 comes into contact with the circuit board 64.
  • the second embodiment differs from the first embodiment only in that conductor pattern 13 on the surface of multilayer ceramic electronic component 60 is formed before or after firing the laminate.
  • the first embodiment requires only one heat treatment step, and therefore has higher productivity than the second embodiment. (Embodiment 3)
  • FIG. 7 is an enlarged cross-sectional view of a main part for describing a manufacturing process of the multilayer ceramic electronic component in the third embodiment.
  • the same components as those in the first and second embodiments are denoted by the same reference numerals and description thereof is omitted.
  • the first ceramic sheet 11 and the conductor pattern 13 are alternately laminated, and a laminated body in which the upper and lower surfaces are sandwiched by the second ceramic sheet 12 is produced, and the groove 14 a , 14b are provided on the front and back sides.
  • the laminate is fired so that the first ceramic sheet 11 and the conductor pattern 13 are sintered and the second and third ceramic sheets 12 and 15 are not sintered. .
  • the groove 14a becomes larger again.
  • the upper and lower surfaces of the laminate are pressure-bonded with the third ceramic sheet 15 after forming the grooves 14a and 14b with chamfered ends.
  • shrinkage of first ceramic sheet 11 at the time of firing can be suppressed, so that a multilayer ceramic electronic component having better planar accuracy than that of the first embodiment can be obtained.
  • the conductor pattern on the surface of the multilayer ceramic electronic component may be formed before firing as in the first embodiment, or after firing as in the second embodiment.
  • the groove 14 a is provided so that the second ceramic sheet 12 covers the end of the first ceramic sheet 11, so that the multilayer ceramic electronic component can be manufactured.
  • the end can be rounded.
  • the electronic component has a conductive pattern 13 on the surface, the conductive pattern 13 may be damaged by polishing, so the end cannot be curved. If this electronic component is mounted on a circuit board, When bending occurs, the edge contacts the circuit board and the multilayer ceramic electronic component may be damaged. In the case of an electronic component having a resistor pattern instead of the conductor pattern 13, the characteristics are deteriorated due to damage.
  • the V-shaped groove 14a and the slit-shaped groove 14b have a Y-shaped cross-section for the dividing groove. Is longer. this Accordingly, the laminate can be easily divided after firing while suppressing shrinkage of the first ceramic sheet 11.
  • these grooves are provided on the front and back surfaces of the laminate. However, if the grooves are provided on only one of the surfaces, the laminate can be easily divided after firing.
  • the groove is preferably formed on a surface facing the substrate when the multilayer body is mounted on the circuit substrate, and preferably prevents the electronic component from being damaged by bending.
  • the second ceramic sheet 12 suppresses shrinkage of the first ceramic sheet 11 during firing in order to obtain a multilayer ceramic electronic component having excellent planar accuracy.
  • the degree of freedom of the first ceramic sheet 11 increases accordingly.
  • the first ceramic sheet 11 tends to shrink in the direction of increasing the groove, and the shape accuracy of the laminated ceramic electronic component may be degraded.
  • the laminate is pressed to compress the grooves 14a, and the grooves 14a are apparently reduced. Thereby, even if the first ceramic sheet shrinks during firing, the groove 14a is compressed in advance, so that a sintered laminate having an original state, that is, a desired shape can be obtained.
  • a groove is formed on a surface of a laminate having a first ceramic sheet and a second ceramic sheet having a higher sintering temperature than the first ceramic sheet and sandwiching the first ceramic sheet so as to reach the first ceramic sheet. Is formed. This makes it possible to obtain a multilayer ceramic electronic component having excellent impact resistance, the edges of which are chamfered in a curved shape.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

A laminate is produced by alternately laminating first ceramic sheets and conductor patterns, and integrating them with the lower surfaces clamped by second ceramic sheets. The laminate is provided with conductor patterns between at least either first ceramic sheets or second ceramic sheets. Next, splitting grooves Y-shaped in cross section are formed in desired positions of the laminate so as to cover the inner periphery of an upper end with a second ceramic sheet, then the resultant laminate is fired. Second ceramic sheets are removed and the laminate is split at grooves. Electronic components formed from respective split laminate elements are chamfered into curved shapes at the ends thereof for excellent impact resistance.

Description

明細書 積層セラミック電子部品の製造方法及び電子機器 技術分野  Description Manufacturing method of multilayer ceramic electronic component and electronic equipment
本発明はチップ部品、 半導体等を実装する平面精度に優れた積層セラミック電 子部品の製造方法及びその電子部品を用いた電子機器に関する。 背景技術  The present invention relates to a method for manufacturing a multilayer ceramic electronic component having excellent planar accuracy for mounting chip components, semiconductors, and the like, and an electronic device using the electronic component. Background art
従来の積層セラミック電子部品の製造方法について説明する。 まずガラスセラ ミック粉末に有機バインダ一および可塑剤などを混合して第 1のセラミツクシ一 トが得られる。 次に第 1のセラミックシ一トの表面に導体パ夕一ンが形成され、 第 1のセラミックシートが積層される。 その後、 第 1のセラミックシートの上下 に、 第 1のセラミックシートの焼成温度で焼結しない第 2のセラミックシートが 積層されて積層体が得られる。 次にこの積層体の表面の第 1のセラミックシート にスリットが形成された後に第 1のセラミックシートの焼成温度で焼成され、 焼 結していない第 2のセラミックシートが除去される。 次いでスリツ卜で積層体が 分割され、 積層セラミック電子部品が得られる。  A conventional method for manufacturing a multilayer ceramic electronic component will be described. First, an organic binder and a plasticizer are mixed with glass ceramic powder to obtain a first ceramic sheet. Next, a conductor pattern is formed on the surface of the first ceramic sheet, and the first ceramic sheet is laminated. Thereafter, a second ceramic sheet that is not sintered at the firing temperature of the first ceramic sheet is laminated above and below the first ceramic sheet to obtain a laminate. Next, after a slit is formed in the first ceramic sheet on the surface of the laminate, the laminate is fired at the firing temperature of the first ceramic sheet, and the unsintered second ceramic sheet is removed. Next, the laminate is divided by slits, and a multilayer ceramic electronic component is obtained.
この積層セラミック電子部品が、 表面に電極パターンを有する回路基板に実装 され電子機器が製造される。  The multilayer ceramic electronic component is mounted on a circuit board having an electrode pattern on the surface, and an electronic device is manufactured.
上記積層セラミック電子部品においては、 焼成時第 2のセラミックシートは焼 結せず殆ど収縮しないので、 焼結により収縮しょうとする第 1のセラミツクシ一 トを拘束する。 従って、 第 1のセラミックシートの収縮を抑制でき、 平面精度に 優れた積層セラミック電子部品を生産性良く得ることができる。  In the multilayer ceramic electronic component, since the second ceramic sheet is not sintered and hardly shrinks during firing, the first ceramic sheet that shrinks by sintering is restrained. Therefore, shrinkage of the first ceramic sheet can be suppressed, and a multilayer ceramic electronic component having excellent planar accuracy can be obtained with high productivity.
しかし上記方法によると、 積層セラミック電子部品の端部は鋭角となる。 従つ て、 この電子部品が回路基板に実装される時に回路基板に撓みが発生すると、 回 路基板にこの端部が接触することにより、 積層セラミック電子部品に割れや欠け が発生し、 特性が劣化する。 発明の開示 However, according to the above method, the end of the multilayer ceramic electronic component has an acute angle. Therefore, if the circuit board is bent when the electronic component is mounted on the circuit board, the end of the circuit board comes into contact with the circuit board, causing the multilayer ceramic electronic component to crack or chip. Occurs and the characteristics deteriorate. Disclosure of the invention
第 1のセラミックシートが第 1のセラミックシートよりも高い焼結温度を有す る第 2のセラミックシートで挟まれて積層体が得られる。 積層体に第 1のセラミ ックシ一トに至る溝が、 第 2のセラミックシートが第 1のセラミックシートの溝 の上端部を被覆するように形成される。 第 1のセラミックシートが焼結しかつ第 2のセラミツクシ一トが焼結しない温度で積層体が焼成される。 第 2のセラミツ クシートが除去され、 溝で積層体が分割されて、 積層セラミック電子部品が製造 される。  The first ceramic sheet is sandwiched between second ceramic sheets having a higher sintering temperature than the first ceramic sheet to obtain a laminate. A groove leading to the first ceramic sheet is formed in the laminate such that the second ceramic sheet covers the upper end of the groove of the first ceramic sheet. The laminate is fired at a temperature at which the first ceramic sheet sinters and the second ceramic sheet does not sinter. The second ceramic sheet is removed, and the laminate is divided by the grooves, thereby producing a multilayer ceramic electronic component.
この方法により、 平面精度を確保しつつ、 耐衝撃性に優れた積層セラミック電 子部品が製造される。 図面の簡単な説明  By this method, a multilayer ceramic electronic component having excellent impact resistance while ensuring planarity is manufactured. BRIEF DESCRIPTION OF THE FIGURES
図 1は本発明の実施の形態 1における積層セラミック電子部品の要部拡大断面 図である。  FIG. 1 is an enlarged sectional view of a main part of a multilayer ceramic electronic component according to Embodiment 1 of the present invention.
図 2は実施の形態 1における積層セラミック電子部品の要部拡大断面図である。 図 3は実施の形態 1における積層セラミック電子部品の要部拡大断面図である。 図 4は実施の形態 1における積層セラミック電子部品の要部拡大断面図である。 図 5は本発明の実施の形態 1 , 2における積層セラミック電子部品の断面図で ある。  FIG. 2 is an enlarged sectional view of a main part of the multilayer ceramic electronic component according to the first embodiment. FIG. 3 is an enlarged sectional view of a main part of the multilayer ceramic electronic component according to the first embodiment. FIG. 4 is an enlarged sectional view of a main part of the multilayer ceramic electronic component according to the first embodiment. FIG. 5 is a cross-sectional view of the multilayer ceramic electronic component according to Embodiments 1 and 2 of the present invention.
図 6は実施の形態 1 , 2における電子機器の側面図である。  FIG. 6 is a side view of the electronic device according to the first and second embodiments.
図 7は本発明の実施の形態 3における積層セラミック電子部品の要部拡大断面 図である。 発明を実施するための最良の形態  FIG. 7 is an enlarged sectional view of a main part of a multilayer ceramic electronic component according to Embodiment 3 of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
(実施の形態 1 ) 図 1〜図 4は本発明の実施の形態 1における積層セラミック電子部品の製造ェ 程を説明するための要部拡大断面図、 図 5は積層セラミック電子部品の断面図で ある。 第 1のセラミックシ一ト 1 1は A 1 203, C a O - B a O - S i 02系ガ ラス等を用いて作製される。 第 2のセラミックシート 1 2は第 1のセラミツクシ —ト 1 1の焼結温度よりも高い焼結温度を有し、 A 1 203を用いて作製される。 導体パターン 1 3は A gあるいは A g _ P tを用いて形成される。 積層体にはス リツト状の溝 1 4 aと V字状の溝 1 4 bが設けられる。 (Embodiment 1) 1 to 4 are enlarged cross-sectional views of a principal part for describing a manufacturing process of the multilayer ceramic electronic component according to the first embodiment of the present invention, and FIG. First ceramic sheet Ichito 1 1 A 1 2 0 3, C a O - prepared using a S i 0 2 based glass or the like - B a O. The second ceramic sheet 1 2 first Seramitsukushi - has a higher sintering temperature than the sintering temperature of the sheet 1 1 is manufactured using the A 1 2 0 3. The conductor pattern 13 is formed using Ag or Ag_Pt. The laminate is provided with a slit-shaped groove 14a and a V-shaped groove 14b.
図 6は実施の形態 1における電子機器の側面図である。 表面に電極パターン 6 3を有する回路基板 6 4に図 5に示す積層セラミック電子部品 6 0が実装される。 以下実施の形態 1における積層セラミック電子部品の製造方法について説明す る。  FIG. 6 is a side view of the electronic device according to the first embodiment. The multilayer ceramic electronic component 60 shown in FIG. 5 is mounted on a circuit board 64 having an electrode pattern 63 on the surface. Hereinafter, a method for manufacturing the multilayer ceramic electronic component in the first embodiment will be described.
まず第 1のセラミックシート 1 1と導体パターン 1 3とが交互に積層され、 'こ の上下面が第 2のセラミックシート 1 2で挟み込まれて一体化された積層体が作 製される。 第 1のセラミックシート 1 1と第 2のセラミックシート 1 2の少なく とも一方の間には導体パターン 1 3が存在する。  First, the first ceramic sheets 11 and the conductor patterns 13 are alternately laminated, and the upper and lower surfaces are sandwiched between the second ceramic sheets 12 to produce an integrated laminate. A conductor pattern 13 exists between at least one of the first ceramic sheet 11 and the second ceramic sheet 12.
次に、 図 1に示すようにカッター刃などで第 1のセラミックシ一ト 1 1に至る スリット状の溝 1 4 aが積層体の表面の所定の位置に形成され、 続いて図 2に示 すように断面が V字状の金型で溝 1 4 aを押し開くようにして溝 1 4 bが形成さ れる。 この時、 金型の先端は第 1のセラミックシ一ト 1 1に到達する。 溝 1 4 a, 1 4 bの形成後は、 第 2のセラミックシート 1 2が第 1のセラミックシート 1 1 の溝 1 4 aの内部上方の部分を被覆する。 そして、 第 1のセラミックシート 1 1 の溝 1 4 aを形成する部分の上端は曲面状に面取りされる。  Next, as shown in FIG. 1, a slit-like groove 14a reaching the first ceramic sheet 11 with a cutter blade or the like is formed at a predetermined position on the surface of the laminate, and subsequently, as shown in FIG. The groove 14b is formed by pushing and opening the groove 14a with a mold having a V-shaped cross section. At this time, the tip of the mold reaches the first ceramic sheet 11. After the formation of the grooves 14a and 14b, the second ceramic sheet 12 covers the upper part of the inside of the groove 14a of the first ceramic sheet 11. Then, the upper end of the portion forming the groove 14a of the first ceramic sheet 11 is chamfered in a curved shape.
またこの溝に対向するように、 積層体裏面にも同様の溝 1 4 a , 1 4 bが設け られる。 その後、 この積層体がプレスされて、 図 3.に示すように溝 1 4 bが小さ くなる。  Similar grooves 14a and 14b are provided on the back surface of the laminate so as to face the grooves. Thereafter, the laminate is pressed, and the groove 14b is reduced as shown in FIG.
そしてこの状態のまま、 第 1のセラミックシート 1 1及び導体パターン 1 3が 焼結され、 かつ第 2のセラミツクシ一卜 1 2が焼結されないように積層体が焼成 される。 このとき、 第 2のセラミックシート 1 2は焼結されないのでほとんど収 縮しない。 従って、 焼結する第 1のセラミックシート 1 1が収縮するのを抑制さ れ、 平面精度に優れた焼結体が得られる。 第 1のセラミックシート 1 1の溝 1 4 bの部分は自由度が他の部分よりも大きいので収縮し、 溝 1 4 bは再び図 4に示 すように大きくなる。 Then, in this state, the laminated body is fired so that the first ceramic sheet 11 and the conductor pattern 13 are sintered, and the second ceramic sheet 12 is not sintered. Is done. At this time, the second ceramic sheet 12 hardly shrinks because it is not sintered. Accordingly, shrinkage of the first ceramic sheet 11 to be sintered is suppressed, and a sintered body having excellent planar accuracy can be obtained. The groove 14b of the first ceramic sheet 11 contracts because it has a greater degree of freedom than the other parts, and the groove 14b becomes larger again as shown in FIG.
次に、 第 2のセラミックシート 1 2のみが除去される。 第 2のセラミツクシ一 ト 1 2は未焼結なので、 容易に除去できる。  Next, only the second ceramic sheet 12 is removed. Since the second ceramic sheet 12 is not sintered, it can be easily removed.
次いで、 導体パターン 1 3を有する表面に I C 6 1やコンデンサ 6 2などが導 体パターン 1 3に接続され、 溝 1 4 a , 1 4 bで積層体が分割され、 図 5に示す ような積層セラミック電子部品 6 0が得られる。  Next, the IC 61 and the capacitor 62 are connected to the conductor pattern 13 on the surface having the conductor pattern 13, the laminate is divided by the grooves 14 a and 14 b, and the laminate shown in FIG. 5 is formed. A ceramic electronic component 60 is obtained.
積層セラミック電子部品 6 0は、 平面精度に優れているだけでなく端部が曲面 状に面取りされるので、 衝撃に強く優れた強度を有する。  The multilayer ceramic electronic component 60 is not only excellent in flatness accuracy but also has excellent strength against impact since the end portion is chamfered in a curved shape.
積層セラミック電子部品 6 0が図 6に示すように、 表面 φ電極パターン 6 3を 有する回路基板 6 4に実装されることにより、 例えば携帯電話などの各種電子機 器が製造される。  By mounting the multilayer ceramic electronic component 60 on a circuit board 64 having a surface φ electrode pattern 63 as shown in FIG. 6, various electronic devices such as mobile phones are manufactured.
例えば電子機器に衝撃が加わり、 回路基板 6 4に撓みが発生した場合、 積層セ ラミック電子部品 6 0は端部が曲面状に面取りされるので、 回路基板 6 4に接触 したとしても回路基板 6 4の損傷を防止できる。  For example, when a shock is applied to the electronic device and the circuit board 64 is bent, the laminated ceramic electronic component 60 is chamfered in a curved shape at its end. 4 can prevent damage.
なお、 溝 1 4 a , 1 4 bは別の方法で形成されてもよい。 断面が V字状の金型 が積層体表面の所定の位置に押し付けられて、 断面が V字状の溝が形成される。 この時、 金型の先端が第 1のセラミックシート 1 1に到達し、 第 2のセラミック シート 1 2が第 1のセラミックシート 1 1の溝の内部上方を被覆する。 第 1のセ ラミックシート 1 1の溝を形成する部分の上端は曲面状に面取りされる。 次にこ の溝を更に深くするように、 カツ夕一刃などでスリツト状の溝が設けられる。 導体パターン 1 3は導体パターンを含む抵抗体パターン等の回路パターンでも よい。 (実施の形態 2 ) Note that the grooves 14a and 14b may be formed by another method. A mold having a V-shaped cross section is pressed against a predetermined position on the surface of the laminate to form a groove having a V-shaped cross section. At this time, the tip of the mold reaches the first ceramic sheet 11 and the second ceramic sheet 12 covers the inside of the groove of the first ceramic sheet 11. The upper end of the groove forming portion of the first ceramic sheet 11 is chamfered in a curved shape. Next, a slit-like groove is provided with a knife or the like so as to further deepen the groove. The conductor pattern 13 may be a circuit pattern such as a resistor pattern including the conductor pattern. (Embodiment 2)
まず実施の形態 1と同様にして形成された積層体は、 溝 1 4 a, 1 4 bが形成 された後、 実施の形態 1と同様に焼成される。 ただし、 第 1のセラミックシート 1 1と第 2のセラミックシート 1 2との間に導体パターン 1 3が形成されない。 次に第 2のセラミックシート 1 2が除去された後、 焼結体の表面に金属ペース トが塗布され、 焼き付けられることにより導体パターン 1 3が形成される。 その 後、 この導体パターン 1 3の上に I Cやコンデンサなどの電子部品が実装される。 その後、 溝 1 4 a, 1 4 bで積層体が分割され、 積層セラミック電子部品 6 0が 得られる。 そして電子部品 6 0は回路基板に実装され、 電子機器が製造される。 実施の形態 2においても実施の形態 1と同様に、 得られた積層セラミック電子 部品は平面精度に優れているだけでなく端部が曲面状に面取りされるので、 衝撃 に強く優れた強度を有する。 また回路基板に実装後、 撓みが発生したとしても積 層セラミック電子部品 6 0は端部が曲面状に面取りされるので、 回路基板 6 4に 接触したとしても損傷を防止できる。  First, the laminate formed in the same manner as in the first embodiment is fired in the same manner as in the first embodiment after the grooves 14a and 14b are formed. However, the conductor pattern 13 is not formed between the first ceramic sheet 11 and the second ceramic sheet 12. Next, after the second ceramic sheet 12 is removed, a metal paste is applied to the surface of the sintered body and is baked to form the conductor pattern 13. Thereafter, electronic components such as ICs and capacitors are mounted on the conductor pattern 13. Thereafter, the multilayer body is divided by the grooves 14a and 14b, and a multilayer ceramic electronic component 60 is obtained. Then, the electronic component 60 is mounted on a circuit board, and an electronic device is manufactured. In the second embodiment, similarly to the first embodiment, the obtained multilayer ceramic electronic component not only has excellent flatness accuracy, but also has a strength that is strong against impact because it has a chamfered end portion. . Further, even if bending occurs after mounting on the circuit board, the end of the laminated ceramic electronic component 60 is chamfered into a curved shape, so that damage can be prevented even if the laminated ceramic electronic component 60 comes into contact with the circuit board 64.
実施の形態 2と実施の形態 1とは、 積層セラミック電子部品 6 0の表面の導体 パターン 1 3が積層体の焼成前あるいは焼成後に形成されるかだけが異なる。 表面の導体パターン 1 3の形成に熱処理工程を含む場合、 実施の形態 1におい ては、 熱処理工程が一度で済むので実施の形態 2よりも生産性に優れる。 (実施の形態 3 )  The second embodiment differs from the first embodiment only in that conductor pattern 13 on the surface of multilayer ceramic electronic component 60 is formed before or after firing the laminate. In the case where a heat treatment step is included in the formation of the conductor pattern 13 on the front surface, the first embodiment requires only one heat treatment step, and therefore has higher productivity than the second embodiment. (Embodiment 3)
図 7は実施の形態 3における積層セラミック電子部品の製造工程を説明するた めの要部拡大断面図である。 実施の形態 1 , 2と同様の構成要素については同番 号を付して説明を省略する。  FIG. 7 is an enlarged cross-sectional view of a main part for describing a manufacturing process of the multilayer ceramic electronic component in the third embodiment. The same components as those in the first and second embodiments are denoted by the same reference numerals and description thereof is omitted.
まず実施の形態 1と同様に第 1のセラミックシート 1 1と導体パターン 1 3を 交互に積層され、 上、 下面を第 2のセラミックシート 1 2が挟み込んだ積層体が 作製され、 溝 1 4 a, 1 4 bが表、 裏面に設けられる。  First, similarly to the first embodiment, the first ceramic sheet 11 and the conductor pattern 13 are alternately laminated, and a laminated body in which the upper and lower surfaces are sandwiched by the second ceramic sheet 12 is produced, and the groove 14 a , 14b are provided on the front and back sides.
次に、 図 7に示すようにこの積層体の上、 下面の溝 1 4 a, 1 4 bを覆うよう に第 2のセラミックシート 1 2と同様の材質の第 3のセラミックシート 1 5が圧 着される。 この時、 積層体は外周から加圧されるため、 実施の形態 1と同様に溝 1 4 aは最初に形成した時よりも小さくなる。 Next, as shown in Fig. 7, cover the grooves 14a and 14b on the upper and lower surfaces of this laminate. Then, a third ceramic sheet 15 having the same material as that of the second ceramic sheet 12 is pressed. At this time, since the laminate is pressed from the outer periphery, the groove 14a is smaller than when it is first formed as in the first embodiment.
その後、 この積層体が、 第 1のセラミックシート 1 1及び導体パターン 1 3が 焼結しかつ第 2と第 3のセラミックシ一ト 1 2、 1 5が未焼結となるように焼成 される。 この結果、 実施の形態 1と同様に溝 1 4 aは再び大きくなる。  Thereafter, the laminate is fired so that the first ceramic sheet 11 and the conductor pattern 13 are sintered and the second and third ceramic sheets 12 and 15 are not sintered. . As a result, as in the first embodiment, the groove 14a becomes larger again.
次に第 2と第 3のセラミックシート 1 2、 1 5が除去され、 積層体の表面に I Cゃコンデンサ等の電子部品が実装された後、 溝 1 4 a , 1 4 bで積層体を分割 され、 図 5に示すような積層セラミック電子部品が得られる。  Next, the second and third ceramic sheets 12 and 15 are removed, electronic components such as ICs and capacitors are mounted on the surface of the laminate, and the laminate is divided by the grooves 14a and 14b. Thus, a multilayer ceramic electronic component as shown in FIG. 5 is obtained.
実施の形態 3においては、 端部が曲面状に面取りされ、 溝 1 4 a, 1 4 bを形 成した後に第 3のセラミックシート 1 5で積層体の上、 下面が圧着される。 これ により、 焼成時の第 1のセラミックシート 1 1の収縮をされに抑制できるので実 施の形態 1よりも平面精度に優れた積層セラミック電子部品を得ることができる。 実施の形態 3においては積層セラミック電子部品表面の導体パターンは、 実施 の形態 1のように焼成前、 あるいは実施の形態 2のように焼成後に形成されても よい。  In the third embodiment, the upper and lower surfaces of the laminate are pressure-bonded with the third ceramic sheet 15 after forming the grooves 14a and 14b with chamfered ends. Thereby, shrinkage of first ceramic sheet 11 at the time of firing can be suppressed, so that a multilayer ceramic electronic component having better planar accuracy than that of the first embodiment can be obtained. In the third embodiment, the conductor pattern on the surface of the multilayer ceramic electronic component may be formed before firing as in the first embodiment, or after firing as in the second embodiment.
実施の形態 1〜3においては、 第 2のセラミックシート 1 2が第 1のセラミツ クシ一ト 1 1の端部を被覆するように溝 1 4 aが設けられることにより、 積層セ ラミック電子部品の端部を曲面状に面取りできる。  In the first to third embodiments, the groove 14 a is provided so that the second ceramic sheet 12 covers the end of the first ceramic sheet 11, so that the multilayer ceramic electronic component can be manufactured. The end can be rounded.
また従来の積層セラミック電子部品においては端部を曲面状に面取りするため には焼成後研磨する必要がある。 電子部品が表面に導体パターン 1 3を有する場 合、 研磨により導体パターン 1 3が損傷する場合があるので端部を曲面にできな レ^ この電子部品が回路基板に実装されると、 基板に撓みが発生した場合端部が 回路基板に接触し、 積層セラミック電子部品が損傷することがある。 導体パター ン 1 3の代りに抵抗体パターンを有する電子部品では損傷により特性が劣化する。  Further, in the case of a conventional multilayer ceramic electronic component, it is necessary to polish after firing in order to chamfer the end portion into a curved shape. If the electronic component has a conductive pattern 13 on the surface, the conductive pattern 13 may be damaged by polishing, so the end cannot be curved. If this electronic component is mounted on a circuit board, When bending occurs, the edge contacts the circuit board and the multilayer ceramic electronic component may be damaged. In the case of an electronic component having a resistor pattern instead of the conductor pattern 13, the characteristics are deteriorated due to damage.
V字状の溝 1 4 aとスリツト状の溝 1 4 bからなる断面が Y字状の分割用の溝 は、 V字状の型で形成された部分よりも、 刃で形成された部分の方が長い。 これ により第 1のセラミックシート 1 1の収縮を抑制しつつ、 焼成後に積層体は容易 に分割できる。 The V-shaped groove 14a and the slit-shaped groove 14b have a Y-shaped cross-section for the dividing groove. Is longer. this Accordingly, the laminate can be easily divided after firing while suppressing shrinkage of the first ceramic sheet 11.
実施の形態 1〜3ではこれらの溝は積層体の表、 裏面に設けられるが、 溝はい ずれか一方の面にのみ設けられても焼成後積層体は容易に分割できる。 溝は、 積 層体が回路基板に実装される際の基板に対向する面に形成され、 撓みにより電子 部品が損傷するのを防止することが好ましい。  In Embodiments 1 to 3, these grooves are provided on the front and back surfaces of the laminate. However, if the grooves are provided on only one of the surfaces, the laminate can be easily divided after firing. The groove is preferably formed on a surface facing the substrate when the multilayer body is mounted on the circuit substrate, and preferably prevents the electronic component from being damaged by bending.
さらに、 第 2のセラミックシート 1 2は、 平面精度に優れた積層セラミック電 子部品を得るため、 焼成時に第 1のセラミックシート 1 1が収縮するのを抑制す る。 第 1及び第 2のセラミックシート 1 1, 1 2の両方に分割用の溝が設けられ ると、 それだけ第 1のセラミックシート 1 1の自由度が大きくなる。 これにより 第 1のセラミックシート 1 1は溝を大きくする方向に収縮しやすくなり、 積層セ ラミック電子部品の形状精度が悪くなる恐れが有る。 分割用の溝が設けられた後 に積層体が加圧されて溝 1 4 aが圧縮され、 見かけ上溝 1 4 aが小さくなる。 こ れにより焼成時、 第 1のセラミックシートが収縮したとしても、 前もって溝 1 4 aが圧縮されているので、 元の状態、 即ち所望の形状の焼結された積層体を得る ことができる。 産業上の利用可能性  Further, the second ceramic sheet 12 suppresses shrinkage of the first ceramic sheet 11 during firing in order to obtain a multilayer ceramic electronic component having excellent planar accuracy. If the dividing grooves are provided in both the first and second ceramic sheets 11 and 12, the degree of freedom of the first ceramic sheet 11 increases accordingly. As a result, the first ceramic sheet 11 tends to shrink in the direction of increasing the groove, and the shape accuracy of the laminated ceramic electronic component may be degraded. After the grooves for division are provided, the laminate is pressed to compress the grooves 14a, and the grooves 14a are apparently reduced. Thereby, even if the first ceramic sheet shrinks during firing, the groove 14a is compressed in advance, so that a sintered laminate having an original state, that is, a desired shape can be obtained. Industrial applicability
本発明によると、 第 1のセラミックシートとこれを挟むこれよりも高い焼結温 度を有する第 2のセラミックシートとを有する積層体の表面に、 第 1のセラミツ クシ一トに至るように溝が形成される。 これにより、 端部が曲面状に面取りされ る耐衝撃性に優れた積層セラミック電子部品を得ることができる。  According to the present invention, a groove is formed on a surface of a laminate having a first ceramic sheet and a second ceramic sheet having a higher sintering temperature than the first ceramic sheet and sandwiching the first ceramic sheet so as to reach the first ceramic sheet. Is formed. This makes it possible to obtain a multilayer ceramic electronic component having excellent impact resistance, the edges of which are chamfered in a curved shape.

Claims

請求の範囲 The scope of the claims
1 . 第 1のセラミックシートを前記第 1のセラミックシートよりも高い焼結温 度を有する第 2のセラミックシートで挟み積層体を得る工程と、  1. sandwiching the first ceramic sheet with a second ceramic sheet having a higher sintering temperature than the first ceramic sheet to obtain a laminate;
前記積層体の第 1面に前記第 1のセラミックシートに至る溝を、 前記第 2 のセラミックシ一トが前記第 1のセラミツクシ一卜の前記溝の上端部を被覆する ように形成する工程と、  Forming a groove on the first surface of the laminate to reach the first ceramic sheet, so that the second ceramic sheet covers an upper end of the groove of the first ceramic sheet; ,
前記第 1のセラミックシートが焼結しかつ前記第 2のセラミックシートが 焼結しない温度で前記積層体を焼成する工程と、  Baking the laminate at a temperature at which the first ceramic sheet is sintered and the second ceramic sheet is not sintered;
前記第 2のセラミックシートを除去する工程と、  Removing the second ceramic sheet;
前記溝で前記積層体を分割する工程と  Dividing the laminate by the grooves;
を備えた、 積層セラミック電子部品の製造方法。 A method for manufacturing a multilayer ceramic electronic component, comprising:
2 . 前記第 1のセラミックシート上に回路パターンを形成する工程をさらに備え た、 請求の範囲第 1項に記載の方法。 2. The method according to claim 1, further comprising forming a circuit pattern on the first ceramic sheet.
3 . 前記焼成された積層体上に回路パターンを形成する工程をさらに備えた、 請 求の範囲第 1項に記載の方法。 3. The method of claim 1, further comprising forming a circuit pattern on the fired laminate.
4. 前記積層体の前記溝を有する面に第 3のセラミックシートを積層する工程を さらに備えた、 請求の範囲第 1項に記載の方法。 4. The method according to claim 1, further comprising: laminating a third ceramic sheet on a surface of the laminate having the groove.
5 . 前記焼成された積層体の前記上端部は面取りされている、 請求の範囲第 1項 に記載の方法。 5. The method of claim 1, wherein the upper end of the fired laminate is chamfered.
6 . 前記溝の断面は Y字状である、 請求の範囲第 1項に記載の方法。 6. The method according to claim 1, wherein the groove has a Y-shaped cross section.
7 . 前記溝を形成する工程は、 前記積層体に刃で切り込みを入れる工程と、 7. The step of forming the groove, A step of cutting the laminate with a blade,
前記積層体に V字状の型を押し付ける工程と、  Pressing a V-shaped mold against the laminate,
む、 請求の範囲第 1項に記載の方法。  The method according to claim 1.
8 . 前記 V字状の型を押し付ける工程は、 前記 V字状の型を前記第 1のセラミツ クシ一トに到達させる工程を含む、 請求の範囲第 7項に記載の方法。 8. The method according to claim 7, wherein the step of pressing the V-shaped mold includes the step of causing the V-shaped mold to reach the first ceramic sheet.
9 . 前記 V字状の型を押し付ける工程は、 前記切り込みより浅く前記 V字状の型 を押し付ける工程を含む、 請求の範囲第 7項に記載の方法。 9. The method of claim 7, wherein pressing the V-shaped mold comprises pressing the V-shaped mold shallower than the cut.
1 0 . 前記積層体の前記第 1面の反対側の第 2面に別の溝を形成する工程をさら に備えた、 請求の範囲第 1項に記載の方法。 10. The method according to claim 1, further comprising the step of forming another groove on a second surface of the laminate opposite to the first surface.
1 1 . 前記積層体を焼成する工程の前に前記溝を有する前記積層体を加圧するェ 程をさらに備えた、 請求の範囲第 1項に記載の方法。 11. The method according to claim 1, further comprising a step of pressing the laminate having the groove before the step of firing the laminate.
1 2 . 表面に電極パターンを有する回路基板と、 1 2. A circuit board having an electrode pattern on its surface;
前記回路基板に対向する面取りされた端部を有し、 表面に電子部品と回路 パターンとの少なくとも一つを備えた、 前記回路基板上に実装されて前記電極パ ターンに接続された積層セラミック電子部品と、  A multilayer ceramic electronic device having a chamfered end facing the circuit board and having at least one of an electronic component and a circuit pattern on a surface, mounted on the circuit board and connected to the electrode pattern; Parts and
を備えた電子機器。 Electronic equipment with.
PCT/JP2002/008795 2001-09-20 2002-08-30 Production method of laminated ceramic electronic component and electronic apparatus WO2003026856A1 (en)

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