JPH0766076A - Manufacture of laminated chip component and laminated chip component - Google Patents

Manufacture of laminated chip component and laminated chip component

Info

Publication number
JPH0766076A
JPH0766076A JP23546993A JP23546993A JPH0766076A JP H0766076 A JPH0766076 A JP H0766076A JP 23546993 A JP23546993 A JP 23546993A JP 23546993 A JP23546993 A JP 23546993A JP H0766076 A JPH0766076 A JP H0766076A
Authority
JP
Japan
Prior art keywords
laminated
laminated chip
cut
chip
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23546993A
Other languages
Japanese (ja)
Inventor
Shinichi Iwata
伸一 岩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokin Corp
Original Assignee
Tokin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokin Corp filed Critical Tokin Corp
Priority to JP23546993A priority Critical patent/JPH0766076A/en
Publication of JPH0766076A publication Critical patent/JPH0766076A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To prevent generation of breaking, cracks and delamination so as to improve reliability by previously bevelling the corner parts of a laminated chip in the shape of C or R before a cut-out process. CONSTITUTION:Through-holes 3 whose sections are rhombic or in the shape having curvature on the sides of a rhomb are stamped out from green sheets 1 and 2 having the points of intersection of the cut-out arranged lines 5 of the laminated chips. Later, these are laminated inside a laminated metal mold and subjected to thermocompression bonding so as to obtain a laminate having the through-holes 3 in the positions corresponding to the points of intersection of the arranged cut-out lines 5 of the laminated chips. The obtained laminates are cut off by a dicing saw along the lines shown by the arranged cut-out lines so as to obtain individual laminated chips having R-parts on four corners in the thickness direction. Later, debindering and sintering are followed by bevelling treatment inside a barrel device having alumina beads as a medium.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子機器等の回路に用
いられる、積層チップ部品およびその製造方法に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated chip part used in a circuit of electronic equipment and a method for manufacturing the same.

【0002】[0002]

【従来の技術】積層セラミックコンデンサー、積層セラ
ミックインダクター、積層バリスターなどに代表され
る、積層チップ部品は、形状及び構造の小型化と高密度
化が促進されると共に、信頼性に対する要求も厳しくな
ってきている。これらの積層チップ部品は定型のセラミ
ックのグリーンシート上に、所定の電極層又は導体パタ
ーンを印刷の後、精度良く積層金型内に積層し熱圧着を
行うことで、内部に電極層又は導体パターンを含む積層
体を得るグリーンシート積層法によるのが一般的であ
る。これにより得られた積層体は、所定の位置に沿っ
て、ダイシングソー又は押切り装置で切断を行い、複数
個の積層チップを切り出し焼結を行った後、積層チップ
焼結体をバレル装置等を用いて、チップ稜線部の角取り
処理を行なうことで焼結を完了した図4に示すような積
層チップを得る。その後、外部電極を形成し積層チップ
部品として仕上げる。
2. Description of the Related Art Multilayer chip parts, represented by monolithic ceramic capacitors, monolithic ceramic inductors, multi-layer varistors, etc., are being promoted in miniaturization and densification of shapes and structures, and demands for reliability are strict. It has become to. These laminated chip parts are printed with a predetermined electrode layer or conductor pattern on a standard ceramic green sheet, and then laminated in a laminated die with high accuracy and thermocompression bonded to the electrode layer or conductor pattern inside. A green sheet laminating method is generally used to obtain a laminated body containing. The laminated body obtained by this is cut along a predetermined position with a dicing saw or a pressing device, a plurality of laminated chips are cut out and sintered, and then the laminated chip sintered body is subjected to a barrel device or the like. Is used to chamfer the edge portion of the chip to obtain a laminated chip as shown in FIG. After that, external electrodes are formed and finished as a laminated chip component.

【0003】この場合、積層チップの信頼性に係る要因
として以下の事柄を挙げることが出来る。
In this case, the following matters can be mentioned as factors relating to the reliability of the laminated chip.

【0004】1.積層体を形成する際の層間剥離(デラ
ミネーション)の発生。
1. Occurrence of delamination when forming a laminated body.

【0005】近年、積層チップ部品の小型、高密度化が
促進されれば、される程、セラミックグリーンシートの
積層枚数は増す方向にあり、積層セラミックコンデンサ
ー等では、保護シートを含めたグリーンシートの積層数
が100〜200層になることも珍しく無い。ところ
が、積層体の形成時に問題が発生する。すなわち、積層
金型内にグリーンシートを積層する際、グリーンシート
間に空気層をまき込むと、得られた積層体内部でグリー
ンシート間の密着が不完全となりデラミネーションの発
生原因となる。グリーンシート積層時の空気抜きが円滑
に行なわれることが重要であるが、従来方法による一枚
シートの積層では、そのサイズが大きくなる程、空気抜
きが困難となる。
In recent years, the more compact and high-density laminated chip parts are promoted, the more the number of laminated ceramic green sheets tends to increase. In laminated ceramic capacitors and the like, the green sheets including a protective sheet are It is not uncommon for the number of layers to be 100 to 200. However, a problem occurs when the laminated body is formed. That is, when the green sheets are stacked in the stacking mold, if an air layer is spread between the green sheets, the adhesion between the green sheets will be incomplete inside the obtained stacked body, which may cause delamination. It is important that air is smoothly removed when stacking the green sheets, but in the stacking of one sheet by the conventional method, the larger the size, the more difficult it is to remove air.

【0006】2.積層体切断面近傍でのデラミネーショ
ンの発生。
2. Delamination occurs near the cut surface of the laminate.

【0007】積層体より積層体チップの切り出しを行な
う際、切断面での歪を最小限に抑える必要がある。積層
体切断面にかかる歪が大きい場合、切断面近傍でのデラ
ミネーションの発生原因となる。切断ブレードとして、
ダイシングソーブレードあるいは一枚刃ブレードがある
が、歪を緩和するためには切断ブレードと積層体切断面
との接触面積を極力少なくする事が重要であり又、切り
粉の逃げ場があると一層効果がある。従来の積層体で
は、切断スピードダウン等の切断条件の設定により、歪
の緩和を計っているが、作業能率上限界がある。
When cutting out a laminated chip from the laminated body, it is necessary to minimize distortion at the cut surface. When the strain applied to the cut surface of the laminate is large, it causes delamination near the cut surface. As a cutting blade,
There is a dicing saw blade or a single-blade blade, but it is important to minimize the contact area between the cutting blade and the cut surface of the laminate in order to alleviate the strain, and it is even more effective if there is an escape area for the cutting chips. There is. In the conventional laminated body, strain is relaxed by setting cutting conditions such as cutting speed reduction, but there is a limit in work efficiency.

【0008】3.積層チップ焼結体の角取り処理時の衝
撃によるカケ、クラック、デラミネーション等の内部欠
陥の発生による信頼性の低下。
3. Decrease in reliability due to internal defects such as chipping, cracks, and delamination due to impact during chamfering of the laminated chip sintered body.

【0009】焼結体の角取り処理ではバレル研摩を用い
ることが普通であるが、バレル研摩時の衝撃を小さく、
かつ短時間に抑える必要がある。特に角型を成す積層体
チップでは稜線部の衝撃が強く、その部分からカケ、ク
ラック、デラミネーションが発生する原因となりやす
い。
Barrel polishing is usually used in the chamfering treatment of the sintered body, but the impact during barrel polishing is small,
And it is necessary to keep it in a short time. Particularly, in the case of a rectangular laminated chip, the impact on the ridge portion is strong, and chipping, cracking, and delamination are likely to occur from that portion.

【0010】[0010]

【発明が解決しようとする課題】以上述べたごとく、従
来の製造方法によると、1)積層体の作製段階、2)積
層体より個々の積層体チップを切り出す段階、さらに
は、3)焼結された積層体チップの角取りを行なう段階
で、積層体内部のデラミネーション、積層体チップ表面
でのデラミネーション又は、積層体チップのカケ、クラ
ック、デラミネーションの拡大を起こしやすいという問
題点を含み、これらに起因する信頼性の劣化を生じると
いう問題点を有している。信頼性の劣化というのは、具
体的には、製品の絶縁抵抗の劣化もしくはショート現象
を引き起こすことである。
As described above, according to the conventional manufacturing method, 1) the step of producing a laminated body, 2) the step of cutting out individual laminated body chips from the laminated body, and further 3) the sintering. Including the problem that delamination inside the laminate, delamination on the surface of the laminate chip or chipping, cracking, and expansion of delamination of the laminate chip are likely to occur at the stage of chamfering the laminated chip However, there is a problem that the reliability is deteriorated due to these. Specifically, the deterioration of reliability means deterioration of insulation resistance of a product or a short circuit phenomenon.

【0011】[0011]

【課題を解決するための手段】上記問題点を解決するた
めに、積層体を形成して所定の積層チップを切り出した
際、積層チップにおける厚み方向稜線部の角部が、C又
はR形状に角取りされた形状となる様にあらかじめ、積
層されるグリーンシートの該当部分に打ち抜き加工を施
したものを用いることを特徴とする。又は角取りされた
形状となるような印刷パターンを使用してスクリーン印
刷により作製したものを用いても良い。
In order to solve the above-mentioned problems, when a laminated body is formed and a predetermined laminated chip is cut out, the corners of the ridge line in the thickness direction of the laminated chip have a C or R shape. It is characterized in that a green sheet to be laminated is punched at a corresponding portion in advance so as to have a chamfered shape. Alternatively, a screen pattern may be used that has a chamfered shape.

【0012】[0012]

【作用】積層チップの厚み方向の稜線部に形成される角
部に相当する部分が、あらかじめ打ち抜かれているグリ
ーンシートを積層することで、積層体から切り出された
積層チップは、従来法であれば、その厚み方向の稜線部
に形成されるはずの角部が既に、C又はR形状に角取り
されたと同一の形状が得られる。この方法によると、グ
リーンシートを積層金型に多数枚積層して行く場合に
も、グリーンシート間への空気のまき込みによるデラミ
ネーションを解消できる。更に、積層体より積層チップ
を切り出す際、切断ブレードが、打ち抜き加工された孔
の部分を通過するため、孔が切り粉の逃げ場となり、か
つ、切断ブレードと積層体との接触面積を減らすことが
出来るため、切断時に加える歪量を最小限に抑えること
が可能であり、デラミネーションの発生を防止できる。
又、焼結後に最終的な角取りの仕上処理を行なうとして
も、あらかじめ、積層チップの厚み方向の稜線部がC又
はR形状で角取りされた形状となっているため、角取り
を行なうバレル処理等の時間を大巾に短縮することが出
来、また焼結体に与える衝撃の緩和が出来るため、カ
ケ、クラック、デラミネーションの発生を防止できる。
The laminated chip cut out from the laminated body by laminating the green sheets having the corners formed on the ridgeline portion in the thickness direction of the laminated chip is punched in advance by the conventional method. For example, the same shape as that of the corner portion that should be formed on the ridgeline portion in the thickness direction is already obtained by chamfering into the C or R shape. According to this method, even when a large number of green sheets are stacked in a stacking mold, delamination due to the entrainment of air between the green sheets can be eliminated. Furthermore, when cutting the laminated chip from the laminated body, the cutting blade passes through the punched hole portion, so that the hole serves as an escape area for the cutting powder, and the contact area between the cutting blade and the laminated body can be reduced. Therefore, the amount of strain applied at the time of cutting can be minimized, and the occurrence of delamination can be prevented.
Even if the final finishing treatment of chamfering is performed after sintering, since the ridge line portion in the thickness direction of the laminated chip is chamfered in a C or R shape in advance, the barrel for chamfering is performed. Since the processing time can be greatly shortened and the impact given to the sintered body can be relaxed, the occurrence of chipping, cracking and delamination can be prevented.

【0013】[0013]

【実施例】以下、本発明の実施例を図面にもとづいて説
明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0014】図2は積層セラミックコンデンサーチップ
を複数個取りで得るための積層体の構成を示す概略図で
あり、符号aは、内部電極層が印刷されない保護膜層、
符号bは内部電極パターン4が印刷されたグリーンシー
トから成る内部電極層をあらわす。aおよびbを構成す
るグリーンシート1および2はセラミック粉末にPVB
をバインダーとして混合したスラリーをドクターブレー
ド法により厚み20μmに成形後、サイズ100×13
0mmに打ち抜かれたものであり、グリーンシート2は
内部電極パターン4を平面内で規則的な繰り返しでAg
/Pdペーストによって印刷されたものである。グリー
ンシート1および2は、図3に示すごとく、積層チップ
の切り出し予定線5(点線で表示)の交点を中心とし
て、断面が菱形又は菱形の辺に曲率をつけた形の貫通孔
3を打ち抜き加工した後、積層金型内に積み重ね、温度
80℃、圧力200Kg/cm2の条件で熱圧着するこ
とで、積層チップの切り出し予定線5の交点に対応する
位置に貫通孔3を有する積層体が得られる。得られた積
層体を切り出し予定線5で示す線に沿ってダイシングソ
ーにより切断することで、図1に示すような、厚み方向
の4隅に符号Rで示されるR部を有する個々の積層チッ
プが得られる。その後、脱バインダーおよび、900℃
での焼結を行なった後、アルミナビーズをメディアとす
るバレル装置内で数分間という短時間の角取り処理によ
り、積層チップの外形をまるめた後、外部電極としてA
gペーストを塗布、焼付けることでサイズ5.0mm×
2.0mm×1.7mm、内部電極層数150層、容量
10μFの積層セラミックコンデンサーを得た。
FIG. 2 is a schematic view showing the structure of a laminated body for obtaining a plurality of laminated ceramic capacitor chips, wherein reference symbol a is a protective film layer on which an internal electrode layer is not printed,
Reference numeral b represents an internal electrode layer made of a green sheet on which the internal electrode pattern 4 is printed. The green sheets 1 and 2 forming a and b are made of ceramic powder and PVB.
The slurry mixed with as a binder was formed into a thickness of 20 μm by the doctor blade method, and then the size was 100 × 13.
The green sheet 2 was punched out to a thickness of 0 mm, and the green sheet 2 was formed by regularly repeating the internal electrode pattern 4 in a plane by Ag.
/ Pd paste is used for printing. As shown in FIG. 3, the green sheets 1 and 2 have punched out through-holes 3 having a rhombic section or a rhombic section with a curvature centered on the intersection of the planned cutting lines 5 (shown by dotted lines) of the laminated chip. After processing, the product is stacked in a laminated die and thermocompression bonded under the conditions of a temperature of 80 ° C. and a pressure of 200 Kg / cm 2 to obtain a laminated body having a through hole 3 at a position corresponding to the intersection of the planned cutting lines 5 of the laminated chip. Is obtained. By cutting the obtained laminated body with a dicing saw along the line indicated by the planned cutting line 5, individual laminated chips having R portions indicated by reference symbol R at four corners in the thickness direction as shown in FIG. Is obtained. After that, debinding and 900 ° C
After the sintering was performed, the outer shape of the laminated chip was rounded by a chamfering treatment in a barrel device using alumina beads as a medium for a short time of several minutes.
5.0mm x size by applying and baking g paste
A multilayer ceramic capacitor having a size of 2.0 mm × 1.7 mm, 150 internal electrode layers and a capacity of 10 μF was obtained.

【0015】この実施例において、積層チップ焼結体に
内在するデラミネーションを画像処理装置を有する超音
波探傷機を用いて、非破壊探査を行なった。また、一定
基準にて外観上のカケ発生頓度を調べた。さらに、プレ
ッシャー・クッカー・テスト(PCT)により、信頼性の
加速試験での絶縁抵抗値劣化によるショート発生率を調
べた。これらの結果について表1に、従来工法と比較し
て、纏めて示す。
In this example, delamination inherent in the laminated chip sintered body was non-destructively probed using an ultrasonic flaw detector having an image processing device. In addition, the degree of occurrence of chipping on the appearance was examined with a certain standard. Further, a pressure cooker test (PCT) was performed to examine the short-circuit occurrence rate due to the insulation resistance deterioration in the reliability acceleration test. These results are summarized in Table 1 in comparison with the conventional method.

【0016】[0016]

【表1】 [Table 1]

【0017】表1に示す様に、本発明によると、デラミ
ネーション発生率、カケ発生率およびショート発生率い
ずれについても顕著な効果があることが確認された。
As shown in Table 1, according to the present invention, it was confirmed that the delamination occurrence rate, the chipping occurrence rate, and the short-circuit occurrence rate have remarkable effects.

【0018】[0018]

【発明の効果】本発明によると、積層チップ内に発生す
るデラミネーションを解消する効果があり、また工程上
で発生するカケの防止効果があることが確認され、積層
チップ部品の信頼性を向上させることができた。
EFFECTS OF THE INVENTION According to the present invention, it has been confirmed that the delamination that occurs in a laminated chip can be eliminated and that chipping that occurs in the process can be prevented, and the reliability of laminated chip components can be improved. I was able to do it.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の積層チップを示す外観斜視図。FIG. 1 is an external perspective view showing a laminated chip of the present invention.

【図2】本発明の積層体の構成を示す外観斜視図。FIG. 2 is an external perspective view showing the structure of the laminate of the present invention.

【図3】ダミーシートおよび電極シートへの貫通孔形成
の1例を示す平面図。
FIG. 3 is a plan view showing an example of forming a through hole in a dummy sheet and an electrode sheet.

【図4】従来の積層チップを示す外観斜視図。FIG. 4 is an external perspective view showing a conventional laminated chip.

【符号の説明】[Explanation of symbols]

a 保護膜層 b 内部電極層 1 貫通孔を有するダミーシート 2 貫通孔を有する電極シート 3 貫通孔 4 内部電極パターン 5 (積層チップ)切り出し予定線 R (C又はR形状に角取りされた)R部 a protective film layer b internal electrode layer 1 dummy sheet having a through hole 2 electrode sheet having a through hole 3 through hole 4 internal electrode pattern 5 (multilayer chip) planned cutting line R (cut into a C or R shape) R Department

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 内部電極層を含む積層体から所定形状の
積層チップを切り出し焼成することで個々の積層チップ
部品を得る積層チップ部品の製造方法において、前記積
層チップの角部に切り出し工程前にあらかじめC又はR
形状の角取りを施しておくことを特徴とする積層チップ
部品の製造方法。
1. A method of manufacturing a laminated chip component, wherein a laminated chip having a predetermined shape is cut out from a laminated body including internal electrode layers and fired to obtain individual laminated chip components. C or R in advance
A method of manufacturing a laminated chip component, characterized in that the shape is chamfered.
【請求項2】 内部電極層を含む積層体から所定形状の
積層チップが切り出され焼成されて得られる積層チップ
部品において、切り出された積層チップの角部が切り出
される前にあらかじめC又はR形状の角取りがされてい
ることを特徴とする積層チップ部品。
2. A laminated chip component obtained by cutting a laminated chip having a predetermined shape from a laminated body including an internal electrode layer and firing the laminated chip, which has a C or R shape in advance before a corner of the laminated chip is cut out. A laminated chip part characterized by being chamfered.
JP23546993A 1993-08-26 1993-08-26 Manufacture of laminated chip component and laminated chip component Pending JPH0766076A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23546993A JPH0766076A (en) 1993-08-26 1993-08-26 Manufacture of laminated chip component and laminated chip component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23546993A JPH0766076A (en) 1993-08-26 1993-08-26 Manufacture of laminated chip component and laminated chip component

Publications (1)

Publication Number Publication Date
JPH0766076A true JPH0766076A (en) 1995-03-10

Family

ID=16986550

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23546993A Pending JPH0766076A (en) 1993-08-26 1993-08-26 Manufacture of laminated chip component and laminated chip component

Country Status (1)

Country Link
JP (1) JPH0766076A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6221193B1 (en) 1999-01-20 2001-04-24 International Business Machines Corporation Defect reduction method for screened greensheets and article produced therefrom
US6389680B1 (en) 1997-03-19 2002-05-21 Murata Manufacturing Co., Ltd. Method of manufacturing electronic component
KR20030062021A (en) * 2002-01-15 2003-07-23 (주) 래트론 Manufacturing method of cylindrical ceramic capacitor
JP2006229016A (en) * 2005-02-18 2006-08-31 Toko Inc Manufacturing method of laminated electronic component
JP2006321671A (en) * 2005-05-17 2006-11-30 Ngk Spark Plug Co Ltd Method for producing multilayer ceramic
JP2007173626A (en) * 2005-12-22 2007-07-05 Ngk Spark Plug Co Ltd Capacitor and manufacturing method thereof
JP2010080601A (en) * 2008-09-25 2010-04-08 Hitachi Metals Ltd Ceramic laminate component
US8304321B2 (en) 2005-12-22 2012-11-06 Ngk Spark Plug Co., Ltd. Capacitor to be incorporated in wiring substrate, method for manufacturing the capacitor, and wiring substrate
US10121585B2 (en) 2014-06-23 2018-11-06 Cyntec Co., Ltd. Method of manufacturing magnetic core elements

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US6389680B1 (en) 1997-03-19 2002-05-21 Murata Manufacturing Co., Ltd. Method of manufacturing electronic component
US6221193B1 (en) 1999-01-20 2001-04-24 International Business Machines Corporation Defect reduction method for screened greensheets and article produced therefrom
KR20030062021A (en) * 2002-01-15 2003-07-23 (주) 래트론 Manufacturing method of cylindrical ceramic capacitor
JP2006229016A (en) * 2005-02-18 2006-08-31 Toko Inc Manufacturing method of laminated electronic component
JP2006321671A (en) * 2005-05-17 2006-11-30 Ngk Spark Plug Co Ltd Method for producing multilayer ceramic
US8697534B2 (en) 2005-12-22 2014-04-15 Ngk Spark Plug Co., Ltd. Capacitor to be incorporated in wiring substrate, method for manufacturing the capacitor, and wiring substrate
US8304321B2 (en) 2005-12-22 2012-11-06 Ngk Spark Plug Co., Ltd. Capacitor to be incorporated in wiring substrate, method for manufacturing the capacitor, and wiring substrate
US8350306B2 (en) 2005-12-22 2013-01-08 Ngk Spark Plug Co., Ltd. Capacitor to be incorporated in wiring substrate, method for manufacturing the capacitor, and wiring substrate
JP2007173626A (en) * 2005-12-22 2007-07-05 Ngk Spark Plug Co Ltd Capacitor and manufacturing method thereof
JP2010080601A (en) * 2008-09-25 2010-04-08 Hitachi Metals Ltd Ceramic laminate component
US10121585B2 (en) 2014-06-23 2018-11-06 Cyntec Co., Ltd. Method of manufacturing magnetic core elements
TWI659438B (en) * 2014-06-23 2019-05-11 乾坤科技股份有限公司 Magnetic component with distributed gap and method for forming the same
US10679788B2 (en) 2014-06-23 2020-06-09 Cyntec Co., Ltd. Method of manufacturing magnetic core elements

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