WO2003025857A2 - Verfahren und anorndung zur signalverarbeitung, insbesondere der bildsignalverarbeitung - Google Patents
Verfahren und anorndung zur signalverarbeitung, insbesondere der bildsignalverarbeitung Download PDFInfo
- Publication number
- WO2003025857A2 WO2003025857A2 PCT/EP2002/010602 EP0210602W WO03025857A2 WO 2003025857 A2 WO2003025857 A2 WO 2003025857A2 EP 0210602 W EP0210602 W EP 0210602W WO 03025857 A2 WO03025857 A2 WO 03025857A2
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- WIPO (PCT)
- Prior art keywords
- stage
- polynomial
- signal processing
- arrangement
- polynomials
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/11—Complex mathematical operations for solving equations, e.g. nonlinear equations, general mathematical optimization problems
- G06F17/12—Simultaneous equations, e.g. systems of linear equations
Definitions
- the invention relates to a method and an arrangement for signal processing, in particular image signal processing according to the preamble of claims 1 and 5, respectively.
- Transformed coordinates are required if discrete signal processing is to generate and / or compensate for a distortion of the spatial and / or temporal dimension of a signal. Such signal processing works sequentially with variable coordinates. Transformed coordinates must be calculated for these input coordinates. Transformed coordinates are used to read data for signal processing and / or to store processing results.
- Transformed coordinates must be calculated for each sample of an input or output signal. Very high computing power is required for this, in particular with image data. This high computing power can be made available efficiently by an arithmetic processing unit.
- a very flexible definition of a coordinate transformation is possible using a polynomial-based formula.
- a fourth-order polynomial with an input coordinate "x" is shown as an example, which is as follows:
- the coefficients "c" determine the function of the polynomial. For a transformation of several coordinates "(x, y, z, ...)" into transformed coordinates "(x t , y t , z t , ...)", several polynomials with different coefficients have to be calculated.
- the object of the invention is to provide a method and an arrangement of the type mentioned at the outset which reduce the computation effort required.
- the invention has a number of advantages.
- the number of multiplications required is kept low and the complexity of the circuit arrangement according to the invention is reduced.
- the coordinate transformation is designed to be practically universally configurable, so that a large number of applications are supported.
- Figure 2 shows a sub-module of a circuit arrangement according to the invention according to Figure 3 or Figure 4;
- Figure 3 shows a first embodiment of a circuit arrangement according to the invention.
- Figure 4 shows a second embodiment of a circuit arrangement according to the invention.
- f (x, y) coo + corx + C ⁇ o -y + co2-x 2 + c ⁇ rx- y + c 2 oy 2 + c 0 3-x 3 + C12 -x 2 -y + C2i-x- y 2 + c 30 -y 3
- Equation 4 A circuit architecture that implements this calculation directly is shown in FIG. 1.
- the modules marked with MULT carry out a multiplication
- the modules marked with ADD carry out an addition.
- the MULT modules for multiplication are particularly complex.
- Nine multiplication modules are required to calculate Equation 4.
- Image processing applications often contain an inherent symmetry. This symmetry results, for example, from projection or image acquisition using a lens system. There is an optical axis that is in the center of the lens and therefore in the center of the image. Interference from the lens is then symmetrical about this axis. An axis of symmetry can also result from the arrangement of a projection system in relation to the surface to be projected on. This symmetry or redundancy is used and the number of multiplications is reduced. For this it may be necessary to shift the input coordinates in such a way that the axis of symmetry coincides with the zero point of the coordinates.
- the symmetries can also be determined by calculation, it being determined which coefficients c are set to zero, so that the corresponding (“second”) partial polynomials are not used in the calculation of a polynomial.
- Equation 5 use Equation 5, which requires three multiplications to calculate.
- Equation 6 results for the example from equation 6
- An efficient circuit architecture for calculating polynomial-based multidimensional coordinate transformations is based on a sub-module called PE, which is shown in FIG. 2.
- the sub-module PE receives as input the coordinates shifted on the symmetry axes, shown in the figure for two coordinates “x s ” and “y s ”.
- a coordinate is selected via a multiplexer (MUX) and made available as a multiplicand to a multiplication submodule (MULT).
- the multiplier is formed with an adder (ADD) from the sum of other inputs. These inputs are a fixed constant (const) and output signals of previous stages.
- FIG. 3 shows the circuit architecture for calculating coordinate transformations.
- the circuit architecture consists of subtractors (OFFSET) for calculating the shifted coordinates X_S, Y_S as the difference between the input coordinates X, Y and a programmable constant D_X, D_Y.
- the shifted coordinates are guided to sub-modules PE, which are arranged cascaded (stage 0, stage 1, stage 2, stage n-1, stage n).
- the outputs of a sub-module PE are connected to the inputs of one or more sub-modules PE of a subsequent stage. If a sub-module PE is connected to several subsequent sub-modules PE, these connecting lines can be configured using switches (SWITCH).
- SWITCH switches
- SWITCH pass on output signals of a PE or replace them with the value zero.
- the results of the last stage on sub-modules PE (stage 1) are combined with a final adder (ADD_F) together with another constant (const) (stage 0) and form the transformed coordinate F_OUT.
- the number of stages determines the degree of the polynomial that can be calculated with the overall circuit.
- the number of sub-modules PE per stage determines the number of non-zero coefficients that can be selected per degree of the polynomial, and thus the number of “first partial polynomials” that are calculated. “Second partial polynomials” for which the coefficients are set to zero , are not calculated due to symmetries.
- FIG. 4 shows an architecture which calculates a 5th order polynomial in accordance with equation 8.
- f (x s , ys) coo + C01 -x s + c ⁇ 0 -ys + c 02 -x s 2 + Cn x s -y s + c 20 -ys 2 +
- stage 0 processes the results of the previous stage and adds the constant c 0 o from equation 8.
- stage 1 contains two sub-modules PE, which calculate the terms of the 1st degree (x s , y s ) corresponding to c 0 ⁇ and c ⁇ 0 .
- stage 2 contains three sub-modules PE, which calculate the terms of the 2nd degree (x s 2 , x s -y s , y s 2 ) corresponding to c 02 , cn, c 2 o.
- stage 3 contains two sub-modules PE, which calculate the terms of the 3rd degree (x s 3 , x s 2 -y s , Xs7s 2 y s 3 ) corresponding to c 0 , c «, Q21, c 3 o. Since only 2 sub-modules PE are available, only 2 of the coefficients of this degree can be freely selected, ie 2 "first sub-polynomials" are calculated. The other coefficients are chosen to be zero ("second sub-polynomials).
- stage 4" contains two sub-modules PE, which have the terms of the 4th degree (x s 4 , Xs 3- y s , x s 2, ys 2. S ⁇ s 3 , y s 4 ) corresponding to c 04 ( C ⁇ 3 , Calculate C22, c 31 , c 4 o.
- the previous stage (stage 2) there are only 2 sub-modules PE, only 2 of the coefficients can be freely selected (2 "first sub-polynomials"); while the other coefficients are chosen to be zero ("Second partial polynomials").
- the stage "stage 5" contains three sub-modules PE which contain the terms of the 5th degree (x s 5 , x s 4 -y s , s 3 -ys 2 , x s 2 -y s 3 , Xs'y s 4 , y s 5 ) according to c 0 5, C ⁇ 4 , c 2 3, c 2, c 4 ⁇ , c 5 o calculate.
- 3 sub-modules PE 3 of the coefficients can be selected for values not equal to zero (three "first partial polynomials"). Since this stage is not preceded by another stage, the unused inputs of the sub-module PE are connected to the value zero.
- the adders of the sub-modules PE can then omitted and the signal denoting the constant is fed directly to the multiplication sub-module of the sub-module.
- a sub-module PE from the "stage 5" stage can not only be connected to the input of a sub-module PE ⁇ from the immediately following stage (stage 4), but also with sub-module (PE) inputs of further subsequent stages ( in Figure 3, "stage 3" and "stage 2") are connected.
- PE sub-module
- the arrangement or circuit arrangement described above with reference to FIGS. 3 and 4 can be controlled in such a way that the calculation of a polynomial is carried out by successive multiplications of first partial polynomials and second partial polynomials are not used in the calculation of the polynomial.
- CT computer-related circuit arrangement
- DE 100 52 263 A1 appliance: Liesegang electronics GmbH, Hanno- ver / Germany
- arrangement for image processing with simultaneous coordinate transformation can be part (“CT”) of the device described in DE 100 52 263 A1 (applicant: Liesegang electronics GmbH, Hanno- ver / Germany) disclosed arrangement for image processing with simultaneous coordinate transformation.
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Computational Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Data Mining & Analysis (AREA)
- Operations Research (AREA)
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Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002337121A AU2002337121A1 (en) | 2001-09-20 | 2002-09-20 | Method and arrangement for signal processing in particular image signal processing |
US10/490,352 US20050047668A1 (en) | 2001-09-20 | 2002-09-20 | Method and arrangement for signal processing particular image signal processing |
EP02772332A EP1430445A2 (de) | 2001-09-20 | 2002-09-20 | Verfahren und anorndung zur signalverarbeitung, insbesondere der bildsignalverarbeitung |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10146416.9 | 2001-09-20 | ||
DE10146416A DE10146416A1 (de) | 2001-09-20 | 2001-09-20 | Verfahren und Anordnung zur effizienten Berechnung polynombasierter Koordinatentransformationen |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2003025857A2 true WO2003025857A2 (de) | 2003-03-27 |
WO2003025857A3 WO2003025857A3 (de) | 2004-01-15 |
Family
ID=7699698
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2002/010602 WO2003025857A2 (de) | 2001-09-20 | 2002-09-20 | Verfahren und anorndung zur signalverarbeitung, insbesondere der bildsignalverarbeitung |
Country Status (6)
Country | Link |
---|---|
US (1) | US20050047668A1 (de) |
EP (1) | EP1430445A2 (de) |
AU (1) | AU2002337121A1 (de) |
DE (1) | DE10146416A1 (de) |
TW (1) | TWI233296B (de) |
WO (1) | WO2003025857A2 (de) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4502141A (en) * | 1981-09-11 | 1985-02-26 | Nippon Electric Co., Ltd. | Circuit for checking bit errors in a received BCH code succession by the use of primitive and non-primitive polynomials |
US5261034A (en) * | 1990-08-21 | 1993-11-09 | Fuji Xerox Co., Ltd. | Graphics microcomputer for generating geometric figures |
DE10052263A1 (de) * | 2000-10-21 | 2002-05-08 | Liesegang Electronics Gmbh | Verfahren und Anordnung zur Bildverarbeitung mit gleichzeitiger Koordinatentransformation |
-
2001
- 2001-09-20 DE DE10146416A patent/DE10146416A1/de not_active Withdrawn
-
2002
- 2002-09-20 AU AU2002337121A patent/AU2002337121A1/en not_active Abandoned
- 2002-09-20 US US10/490,352 patent/US20050047668A1/en not_active Abandoned
- 2002-09-20 WO PCT/EP2002/010602 patent/WO2003025857A2/de not_active Application Discontinuation
- 2002-09-20 TW TW091121563A patent/TWI233296B/zh not_active IP Right Cessation
- 2002-09-20 EP EP02772332A patent/EP1430445A2/de not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4502141A (en) * | 1981-09-11 | 1985-02-26 | Nippon Electric Co., Ltd. | Circuit for checking bit errors in a received BCH code succession by the use of primitive and non-primitive polynomials |
US5261034A (en) * | 1990-08-21 | 1993-11-09 | Fuji Xerox Co., Ltd. | Graphics microcomputer for generating geometric figures |
DE10052263A1 (de) * | 2000-10-21 | 2002-05-08 | Liesegang Electronics Gmbh | Verfahren und Anordnung zur Bildverarbeitung mit gleichzeitiger Koordinatentransformation |
Non-Patent Citations (1)
Title |
---|
WINZKER M ET AL: "VLSI CHIP SET FOR 2D HDTV SUBBAND FILTERING WITH ON-CHIP LINE MEMORIES" IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, Bd. 28, Nr. 12, 1. Dezember 1993 (1993-12-01), Seiten 1354-1361, XP000435910 ISSN: 0018-9200 * |
Also Published As
Publication number | Publication date |
---|---|
DE10146416A1 (de) | 2003-04-17 |
US20050047668A1 (en) | 2005-03-03 |
WO2003025857A3 (de) | 2004-01-15 |
TWI233296B (en) | 2005-05-21 |
EP1430445A2 (de) | 2004-06-23 |
AU2002337121A1 (en) | 2003-04-01 |
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